Jakob Stoklund Olesen
53fa56e8dc
Handle call-clobbered ymm registers on Win64.
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The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 22:59:28 +00:00
Victor Umansky
668f7ac9e4
Fix for the following bug in AVX codegen for double-to-int conversions:
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. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 08:51:39 +00:00
Craig Topper
a3937416e4
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:51:55 +00:00
Craig Topper
15388c4666
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:31:30 +00:00
Craig Topper
e566cd0f4d
Remove some more patterns by custom lowering intrinsics to target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 07:18:03 +00:00
Chris Lattner
9748479590
fix a bug I introduced in r148929, this is not a splat!
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Thanks to Eli for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 09:56:22 +00:00
Craig Topper
969ba287cd
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:43:11 +00:00
Chris Lattner
4ca829e895
use ConstantVector::getSplat in a few places.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:02:56 +00:00
Craig Topper
4bb3f34b22
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 05:37:32 +00:00
Craig Topper
bce73e0a8c
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 04:42:03 +00:00
Craig Topper
042883f5da
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 03:52:09 +00:00
Devang Patel
3b96e1fe3b
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
Elena Demikhovsky
28d7e71a30
ZERO_EXTEND operation is optimized for AVX.
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v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 13:54:13 +00:00
Craig Topper
dfc8e470b6
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 03:03:17 +00:00
Devang Patel
392ad6d8aa
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:56:33 +00:00
Devang Patel
f2d213745e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 22:35:25 +00:00
Devang Patel
3e08131185
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 20:20:06 +00:00
Devang Patel
7c64fe651a
Intel syntax: Parse segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 18:31:58 +00:00
Craig Topper
7925e2555d
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 08:18:28 +00:00
Craig Topper
7fb8b0c5d3
Update more places to use target specific nodes for vector shifts instead of intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 06:46:22 +00:00
Craig Topper
80e46360e9
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 06:16:53 +00:00
Craig Topper
2b21fbaf11
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 00:06:44 +00:00
Craig Topper
1906d32e55
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 19:15:14 +00:00
Craig Topper
07a276277f
Make code a little less verbose.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 03:07:48 +00:00
Craig Topper
6a32b6f0c0
Remove unused X86 ISD node type defines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 01:15:56 +00:00
Craig Topper
6fdf3d54d2
Move some vector shift patterns into their instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 00:41:20 +00:00
Craig Topper
babb1459f3
Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148641 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 18:37:15 +00:00
Benjamin Kramer
8608cc9473
Remove unused variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 10:42:44 +00:00
Craig Topper
d9ec725db4
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 08:49:33 +00:00
Devang Patel
1aea430b88
Intel syntax: Robustify register parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
David Blaikie
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Devang Patel
fdd3b30151
Intel syntax: Parse ... PTR [-8]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
Craig Topper
8f35c13842
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 09:29:03 +00:00
Craig Topper
0e2037ba2b
Add support for selecting 256-bit PALIGNR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 05:53:00 +00:00
Eli Friedman
9a2478ac1a
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 00:05:46 +00:00
Devang Patel
a951f77ca3
Post process 'and', 'sub' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380
Intel syntax: There is no need to create unary expr for simple negative displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
Craig Topper
40385c8104
Folding table additions and fixes for AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:50:38 +00:00
Craig Topper
1a7700a3fa
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:19:12 +00:00
Nick Lewycky
22de16dc75
Add a TargetOption for disabling tail calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
c38c4561cd
Add experimental -x86-use-regmask command line option.
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It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
71f0fc1ca8
Ignore register mask operands when lowering instructions to MC.
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This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 23:52:19 +00:00
Devang Patel
b8ba13f009
Process instructions after match to select alternative encoding which may be more desirable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:42:29 +00:00
Jim Grosbach
ec3433852d
Tidy up. MCAsmBackend naming conventions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
31867660cb
Add a CoveredBySubRegs property to Register descriptions.
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When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
0bd2ae92b0
Move X86 callee saved register lists to the X86CallConv .td file.
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Add a trivial implementation of the getCallPreservedMask() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:47:01 +00:00
Devang Patel
2f8af1d643
Intel syntax: Fix parser match class to check memory operand size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:48:03 +00:00
Devang Patel
6220fea2a8
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:25:10 +00:00
Devang Patel
bc51e501a0
Untabify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:09:22 +00:00
Devang Patel
9a3d293cf3
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:08:07 +00:00
Devang Patel
d37ad247cc
Intel syntax: Robustify memory operand parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:00:18 +00:00
Nadav Rotem
a16d441430
Fix warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 09:31:09 +00:00
Nadav Rotem
0b94b5f52b
Fix 11769.
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In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 09:13:19 +00:00
Craig Topper
8b5a6b63dd
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 08:23:44 +00:00
Craig Topper
37c2677fbc
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 04:44:50 +00:00
Eli Friedman
1857b51ef5
Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 16:42:21 +00:00
Eli Friedman
a20b71518a
Get rid of unused codegen-only instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148239 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 16:29:35 +00:00
Craig Topper
b7ab7fe053
Give priority to AVX over SSE for 128-bit floating point unpck instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 09:56:42 +00:00
Nadav Rotem
cc6165695f
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
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We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.
Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15 19:27:55 +00:00
Benjamin Kramer
ed4c8c633c
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15 13:16:05 +00:00
Craig Topper
d07ef50ca1
Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14 18:29:57 +00:00
Craig Topper
446626d236
Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14 18:14:53 +00:00
Chad Rosier
d32d3b758f
Fix pasto from r146196.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14 01:50:21 +00:00
Devang Patel
85d5aaecd0
Revert r148131, it was committed before it was ready.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 19:28:58 +00:00
Devang Patel
c798cc4283
Refactor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 19:12:18 +00:00
Craig Topper
0518970dc8
Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 09:21:41 +00:00
Craig Topper
562659ff6b
use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 08:32:21 +00:00
Craig Topper
12216172c0
Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 08:12:35 +00:00
Craig Topper
c30432ab57
Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 06:59:47 +00:00
Craig Topper
b9c7f652d7
Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 06:12:41 +00:00
Craig Topper
e6cf4a070d
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 05:04:25 +00:00
Bill Wendling
b4ee5168ab
Fix off-by-one error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 00:41:53 +00:00
Bill Wendling
86b1a7d614
Fix the code that was WRONG.
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The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 23:05:03 +00:00
Elena Demikhovsky
16db710898
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
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lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 20:33:10 +00:00
Rafael Espindola
85b9d43d4c
Support segmented stacks on 64-bit FreeBSD.
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This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 20:24:30 +00:00
Rafael Espindola
e4d18de5d1
Support segmented stacks on win32.
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Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 20:22:08 +00:00
Devang Patel
dd929fc704
Rename X86ATTAsmParser -> X86AsmParser
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We are using one parser to parse att as well as intel style syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 18:03:40 +00:00
Benjamin Kramer
e2eb92578a
After Jakob's r147938 exception handling on i386 was completely broken.
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Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.
This should fix nightly tester failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 17:37:18 +00:00
Nadav Rotem
d2070b00ef
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
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The attached testcase was stuck in an endless loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 15:31:55 +00:00
Benjamin Kramer
fb418bab97
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 12:41:34 +00:00
Devang Patel
c59d9df248
Add predicate method check match memory operand size, if available.
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In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 01:51:42 +00:00
Devang Patel
0a338868b7
Add intel style operand parser skeleton.
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This is a work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 01:36:43 +00:00
Chandler Carruth
0fe9a92b33
Switch all of the uses of my InsertDAGNode helper to follow the exact
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same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.
I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.
I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 01:34:44 +00:00
Rafael Espindola
2028b793e1
Support segmented stacks on mac.
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This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support
frames with static size
Patch by Brian Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 19:00:37 +00:00
Rafael Espindola
25cd4ff97e
Generate the segmented stack prologue for fastcc too.
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Patch by Brian Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 18:41:19 +00:00
Chandler Carruth
11f0e7b158
Revert r147945 which disabled an addressing mode transformation. I had
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hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.
If anyone else is seeing failures, please let me know!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 18:36:12 +00:00
Rafael Espindola
313c703831
Use unsigned comparison in segmented stack prologue.
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This is a comparison of two addresses, and GCC does the comparison unsigned.
Patch by Brian Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 18:23:35 +00:00
Rafael Espindola
014f7a3b37
Explicitly set the scale to 1 on some segstack prologue instrs.
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Patch by Brian Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 18:14:03 +00:00
Jan Sjödin
46df3adb4e
Add XOP Intrinsics and tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 15:20:20 +00:00
Nadav Rotem
394a1f53b9
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 14:07:51 +00:00
Chandler Carruth
e4bc80a14b
Disable the transformation I added in r147936 to see if it fixes some
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strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 12:17:47 +00:00
Chandler Carruth
d65a9106cd
Hoist a really redundant code pattern into a helper function, and delete
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lots of lines of code. No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147942 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 11:04:36 +00:00
Chandler Carruth
93b7358fc9
Simplify the AND-rooted mask+shift checking code to match that of the
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SRL-rooted code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 09:35:04 +00:00
Chandler Carruth
dddcd78e24
Unify the interface of the three mask+shift transform helpers, and
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factor the differences that were hiding in one of them into its other
caller, the SRL handling code. No change in behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 09:35:02 +00:00
Chandler Carruth
fde2c1a4c6
Clarify and make explicit some of the requirements for transforming
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mask+shift pairs at the beginning of the ISD::AND case block, and then
hoist the final pattern into a helper function, simplifying and
reflowing it appropriately. This should have no observable behavior
change, but several simplifications fell out of this such as directly
computing the new mask constant, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 09:35:00 +00:00
Jakob Stoklund Olesen
dec1f99615
Fix undefined code and reenable test case.
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I don't think the compact encoding code is right, but at least is has
defined behavior now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 09:08:04 +00:00