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f20da7e1a7
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11802 Commits

Author SHA1 Message Date
Evan Cheng
f20da7e1a7 Added support for ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24638 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 04:28:48 +00:00
Evan Cheng
670fd8f8dd Added explicit type field to ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24637 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:15:07 +00:00
Evan Cheng
ec693f77c0 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24635 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:01:35 +00:00
Nate Begeman
cc827e60b6 Fix a crash where ConstantVec nodes were being generated with the wrong 
type when the target did not support them.  Also teach Legalize how to
expand ConstantVecs.

This allows us to generate

_test:
        lwz r2, 12(r3)
        lwz r4, 8(r3)
        lwz r5, 4(r3)
        lwz r6, 0(r3)
        addi r2, r2, 4
        addi r4, r4, 3
        addi r5, r5, 2
        addi r6, r6, 1
        stw r2, 12(r3)
        stw r4, 8(r3)
        stw r5, 4(r3)
        stw r6, 0(r3)
        blr

For:

void %test(%v4i *%P) {
        %T = load %v4i* %P
        %S = add %v4i %T, <int 1, int 2, int 3, int 4>
        store %v4i %S, %v4i * %P
        ret void
}

On PowerPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24633 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-07 19:48:11 +00:00
Chris Lattner
cc2210b4fa Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or 
if the target supports the resultant sextinreg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24632 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-07 18:02:05 +00:00
Chris Lattner
e80242a948 X86 doesn't support sextinreg for 8-bit things either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24631 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-07 17:59:14 +00:00
Chris Lattner
b14ab8a10d Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg 
when the types match up.  This allows the X86 backend to compile:

sbyte %toggle_value(sbyte* %tmp.1) {
        %tmp.2 = load sbyte* %tmp.1
        ret sbyte %tmp.2
}

to this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        ret

instead of this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        movsx %EAX, %AL
        ret

noticed in Shootout/objinst.

-Chris


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24630 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-07 07:11:03 +00:00
Andrew Lenharth
bbe1225bf4 fix divide and remainder 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24628 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 23:27:39 +00:00
Chris Lattner
85961d5ec1 Silence another annoying GCC warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24627 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 20:56:18 +00:00
Andrew Lenharth
f88471ded7 more decent branches for FP. I might have to make some intermediate nodes to actually be able to use the DAG for FPcmp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24625 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 20:43:30 +00:00
Andrew Lenharth
cfb2815695 OK, this does wonders for broken stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24624 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 20:40:34 +00:00
Sumant Kowshik
8a3802d5b2 Collapsing node if variable length struct with final field of length zero 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24621 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 18:04:30 +00:00
Chris Lattner
ed74a4ef3b Fix test/Regression/Linker/2005-12-06-AppendingZeroLengthArrays.ll and 
PR662.  Thanks to Markus for providing me with a ton of files to
reproduce the problem!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24619 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 17:30:58 +00:00
Nate Begeman
8cfa57b1b4 Teach the SelectionDAG ISel how to turn ConstantPacked values into 
constant nodes with vector types.  Also teach the asm printer how to print
ConstantPacked constant pool entries.  This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0:  <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
        .space  4
        .space  4
        .space  4
        .long   1065353216      ; float 1
        .text
        .align  4
        .globl  _foo
_foo:
        lis r2, ha16(LCPI1_0)
        la r2, lo16(LCPI1_0)(r2)
        li r4, 0
        lvx v0, r4, r2
        lvx v1, r4, r3
        vaddfp v0, v1, v0
        stvx v0, r4, r3
        blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24616 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 06:18:55 +00:00
Chris Lattner
4172b10ca1 Use new PPC-specific nodes to represent shifts which require the 6-bit 
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 02:10:38 +00:00
Andrew Lenharth
eda80a0dec added instructions with inverted immediates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24614 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 00:33:53 +00:00
Andrew Lenharth
8a3a5fc9ba yea, it helps to have your path set right when testing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24613 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 23:41:45 +00:00
Andrew Lenharth
5de36f95da These never trigger, but whatever 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24612 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 23:19:44 +00:00
Evan Cheng
8d202230b4 Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24611 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 23:09:43 +00:00
Andrew Lenharth
7962065fdb move this over to the dag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24609 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 20:50:53 +00:00
Chris Lattner
e08dc62b1a getRawValue zero extens for unsigned values, use getsextvalue so that we 
know that small negative values fit into the immediate field of addressing
modes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24608 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 18:23:57 +00:00
Andrew Lenharth
b457a93123 fix constant pool loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24607 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 17:51:02 +00:00
Chris Lattner
c88d8e944d Fix the #1 code quality problem that I have seen on X86 (and it also affects 
PPC and other targets).  In a particular, consider code like this:

struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
   return a.x * b.x  +  a.y * b.y  +  a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
   Vector3 r;
   r.x = dot( a, b.a );
   r.y = dot( a, b.b );
   r.z = dot( a, b.c );
   return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
   for (int i = 0; i < n; i++)
      x[i] = mul( x[i], m );
}

we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them).  Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:

LBB3_1: ; no_exit.preheader
        li r2, 0
        addi r6, r3, 64        ;; 9 values live across the loop body!
        addi r7, r3, 56
        addi r8, r3, 48
        addi r9, r3, 40
        addi r10, r3, 32
        addi r11, r3, 24
        addi r12, r3, 16
        addi r30, r3, 8
LBB3_2: ; no_exit
        lfd f0, 0(r30)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)        ;; no constant indices folded into the loads!
        lfd f3, 0(r4)
        lfd f4, 0(r10)
        lfd f5, 0(r6)
        lfd f6, 0(r7)
        lfd f7, 0(r8)
        lfd f8, 0(r9)
        lfd f9, 0(r11)
        lfd f10, 0(r12)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r29, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r29, r29
        bne cr0, LBB3_2 ; no_exit

uh, yuck.  With this patch, we now sink the constant offsets into the loop, producing
this code:

LBB3_1: ; no_exit.preheader
        li r2, 0
LBB3_2: ; no_exit
        lfd f0, 8(r3)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)
        lfd f3, 0(r4)
        lfd f4, 32(r3)       ;; much nicer.
        lfd f5, 64(r3)
        lfd f6, 56(r3)
        lfd f7, 48(r3)
        lfd f8, 40(r3)
        lfd f9, 24(r3)
        lfd f10, 16(r3)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r6, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r6, r6
        bne cr0, LBB3_2 ; no_exit

This is much nicer as it reduces register pressure in the loop a lot.  On X86,
this takes the function from having 9 spilled registers to 2.  This should help
some spec programs on X86 (gzip?)

This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 07:10:48 +00:00
Chris Lattner
30614675f4 Add a flag to Module::getGlobalVariable to allow it to return vars with 
internal linkage.

Patch provided by Evan Jones, thanks!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24604 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 05:30:21 +00:00
Chris Lattner
6b44ba2803 Wrap a long line, never internalize llvm.used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24602 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 05:07:38 +00:00
Chris Lattner
3d36a9f6f4 Several things: 
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24599 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:40:25 +00:00
Chris Lattner
68bfd9c1e8 On some targets (e.g. X86), shift amounts are not the same as the value 
being shifted.  Don't assume they are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24598 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:37:26 +00:00
Chris Lattner
b5d01436e3 Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24595 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:34:29 +00:00
Chris Lattner
bd05982b48 Add some explicit type casts so that tblgen knows the type of the shift 
amount, which is not necessarily the same as the type being shifted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24594 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:34:05 +00:00
Chris Lattner
bead6612a5 The basic fneg cases are already autogen'd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24592 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 19:04:38 +00:00
Chris Lattner
937a79dbe3 Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen 
improvements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 19:01:59 +00:00
Chris Lattner
60a4ab2d5c Finish moving uncond br over to .td file, remove from .cpp file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 18:48:01 +00:00
Chris Lattner
1e48478557 Define BR in the .td file now that Evan made tblgen smarter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 18:42:54 +00:00
Evan Cheng
d35b8c1adb Added isel patterns for RET, JMP, and WRITEPORT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24588 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 08:19:43 +00:00
Evan Cheng
f8ac814957 * Added instruction property hasCtrlDep for those which r/w control-flow 
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 08:13:17 +00:00
Chris Lattner
df65de42cf Fix PR672 another way which should be more robust 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24585 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 06:03:50 +00:00
Chris Lattner
d67b3a8bf7 dbg.stoppoint returns a value, don't forget to init it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24583 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-03 18:50:48 +00:00
Chris Lattner
8e75ee212f Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24581 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-03 18:25:58 +00:00
Chris Lattner
a027ba885a Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672. 
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24578 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-03 07:15:55 +00:00
Andrew Lenharth
cde0f5cfe7 bah, must generate all results 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24574 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-02 06:08:08 +00:00
Andrew Lenharth
49c709f891 cycle counter fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24573 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-02 04:56:24 +00:00
Chris Lattner
865874c88a add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24572 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-02 00:11:20 +00:00
Chris Lattner
fe14b34d83 Don't remove two operand, two result nodes from the binary ops map. These 
should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24571 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 23:14:50 +00:00
Chris Lattner
9ad17c9c9a Promote line and column number information for our friendly 64-bit targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24568 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 18:21:35 +00:00
Chris Lattner
18c778f8be IA64 doesn't support the LOCATION node, and for some reason the ISelPattern 
stuff isn't using ISelLowering.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24567 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 18:19:53 +00:00
Chris Lattner
05f56a529c Make sure these get added into the codegenmap when appropriate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24566 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 18:09:22 +00:00
Chris Lattner
c5e6c649b5 This is a bugfix for SelectNodeTo. In certain situations, we could be 
selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24565 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 18:00:57 +00:00
Andrew Lenharth
6251b36d88 major think-o 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24564 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 17:48:51 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:51:06 +00:00
Nate Begeman
5dfc55c304 Cosmetic change, better reflects actual values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24562 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:48:26 +00:00