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52132 Commits

Author SHA1 Message Date
Akira Hatanaka
cb9dd72fdc Have getRegForInlineAsmConstraint return the correct register class when target 
is Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 02:45:01 +00:00
Evan Cheng
afad0fe59a Fix more places which should be checking for iOS, not darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 01:55:04 +00:00
Evan Cheng
56f582d664 For x86, canonicalize max 
(x > y) ? x : y
=>
(x >= y) ? x : y

So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0

This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl   %esi, %edi
testl  %edi, %edi
movl   $0, %eax
cmovgl %edi, %eax
=>
xorl   %eax, %eax
subl   %esi, $edi
cmovsl %eax, %edi

rdar://10633221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147512 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-04 01:41:39 +00:00
Chris Lattner
fcd7090063 Turn a few more inline asm errors into "emitErrors" instead of fatal errors. 
Before we'd get:

$ clang t.c 
fatal error: error in backend: Invalid operand for inline asm constraint 'i'!

Now we get:

$ clang t.c
t.c:16:5: error: invalid operand for inline asm constraint 'i'!
    "movq         (%4), %%mm0\n"
    ^

Which at least gets us the inline asm that is the problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147502 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 23:51:01 +00:00
Chris Lattner
3a4c60ca3b generalize LLVMContext::emitError to take a twine instead of a StringRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147501 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 23:47:05 +00:00
Chad Rosier
b90d2a9046 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 23:19:12 +00:00
Jakob Stoklund Olesen
6d5b7cc235 Revert r146997, "Heed spill slot alignment on ARM." 
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 22:34:35 +00:00
Jakob Stoklund Olesen
2d44e02533 Assert when reserved registers have been assigned. 
This can only happen if the set of reserved registers changes during
register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147486 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 22:34:31 +00:00
Nadav Rotem
c2d064f028 Revert 147426 because it caused pr11696. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 22:19:42 +00:00
Nadav Rotem
316477dd54 Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 22:12:28 +00:00
Chad Rosier
3d1161e9ae Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather 
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147481 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 21:05:52 +00:00
Nick Lewycky
48a09aec60 Conform to the style guide; remove 'else' after 'return'. Also remove an extra 
if-statement by turning it into an assert. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147474 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 20:33:00 +00:00
Owen Anderson
517c4d7fda Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147472 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 20:09:02 +00:00
Lang Hames
567cdbab28 Clarified assert text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147471 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 20:05:57 +00:00
Matt Beaumont-Gay
19055cc271 Fix malformed assert. 
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 19:03:59 +00:00
Nick Lewycky
5eb2e957b3 Fix typo in ruler. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147454 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 18:22:43 +00:00
Devang Patel
b1666b971e Intel style asm variant does not need '%' prefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 18:22:10 +00:00
Stepan Dyatkovskiy
bd47f59afa Type: replaced usage of ID with getTypeID(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147446 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 14:05:04 +00:00
Elena Demikhovsky
ce58a03587 Fixed a bug in SelectionDAG.cpp. 
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147445 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 11:59:04 +00:00
Andrew Trick
0f8cd56bfd Fix SCEVExpander to handle loops with no preheader when LSR gives it a 
"phony" insertion point.

Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 21:25:10 +00:00
Craig Topper
c612d79817 Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147430 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 09:17:37 +00:00
Craig Topper
a51bb3aa75 Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147428 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 08:46:48 +00:00
Nadav Rotem
a46f35d3d6 Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 08:05:46 +00:00
Rafael Espindola
47f79bb58e Materialize functions whose basic blocks are used by global variables. Fixes 
PR11677.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147425 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-02 07:49:53 +00:00
Craig Topper
a86bcfb565 Allow CRC32 instructions to be selected when AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 19:51:58 +00:00
Craig Topper
de9e4c728e Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 19:40:22 +00:00
Benjamin Kramer
8943574b44 X86Disassembler: Fix undefined behavior found by GCC 4.6 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147404 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 17:55:36 +00:00
Benjamin Kramer
55c6d57734 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147403 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 17:55:30 +00:00
Rafael Espindola
acae2a63b9 Revert 147399. It broke CodeGen/ARM/vext.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147400 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 17:36:23 +00:00
Elena Demikhovsky
ac12855066 Fixed a bug in SelectionDAG.cpp. 
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147399 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 16:22:47 +00:00
Craig Topper
b3982da7d2 Merge X86 SHUFPS and SHUFPD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:50:21 +00:00
Craig Topper
3ee6d22c78 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:24:49 +00:00
Craig Topper
e00805d52f Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 23:15:11 +00:00
Nick Lewycky
57ed0948b8 Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the 
'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 21:30:22 +00:00
Dylan Noblesmith
ccc9a59614 VMCore: add assert for miscompile 
See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.

This makes the source of the bug more obvious
than the other asserts triggering later on did.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 13:58:58 +00:00
Bruno Cardoso Lopes
ce8524c016 Cleanup Mips code and rename some variables. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
3aa035fa0c Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147382 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:04:30 +00:00
Craig Topper
7ba2725f5d Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 07:16:00 +00:00
Craig Topper
06f554d06a Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9 Combine FMA4 SS/SD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b Combine FMA4 PS/PD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 01:49:53 +00:00
Hal Finkel
2e95afa04c Cleanup stack/frame register define/kill states. This fixes two bugs: 
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 00:34:00 +00:00
Rafael Espindola
ed23bdb65f Implement cfi_restore. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 21:43:03 +00:00
Rafael Espindola
c25680f728 Rename Remember and Restore to RememberState and RestoreState for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 21:09:08 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Rafael Espindola
6f0b181bc7 Implement .cfi_escape. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:24:47 +00:00