6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-17 03:30:28 +00:00
Code Issues Projects Releases Wiki Activity
45,707 Commits 39 Branches 0 Tags 277 MiB
f41fcbb60d
Commit Graph

37 Commits

Author SHA1 Message Date
Evan Cheng
ffa6d962a7 Handle the rest of pseudo instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-13 23:36:57 +00:00
Evan Cheng
148cad8b30 Fix pre- and post-indexed load / store encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-13 07:34:59 +00:00
Evan Cheng
3c4a4ffa3d Consolidate formats; fix FCMPED etc. encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 07:18:38 +00:00
Evan Cheng
80a119842d Fix VFP conversion instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 06:41:41 +00:00
Evan Cheng
0a0ab1387a Fix FMDRR encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 22:46:12 +00:00
Evan Cheng
cd8e66a1ef Encode VFP load / store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 21:48:44 +00:00
Evan Cheng
78be83d7c2 Encode VFP conversion instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 19:40:26 +00:00
Evan Cheng
96581d3633 Encode VFP arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-11 02:11:05 +00:00
Evan Cheng
4df60f5491 Jump table JIT support. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 09:06:08 +00:00
Evan Cheng
8b59db3f2c Encode misc arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 01:41:35 +00:00
Evan Cheng
97f48c39fd Encode extend instructions; more clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 22:15:19 +00:00
Evan Cheng
12c3a533c5 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 17:48:05 +00:00
Evan Cheng
d87293ce78 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 08:47:38 +00:00
Evan Cheng
eb4f52eb62 Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 03:35:07 +00:00
Evan Cheng
fbc9d412ef Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 01:21:28 +00:00
Evan Cheng
83b5cf0272 Encode pic load / store instructions; fix some encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 23:22:34 +00:00
Evan Cheng
edda31c412 Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 18:35:52 +00:00
Evan Cheng
e7fe672445 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 17:57:07 +00:00
Jim Grosbach
0a4b9dc9b1 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 18:38:31 +00:00
Jim Grosbach
2642196a65 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-14 20:36:24 +00:00
Evan Cheng
7fd7ca4e7f Fix addrmode1 instruction encodings; fix bx_ret encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-17 07:53:38 +00:00
Evan Cheng
29c57c34ef Specify instruction encoding using range list to avoid endianess issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-17 07:16:21 +00:00
Evan Cheng
05fc966401 Revert 56176. All those instruction formats are still needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-13 01:35:33 +00:00
Evan Cheng
a964b7dffe Eliminate unnecessary instruction formats. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 23:15:39 +00:00
Evan Cheng
49a9f2958d Addrmode 1 S bit can be dynamically set. Look for CPSR def. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56172 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 22:45:55 +00:00
Evan Cheng
3aac788365 Control flow instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b ldm / stm instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d AXI2 and AXI3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:34:13 +00:00
Evan Cheng
4bbd5f8a9c Reorganize instruction formats again; AXI1 encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:19:00 +00:00
Evan Cheng
840917be2c addrmode3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:00:14 +00:00
Evan Cheng
0d14fc8cd5 Reorganize some instruction format definitions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 01:51:14 +00:00
Evan Cheng
93912739c9 Rest of addrmode2 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec Addr2 word / byte load encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 19:02:21 +00:00
Evan Cheng
b7880ac470 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 18:32:16 +00:00
Evan Cheng
612b79edc9 addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 07:40:52 +00:00
Evan Cheng
130966411f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 06:41:12 +00:00
Evan Cheng
37f25d989a Refactor ARM instruction format definitions into a separate file. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:39:26 +00:00