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51 Commits

Author SHA1 Message Date
Devang Patel
1e86a66b00 mv CodeGen/DebugLoc.h Support/DebugLoc.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73786 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 22:08:58 +00:00
Bill Wendling
df7d5d3170 Temporarily revert r72191. It was causing an assert during llvm-gcc 
bootstrapping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-21 00:04:55 +00:00
Argyrios Kyrtzidis
a3437647dc Introduce DebugScope which gets embedded into the machine instructions' DebugLoc. 
DebugScope refers to a debug region, function or block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-20 22:57:17 +00:00
Devang Patel
390f3ace34 If FastISel is run and it has known DebugLoc then use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69253 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-16 01:33:10 +00:00
Chris Lattner
c5040ab606 optimize FastISel::UpdateValueMap to avoid duplicate map lookups, 
and make it return the assigned register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68888 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-12 07:45:01 +00:00
Dan Gohman
14ea1ec232 Fix FastISel's assumption that i1 values are always zero-extended 
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-13 20:42:20 +00:00
Bill Wendling
9bc96a5720 Create DebugLoc information in FastISel. Several temporary methods were 
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63584 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-03 00:55:04 +00:00
Evan Cheng
536ab130ec Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 09:10:11 +00:00
Devang Patel
83489bb770 Use DebugInfo interface to lower dbg_* intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 00:35:13 +00:00
Dan Gohman
d68a07650c Tidy up #includes, deleting a bunch of unnecessary #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-05 17:59:02 +00:00
Dan Gohman
c8a1a3c426 Factor out the code for sign-extending/truncating gep indices 
and use it in x86 address mode folding. Also, make
getRegForValue return 0 for illegal types even if it has a
ValueMap for them, because Argument values are put in the
ValueMap. This fixes PR3181.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60696 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-08 07:57:47 +00:00
Dan Gohman
dd5b58ad7b FastISel support for exception-handling constructs. 
- Move the EH landing-pad code and adjust it so that it works
   with FastISel as well as with SDISel.
 - Add FastISel support for @llvm.eh.exception and
   @llvm.eh.selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-14 23:54:11 +00:00
Dan Gohman
241f464d24 Fix fast-isel's handling of atomic instructions. They may 
expand to multiple basic blocks, in which case fast-isel
needs to informed of which block to use as it resumes
inserting instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57040 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-04 00:56:36 +00:00
Dan Gohman
d98d6203e4 Optimize conditional branches in X86FastISel. This replaces 
sequences like this:
       sete    %al
       testb   %al, %al
       jne     LBB11_1
with this:
       je      LBB11_1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56969 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-02 22:15:21 +00:00
Dan Gohman
a43abd102f Fix FastISel to not initialize the PIC-base register multiple times 
in functions with PIC references from more than one basic block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56807 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-29 21:55:50 +00:00
Dan Gohman
33134c4a75 FastISel support for debug info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56610 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-25 17:05:24 +00:00
Dan Gohman
d57dd5f4e6 Arrange for FastISel code to have access to the MachineModuleInfo 
object. This will be needed to support debug info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56508 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-23 21:53:34 +00:00
Dan Gohman
0586d91bb3 Add X86FastISel support for static allocas, and refences 
to static allocas. As part of this change, refactor the
address mode code for laods and stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56066 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-10 20:11:02 +00:00
Evan Cheng
59fbc80f6b Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55975 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-09 01:26:59 +00:00
Owen Anderson
9c7216f984 Rename method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55853 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 20:49:33 +00:00
Dan Gohman
40b189e4e2 FastISel support for ConstantExprs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55843 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:18:20 +00:00
Owen Anderson
95267a1e67 Add initial support for selecting constant materializations that require constant 
pool loads on X86 in fast isel.  This isn't actually used yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 00:06:23 +00:00
Dan Gohman
104e4ce162 Do trivial local CSE for constants and other non-Instruction values 
in FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:32:19 +00:00
Dan Gohman
3df24e667f Create HandlePHINodesInSuccessorBlocksFast, a version of 
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:12:08 +00:00
Evan Cheng
ea09f4f469 Make UpdateValueMap, createResultReg, etc. protected instead of private so they can used by target hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55691 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 06:43:10 +00:00
Owen Anderson
cc54e76cc6 Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg 
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 00:38:46 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:21:34 +00:00
Owen Anderson
40a468f249 FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55476 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 17:47:37 +00:00
Owen Anderson
8970f00def Add a helper method that will be used to support EXTRACT_SUBREG for selecting trunc's in fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55439 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 22:30:02 +00:00
Dan Gohman
ad368ac2b5 Add a new FastISel method, getRegForValue, which takes care of 
the details of materializing constants and other values into
registers, and make use of it in several places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55426 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 18:10:19 +00:00
Dan Gohman
10df0fa73e Basic FastISel support for floating-point constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 01:09:54 +00:00
Owen Anderson
d0533c9998 Factor out a large amoutn of the cast handling code in fast isel into helper methods. 
This simultaneously makes the code simpler and adds support for sext as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55398 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 23:46:32 +00:00
Dan Gohman
763d89343b Refactor the bitcast code into its own function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55387 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 21:28:54 +00:00
Owen Anderson
0f84e4e310 Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return 
type down.  This is not currently used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55345 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 23:58:18 +00:00
Owen Anderson
6d0c25ec3a Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55325 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 20:20:32 +00:00
Dan Gohman
6ecf50908c Make MBBMap a DenseMap instead of a std::map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55220 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 02:44:46 +00:00
Dan Gohman
3c8f36fd03 Reapply r55191 and r55192. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55205 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 21:28:19 +00:00
Bill Wendling
449416deb6 Reverting r55190, r55191, and r55192. They broke the build with this error message: 
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 20:51:05 +00:00
Dan Gohman
e0182ec0e4 Support non-fallthrough unconditional branches in FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55191 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 19:21:41 +00:00
Owen Anderson
a794ef7f5d Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55189 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 18:26:07 +00:00
Dan Gohman
22bb31103d Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 00:20:26 +00:00
Dan Gohman
d5fe57d2f9 Basic fast-isel support for instructions with constant int operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55099 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 01:41:07 +00:00
Dan Gohman
7f92ebddd2 Improve the doxygen comment for SelectInstructions::SelectInstructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55094 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 00:19:43 +00:00
Dan Gohman
c7f72de3b4 Begin making more use of the FastISelEmitter class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55093 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 00:19:05 +00:00
Evan Cheng
83785c8096 First cut, un-optimized (and untested) fast isel lowering of GetElementPtrInst. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55085 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 22:45:34 +00:00
Dan Gohman
bb466331e7 Simplify FastISel's constructor argument list, make the FastISel 
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 21:05:57 +00:00
Dan Gohman
cc8430f742 Fix a leak in the FastISel code that Chris pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55031 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:56:17 +00:00
Dan Gohman
bdedd44773 Add FastISel support for several more binary operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55020 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:11:48 +00:00
Dan Gohman
40610241d0 Fix the FastISel class' doxygen comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54957 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-18 23:41:46 +00:00
Dan Gohman
e285a74f7c Make FastISel's constructor protected, and give it a destructor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54793 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-14 21:51:29 +00:00