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151 Commits 4 Branches 32 Tags 7.4 MiB
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16 Commits

Author SHA1 Message Date
marqs 4676cbd2f0 integrate zero-riscy 2018-10-06 13:19:12 +03:00
marqs e1d8446752 BSP and sw modifications 2018-09-26 00:19:24 +03:00
marqs 37650ca22b misc improvements 
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
 2018-03-28 20:09:40 +03:00
marqs dd4ffde231 update to Quartus 17.1 2017-12-07 21:35:08 +02:00
marqs a24d6b0e3a Update latency tester 
* Enable operation with all sources
* Measure strobe length on low-persistence displays
 2017-10-28 12:10:54 +03:00
marqs 1bf279b2a7 Initial latency tester implementation 2017-10-22 22:45:29 +03:00
paulb-nl ac16008076 Add reverse LPF feature 
reverse LPF can be used to mostly reverse the blur on pre 1-CHIP SNES.
For best results use 256x240 optimized mode.
 2017-09-27 22:43:26 +02:00
marqs 4f36278cb7 Sync processing rewritten and some issues fixed 
* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
 2017-05-18 23:36:37 +03:00
marqs 434186d64e Improve lo-res mode processing features 
* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
 2017-01-23 00:56:17 +02:00
marqs d77c293b70 * Clean up some FPGA code 
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
 2016-12-31 14:18:21 +02:00
marqs 03bf4c2c9a Update to Quartus 16.1. 2016-12-13 20:55:10 +02:00
marqs f55e9a877e SD SPI implementation finished 2016-10-21 01:19:53 +03:00
marqs 71d60144e8 Timer and SPI added. 2016-10-16 12:53:54 +03:00
marqs c83653c880 Release 0.69 
* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
 2016-04-15 22:05:53 +03:00
marqs f502b2e46c Release 0.67. 
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
 2016-03-27 23:09:31 +03:00
marqs 388c464f63 Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00