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MAX, MachXO, MachXO2 working

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This commit is contained in:
Zane Kaminski 2023-08-20 07:10:11 -04:00
parent 43e816b74c
commit a59177004e
545 changed files with 317413 additions and 205635 deletions
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18
CPLD/LCMXO2-640HC/.run_manager.ini
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@ -1,9 +1,9 @@
[Runmanager] [Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E] [impl1%3CStrategy1%3E]
isChecked=false isChecked=false
isHidden=false isHidden=false
isExpanded=false isExpanded=false

7
CPLD/LCMXO2-640HC/.setting.ini
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@ -1,3 +1,4 @@
[General] [General]
Export.auto_tasks=Jedecgen Export.auto_tasks=IBIS, TimingSimFileVlg, TimingSimFileVHD, Bitgen, Jedecgen
PAR.auto_tasks=@@empty() PAR.auto_tasks=PARTrace, IOTiming
Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile

3
CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf
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@ -9,6 +9,9 @@
<Source name="REFB.v" type="Verilog" type_short="Verilog"> <Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/> <Options/>
</Source> </Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF"> <Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/> <Options/>
</Source> </Source>

2
CPLD/LCMXO2-640HC/LCMXO2_640HC.lpf
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@ -1,2 +0,0 @@
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;

136
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcl.html
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@ -17,6 +17,142 @@ prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf
<A name="pn230816210353"></A><B><U><big>pn230816210353</big></U></B>
#Start recording tcl command: 8/16/2023 20:34:55
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
prj_run Map -impl impl1
prj_run Export -impl impl1
prj_run PAR -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
prj_run Export -impl impl1
#Stop recording: 8/16/2023 21:03:53
<A name="pn230819062748"></A><B><U><big>pn230819062748</big></U></B>
#Start recording tcl command: 8/18/2023 08:16:23
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
#Stop recording: 8/19/2023 06:27:48
<A name="pn230819062826"></A><B><U><big>pn230819062826</big></U></B>
#Start recording tcl command: 8/19/2023 06:27:54
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
#Stop recording: 8/19/2023 06:28:26
<A name="pn230819062853"></A><B><U><big>pn230819062853</big></U></B>
#Start recording tcl command: 8/19/2023 06:28:30
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1
prj_project close
#Stop recording: 8/19/2023 06:28:53
<A name="pn230819062900"></A><B><U><big>pn230819062900</big></U></B>
#Start recording tcl command: 8/19/2023 06:28:53
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_project close
#Stop recording: 8/19/2023 06:29:00
<A name="pn230819063021"></A><B><U><big>pn230819063021</big></U></B>
#Start recording tcl command: 8/19/2023 06:29:00
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/19/2023 06:30:21
<A name="pn230819205234"></A><B><U><big>pn230819205234</big></U></B>
#Start recording tcl command: 8/19/2023 06:30:42
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
pgr_program run
pgr_program run
pgr_program set -cable USB2
pgr_program set -port FTUSB-0
pgr_program run
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_run Export -impl impl1
prj_run Export -impl impl1
pgr_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_project save
prj_project close
#Stop recording: 8/19/2023 20:52:34
<A name="pn230820055534"></A><B><U><big>pn230820055534</big></U></B>
#Start recording tcl command: 8/19/2023 21:54:38
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1 -forceAll
prj_project close
#Stop recording: 8/20/2023 05:55:34
<BR> <BR>
<BR> <BR>
<BR> <BR>

7
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062748.tcr Normal file
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@ -0,0 +1,7 @@
#Start recording tcl command: 8/18/2023 08:16:23
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Synthesis -impl impl1
#Stop recording: 8/19/2023 06:27:48

5
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062826.tcr Normal file
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@ -0,0 +1,5 @@
#Start recording tcl command: 8/19/2023 06:27:54
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
#Stop recording: 8/19/2023 06:28:26

6
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062853.tcr Normal file
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@ -0,0 +1,6 @@
#Start recording tcl command: 8/19/2023 06:28:30
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Synthesis -impl impl1
prj_project close
#Stop recording: 8/19/2023 06:28:53

5
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819062900.tcr Normal file
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@ -0,0 +1,5 @@
#Start recording tcl command: 8/19/2023 06:28:53
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_project close
#Stop recording: 8/19/2023 06:29:00

4
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819063021.tcr Normal file
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@ -0,0 +1,4 @@
#Start recording tcl command: 8/19/2023 06:29:00
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/19/2023 06:30:21

47
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230819205234.tcr Normal file
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@ -0,0 +1,47 @@
#Start recording tcl command: 8/19/2023 06:30:42
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
pgr_program run
pgr_program run
pgr_program set -cable USB2
pgr_program set -port FTUSB-0
pgr_program run
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
prj_run Export -impl impl1
prj_run Export -impl impl1
pgr_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_run Export -impl impl1 -forceOne
prj_project save
prj_project close
#Stop recording: 8/19/2023 20:52:34

6
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055534.tcr Normal file
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@ -0,0 +1,6 @@
#Start recording tcl command: 8/19/2023 21:54:38
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
prj_run Export -impl impl1 -forceAll
prj_project close
#Stop recording: 8/20/2023 05:55:34

4
CPLD/LCMXO2-640HC/LCMXO2_640HC_tcr.dir/pn230820055626.tcr Normal file
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@ -0,0 +1,4 @@
#Start recording tcl command: 8/20/2023 05:55:58
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
#Stop recording: 8/20/2023 05:56:26

10
CPLD/LCMXO2-640HC/REFB.edn
View File

@ -4,9 +4,9 @@
(keywordMap (keywordLevel 0)) (keywordMap (keywordLevel 0))
(status (status
(written (written
(timestamp 2023 8 16 20 52 2) (timestamp 2023 8 19 7 25 4)
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ") (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 ")
(library ORCLIB (library ORCLIB
(edifLevel 0) (edifLevel 0)
(technology (technology
@ -287,9 +287,9 @@
(property UFM_INIT_FILE_FORMAT (property UFM_INIT_FILE_FORMAT
(string "HEX")) (string "HEX"))
(property UFM_INIT_FILE_NAME (property UFM_INIT_FILE_NAME
(string "NONE")) (string "../RAM2GS-LCMXO2.mem"))
(property UFM_INIT_ALL_ZEROS (property UFM_INIT_ALL_ZEROS
(string "ENABLED")) (string "DISABLED"))
(property UFM_INIT_START_PAGE (property UFM_INIT_START_PAGE
(string "190")) (string "190"))
(property UFM_INIT_PAGES (property UFM_INIT_PAGES
@ -383,7 +383,7 @@
(property EFB_I2C1 (property EFB_I2C1
(string "DISABLED")) (string "DISABLED"))
(property EFB_WB_CLK_FREQ (property EFB_WB_CLK_FREQ
(string "62.5"))) (string "66.7")))
(net scuba_vhi (net scuba_vhi
(joined (joined
(portRef Z (instanceRef scuba_vhi_inst)) (portRef Z (instanceRef scuba_vhi_inst))

8
CPLD/LCMXO2-640HC/REFB.ipx
View File

@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 16 20:52:14.413" version="1.2" type="Module" synthesis="synplify" source_format="Verilog"> <DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 19 07:25:06.194" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<Package> <Package>
<File name="REFB.lpc" type="lpc" modified="2023 08 16 20:52:02.825"/> <File name="REFB.lpc" type="lpc" modified="2023 08 19 07:25:04.117"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 08 16 20:52:02.871"/> <File name="REFB.v" type="top_level_verilog" modified="2023 08 19 07:25:04.191"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 16 20:52:02.871"/> <File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 19 07:25:04.191"/>
</Package> </Package>
</DiamondModule> </DiamondModule>

282
CPLD/LCMXO2-640HC/REFB.lpc
View File

@ -1,141 +1,141 @@
[Device] [Device]
Family=machxo2 Family=machxo2
PartType=LCMXO2-640HC PartType=LCMXO2-640HC
PartName=LCMXO2-640HC-4TG100C PartName=LCMXO2-640HC-4TG100C
SpeedGrade=4 SpeedGrade=4
Package=TQFP100 Package=TQFP100
OperatingCondition=COM OperatingCondition=COM
Status=S Status=S
[IP] [IP]
VendorName=Lattice Semiconductor Corporation VendorName=Lattice Semiconductor Corporation
CoreType=LPM CoreType=LPM
CoreStatus=Demo CoreStatus=Demo
CoreName=EFB CoreName=EFB
CoreRevision=1.2 CoreRevision=1.2
ModuleName=REFB ModuleName=REFB
SourceFormat=Verilog HDL SourceFormat=Verilog HDL
ParameterFileVersion=1.0 ParameterFileVersion=1.0
Date=08/16/2023 Date=08/19/2023
Time=20:52:02 Time=07:25:04
[Parameters] [Parameters]
Verilog=1 Verilog=1
VHDL=0 VHDL=0
EDIF=1 EDIF=1
Destination=Synplicity Destination=Synplicity
Expression=BusA(0 to 7) Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB] Order=Big Endian [MSB:LSB]
IO=0 IO=0
freq= freq=
i2c1=0 i2c1=0
i2c1config=0 i2c1config=0
i2c1_addr=7-Bit Addressing i2c1_addr=7-Bit Addressing
i2c1_ce=0 i2c1_ce=0
i2c1_freq=100 i2c1_freq=100
i2c1_sa=10000 i2c1_sa=10000
i2c1_we=0 i2c1_we=0
i2c2=0 i2c2=0
i2c2_addr=7-Bit Addressing i2c2_addr=7-Bit Addressing
i2c2_ce=0 i2c2_ce=0
i2c2_freq=100 i2c2_freq=100
i2c2_sa=10000 i2c2_sa=10000
i2c2_we=0 i2c2_we=0
ufm_addr=7-Bit Addressing ufm_addr=7-Bit Addressing
ufm_sa=10000 ufm_sa=10000
pll=0 pll=0
pll_cnt=1 pll_cnt=1
spi=0 spi=0
spi_clkinv=0 spi_clkinv=0
spi_cs=1 spi_cs=1
spi_en=0 spi_en=0
spi_freq=1 spi_freq=1
spi_lsb=0 spi_lsb=0
spi_mode=Slave spi_mode=Slave
spi_ib=0 spi_ib=0
spi_ph=0 spi_ph=0
spi_hs=0 spi_hs=0
spi_rxo=0 spi_rxo=0
spi_rxr=0 spi_rxr=0
spi_txo=0 spi_txo=0
spi_txr=0 spi_txr=0
spi_we=0 spi_we=0
static_tc=Static static_tc=Static
tc=0 tc=0
tc_clkinv=Positive tc_clkinv=Positive
tc_ctr=1 tc_ctr=1
tc_div=1 tc_div=1
tc_ipcap=0 tc_ipcap=0
tc_mode=CTCM tc_mode=CTCM
tc_ocr=32767 tc_ocr=32767
tc_oflow=1 tc_oflow=1
tc_o=TOGGLE tc_o=TOGGLE
tc_opcomp=0 tc_opcomp=0
tc_osc=0 tc_osc=0
tc_sa_oflow=0 tc_sa_oflow=0
tc_top=65535 tc_top=65535
ufm=1 ufm=1
ufm0=0 ufm0=0
ufm1=0 ufm1=0
ufm2=0 ufm2=0
ufm3=0 ufm3=0
ufm_cfg0=0 ufm_cfg0=0
ufm_cfg1=0 ufm_cfg1=0
wb_clk_freq=62.5 wb_clk_freq=66.7
ufm_usage=SHARED_EBR_TAG ufm_usage=SHARED_EBR_TAG
ufm_ebr=190 ufm_ebr=190
ufm_remain= ufm_remain=
mem_size=1 mem_size=1
ufm_start= ufm_start=
ufm_init=0 ufm_init=mem
memfile= memfile=../RAM2GS-LCMXO2.mem
ufm_dt=hex ufm_dt=hex
ufm0_ebr= ufm0_ebr=
mem_size0=1 mem_size0=1
ufm0_init=0 ufm0_init=0
memfile0= memfile0=
ufm0_dt=hex ufm0_dt=hex
ufm1_ebr= ufm1_ebr=
mem_size1=1 mem_size1=1
ufm1_init=0 ufm1_init=0
memfile1= memfile1=
ufm1_dt=hex ufm1_dt=hex
ufm2_ebr= ufm2_ebr=
mem_size2=1 mem_size2=1
ufm2_init=0 ufm2_init=0
memfile2= memfile2=
ufm2_dt=hex ufm2_dt=hex
ufm3_ebr= ufm3_ebr=
mem_size3=1 mem_size3=1
ufm3_init=0 ufm3_init=0
memfile3= memfile3=
ufm3_dt=hex ufm3_dt=hex
ufm_cfg0_ebr= ufm_cfg0_ebr=
mem_size_cfg0=1 mem_size_cfg0=1
ufm_cfg0_init=0 ufm_cfg0_init=0
memfile_cfg0= memfile_cfg0=
ufm_cfg0_dt=hex ufm_cfg0_dt=hex
ufm_cfg1_ebr= ufm_cfg1_ebr=
mem_size_cfg1=1 mem_size_cfg1=1
ufm_cfg1_init=0 ufm_cfg1_init=0
memfile_cfg1= memfile_cfg1=
ufm_cfg1_dt=hex ufm_cfg1_dt=hex
wb=1 wb=1
boot_option=Internal boot_option=Internal
efb_ufm=0 efb_ufm=0
boot_option_internal=Single Boot boot_option_internal=Single Boot
internal_ufm0=0 internal_ufm0=0
internal_ufm1=0 internal_ufm1=0
efb_ufm_boot= efb_ufm_boot=
tamperdr=0 tamperdr=0
t_pwd=0 t_pwd=0
t_lockflash=0 t_lockflash=0
t_manmode=0 t_manmode=0
t_jtagport=0 t_jtagport=0
t_sspiport=0 t_sspiport=0
t_sic2port=0 t_sic2port=0
t_wbport=0 t_wbport=0
t_portlock=0 t_portlock=0
[Command] [Command]
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640

62
CPLD/LCMXO2-640HC/REFB.naf
View File

@ -1,31 +1,31 @@
wb_clk_i i wb_clk_i i
wb_rst_i i wb_rst_i i
wb_cyc_i i wb_cyc_i i
wb_stb_i i wb_stb_i i
wb_we_i i wb_we_i i
wb_adr_i[7] i wb_adr_i[7] i
wb_adr_i[6] i wb_adr_i[6] i
wb_adr_i[5] i wb_adr_i[5] i
wb_adr_i[4] i wb_adr_i[4] i
wb_adr_i[3] i wb_adr_i[3] i
wb_adr_i[2] i wb_adr_i[2] i
wb_adr_i[1] i wb_adr_i[1] i
wb_adr_i[0] i wb_adr_i[0] i
wb_dat_i[7] i wb_dat_i[7] i
wb_dat_i[6] i wb_dat_i[6] i
wb_dat_i[5] i wb_dat_i[5] i
wb_dat_i[4] i wb_dat_i[4] i
wb_dat_i[3] i wb_dat_i[3] i
wb_dat_i[2] i wb_dat_i[2] i
wb_dat_i[1] i wb_dat_i[1] i
wb_dat_i[0] i wb_dat_i[0] i
wb_dat_o[7] o wb_dat_o[7] o
wb_dat_o[6] o wb_dat_o[6] o
wb_dat_o[5] o wb_dat_o[5] o
wb_dat_o[4] o wb_dat_o[4] o
wb_dat_o[3] o wb_dat_o[3] o
wb_dat_o[2] o wb_dat_o[2] o
wb_dat_o[1] o wb_dat_o[1] o
wb_dat_o[0] o wb_dat_o[0] o
wb_ack_o o wb_ack_o o
wbc_ufm_irq o wbc_ufm_irq o

2
CPLD/LCMXO2-640HC/REFB.sort
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@ -1 +1 @@
REFB.v REFB.v

4
CPLD/LCMXO2-640HC/REFB.srp
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@ -1,5 +1,5 @@
SCUBA, Version Diamond (64-bit) 3.12.1.454 SCUBA, Version Diamond (64-bit) 3.12.1.454
Wed Aug 16 20:52:02 2023 Sat Aug 19 07:25:04 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -7,7 +7,7 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
Circuit name : REFB Circuit name : REFB
Module type : efb Module type : efb
Module Version : 1.2 Module Version : 1.2

10
CPLD/LCMXO2-640HC/REFB.v
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@ -1,7 +1,7 @@
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ /* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */ /* Module Version: 1.2 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */ /* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 */
/* Wed Aug 16 20:52:02 2023 */ /* Sat Aug 19 07:25:04 2023 */
`timescale 1 ns / 1 ps `timescale 1 ns / 1 ps
@ -26,8 +26,8 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
VLO scuba_vlo_inst (.Z(scuba_vlo)); VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ; defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ;
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ; defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ; defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
defparam EFBInst_0.UFM_INIT_PAGES = 1 ; defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
defparam EFBInst_0.DEV_DENSITY = "640L" ; defparam EFBInst_0.DEV_DENSITY = "640L" ;
@ -74,7 +74,7 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ; defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ;
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),

88
CPLD/LCMXO2-640HC/REFB_generate.log
View File

@ -1,44 +1,44 @@
Starting process: Module Starting process: Module
Starting process: Starting process:
SCUBA, Version Diamond (64-bit) 3.12.1.454 SCUBA, Version Diamond (64-bit) 3.12.1.454
Wed Aug 16 20:52:02 2023 Sat Aug 19 07:25:04 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
BEGIN SCUBA Module Synthesis BEGIN SCUBA Module Synthesis
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
Circuit name : REFB Circuit name : REFB
Module type : efb Module type : efb
Module Version : 1.2 Module Version : 1.2
Ports : Ports :
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
I/O buffer : not inserted I/O buffer : not inserted
EDIF output : REFB.edn EDIF output : REFB.edn
Verilog output : REFB.v Verilog output : REFB.v
Verilog template : REFB_tmpl.v Verilog template : REFB_tmpl.v
Verilog purpose : for synthesis and simulation Verilog purpose : for synthesis and simulation
Bus notation : big endian Bus notation : big endian
Report output : REFB.srp Report output : REFB.srp
Estimated Resource Usage: Estimated Resource Usage:
END SCUBA Module Synthesis END SCUBA Module Synthesis
File: REFB.lpc created. File: REFB.lpc created.
End process: completed successfully. End process: completed successfully.
Total Warnings: 0 Total Warnings: 0
Total Errors: 0 Total Errors: 0

2
CPLD/LCMXO2-640HC/REFB_tmpl.v
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@ -1,6 +1,6 @@
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ /* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */ /* Module Version: 1.2 */
/* Wed Aug 16 20:52:02 2023 */ /* Sat Aug 19 07:25:04 2023 */
/* parameterized module instance */ /* parameterized module instance */
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),

5148
CPLD/LCMXO2-640HC/_math_real.vhd
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File diff suppressed because it is too large Load Diff

200
CPLD/LCMXO2-640HC/generate_core.tcl
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@ -1,100 +1,100 @@
#!/usr/local/bin/wish #!/usr/local/bin/wish
proc GetPlatform {} { proc GetPlatform {} {
global tcl_platform global tcl_platform
set cpu $tcl_platform(machine) set cpu $tcl_platform(machine)
switch $cpu { switch $cpu {
intel - intel -
i*86* { i*86* {
set cpu ix86 set cpu ix86
} }
x86_64 { x86_64 {
if {$tcl_platform(wordSize) == 4} { if {$tcl_platform(wordSize) == 4} {
set cpu ix86 set cpu ix86
} }
} }
} }
switch $tcl_platform(platform) { switch $tcl_platform(platform) {
windows { windows {
if {$cpu == "amd64"} { if {$cpu == "amd64"} {
# Do not check wordSize, win32-x64 is an IL32P64 platform. # Do not check wordSize, win32-x64 is an IL32P64 platform.
set cpu x86_64 set cpu x86_64
} }
if {$cpu == "x86_64"} { if {$cpu == "x86_64"} {
return "nt64" return "nt64"
} else { } else {
return "nt" return "nt"
} }
} }
unix { unix {
if {$tcl_platform(os) == "Linux"} { if {$tcl_platform(os) == "Linux"} {
if {$cpu == "x86_64"} { if {$cpu == "x86_64"} {
return "lin64" return "lin64"
} else { } else {
return "lin" return "lin"
} }
} else { } else {
return "sol" return "sol"
} }
} }
} }
return "nt" return "nt"
} }
proc GetCmdLine {lpcfile} { proc GetCmdLine {lpcfile} {
global Para global Para
if [catch {open $lpcfile r} fileid] { if [catch {open $lpcfile r} fileid] {
puts "Cannot open $para_file file!" puts "Cannot open $para_file file!"
exit -1 exit -1
} }
seek $fileid 0 start seek $fileid 0 start
set default_match 0 set default_match 0
while {[gets $fileid line] >= 0} { while {[gets $fileid line] >= 0} {
if {[string first "\[Command\]" $line] == 0} { if {[string first "\[Command\]" $line] == 0} {
set default_match 1 set default_match 1
continue continue
} }
if {[string first "\[" $line] == 0} { if {[string first "\[" $line] == 0} {
set default_match 0 set default_match 0
} }
if {$default_match == 1} { if {$default_match == 1} {
if [regexp {([^=]*)=(.*)} $line match parameter value] { if [regexp {([^=]*)=(.*)} $line match parameter value] {
if [regexp {([ |\t]*;)} $parameter match] {continue} if [regexp {([ |\t]*;)} $parameter match] {continue}
if [regexp {(.*)[ |\t]*;} $value match temp] { if [regexp {(.*)[ |\t]*;} $value match temp] {
set Para($parameter) $temp set Para($parameter) $temp
} else { } else {
set Para($parameter) $value set Para($parameter) $value
} }
} }
} }
} }
set default_match 0 set default_match 0
close $fileid close $fileid
return $Para(cmd_line) return $Para(cmd_line)
} }
set platformpath [GetPlatform] set platformpath [GetPlatform]
set Para(sbp_path) [file dirname [info script]] set Para(sbp_path) [file dirname [info script]]
set Para(install_dir) $env(TOOLRTF) set Para(install_dir) $env(TOOLRTF)
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
set scuba "$Para(FPGAPath)/scuba" set scuba "$Para(FPGAPath)/scuba"
set modulename "REFB" set modulename "REFB"
set lang "verilog" set lang "verilog"
set lpcfile "$Para(sbp_path)/$modulename.lpc" set lpcfile "$Para(sbp_path)/$modulename.lpc"
set arch "xo2c00" set arch "xo2c00"
set cmd_line [GetCmdLine $lpcfile] set cmd_line [GetCmdLine $lpcfile]
set fdcfile "$Para(sbp_path)/$modulename.fdc" set fdcfile "$Para(sbp_path)/$modulename.fdc"
if {[file exists $fdcfile] == 0} { if {[file exists $fdcfile] == 0} {
append scuba " " $cmd_line append scuba " " $cmd_line
} else { } else {
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
} }
set Para(result) [catch {eval exec "$scuba"} msg] set Para(result) [catch {eval exec "$scuba"} msg]
#puts $msg #puts $msg

148
CPLD/LCMXO2-640HC/generate_ngd.tcl
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@ -1,74 +1,74 @@
#!/usr/local/bin/wish #!/usr/local/bin/wish
proc GetPlatform {} { proc GetPlatform {} {
global tcl_platform global tcl_platform
set cpu $tcl_platform(machine) set cpu $tcl_platform(machine)
switch $cpu { switch $cpu {
intel - intel -
i*86* { i*86* {
set cpu ix86 set cpu ix86
} }
x86_64 { x86_64 {
if {$tcl_platform(wordSize) == 4} { if {$tcl_platform(wordSize) == 4} {
set cpu ix86 set cpu ix86
} }
} }
} }
switch $tcl_platform(platform) { switch $tcl_platform(platform) {
windows { windows {
if {$cpu == "amd64"} { if {$cpu == "amd64"} {
# Do not check wordSize, win32-x64 is an IL32P64 platform. # Do not check wordSize, win32-x64 is an IL32P64 platform.
set cpu x86_64 set cpu x86_64
} }
if {$cpu == "x86_64"} { if {$cpu == "x86_64"} {
return "nt64" return "nt64"
} else { } else {
return "nt" return "nt"
} }
} }
unix { unix {
if {$tcl_platform(os) == "Linux"} { if {$tcl_platform(os) == "Linux"} {
if {$cpu == "x86_64"} { if {$cpu == "x86_64"} {
return "lin64" return "lin64"
} else { } else {
return "lin" return "lin"
} }
} else { } else {
return "sol" return "sol"
} }
} }
} }
return "nt" return "nt"
} }
set platformpath [GetPlatform] set platformpath [GetPlatform]
set Para(sbp_path) [file dirname [info script]] set Para(sbp_path) [file dirname [info script]]
set Para(install_dir) $env(TOOLRTF) set Para(install_dir) $env(TOOLRTF)
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
set Para(ModuleName) "REFB" set Para(ModuleName) "REFB"
set Para(Module) "EFB" set Para(Module) "EFB"
set Para(libname) machxo2 set Para(libname) machxo2
set Para(arch_name) xo2c00 set Para(arch_name) xo2c00
set Para(PartType) "LCMXO2-640HC" set Para(PartType) "LCMXO2-640HC"
set Para(tech_syn) machxo2 set Para(tech_syn) machxo2
set Para(tech_cae) machxo2 set Para(tech_cae) machxo2
set Para(Package) "TQFP100" set Para(Package) "TQFP100"
set Para(SpeedGrade) "4" set Para(SpeedGrade) "4"
set Para(FMax) "100" set Para(FMax) "100"
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
#edif2ngd #edif2ngd
set edif2ngd "$Para(FPGAPath)/edif2ngd" set edif2ngd "$Para(FPGAPath)/edif2ngd"
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
#puts $msg #puts $msg
#ngdbuild #ngdbuild
set ngdbuild "$Para(FPGAPath)/ngdbuild" set ngdbuild "$Para(FPGAPath)/ngdbuild"
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
#puts $msg #puts $msg

65
CPLD/LCMXO2-640HC/impl1/.build_status
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@ -2,41 +2,54 @@
<BuildStatus> <BuildStatus>
<Strategy name="Strategy1"> <Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0"> <Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/> <Task name="IBIS" build_result="2" update_result="0" update_time="1692496517"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/> <Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1692496519"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/> <Task name="TimingSimFileVHD" build_result="2" update_result="0" update_time="1692496520"/>
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/> <Task name="Bitgen" build_result="2" update_result="0" update_time="1692496523"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692233986"/> <Task name="Jedecgen" build_result="2" update_result="0" update_time="1692496527"/>
</Milestone> </Milestone>
<Milestone name="Map" build_result="2" build_time="1692233977"> <Milestone name="Map" build_result="2" build_time="1692496497">
<Task name="Map" build_result="2" update_result="0" update_time="1692233977"/> <Task name="Map" build_result="2" update_result="0" update_time="1692496497"/>
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/> <Task name="MapTrace" build_result="2" update_result="0" update_time="1692496498"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/> <Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692496499"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/> <Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692496501"/>
</Milestone> </Milestone>
<Milestone name="PAR" build_result="2" build_time="1692233984"> <Milestone name="PAR" build_result="2" build_time="1692496511">
<Task name="PAR" build_result="2" update_result="0" update_time="1692233984"/> <Task name="PAR" build_result="2" update_result="0" update_time="1692496511"/>
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/> <Task name="PARTrace" build_result="2" update_result="0" update_time="1692496511"/>
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/> <Task name="IOTiming" build_result="2" update_result="0" update_time="1692496513"/>
</Milestone> </Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1692233976"> <Milestone name="Synthesis" build_result="2" build_time="1692496496">
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692233976"/> <Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692496496"/>
</Milestone> </Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0"> <Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="2" update_time="1692233963"/> <Task name="HDLE" build_result="2" update_result="0" update_time="1692444754"/>
<Task name="BKM" build_result="0" update_result="2" update_time="1692233963"/> <Task name="BKM" build_result="0" update_result="2" update_time="1692444754"/>
<Task name="SSO" build_result="0" update_result="3" update_time="0"/> <Task name="SSO" build_result="0" update_result="3" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/> <Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
<Task name="DEC" build_result="0" update_result="3" update_time="0"/> <Task name="DEC" build_result="0" update_result="3" update_time="0"/>
</Milestone> </Milestone>
<Milestone name="Translate" build_result="2" build_time="1692233976"> <Milestone name="Translate" build_result="2" build_time="1692496497">
<Task name="Translate" build_result="2" update_result="0" update_time="1692233976"/> <Task name="Translate" build_result="2" update_result="0" update_time="1692496497"/>
</Milestone> </Milestone>
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692233986" last_build_size="4399"/> <Report name="IBIS/LCMXO2_640HC_impl1.ibs" last_build_time="1692496517" last_build_size="184928"/>
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692233975" last_build_size="204145"/> <Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692496527" last_build_size="4359"/>
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692233986" last_build_size="177085"/> <Report name="LCMXO2_640HC_impl1.bit" last_build_time="1692496523" last_build_size="6185"/>
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692233984" last_build_size="278109"/> <Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692496494" last_build_size="198884"/>
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692233976" last_build_size="207794"/> <Report name="LCMXO2_640HC_impl1.ior" last_build_time="1692496513" last_build_size="6573"/>
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692233977" last_build_size="197654"/> <Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692496527" last_build_size="177085"/>
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692496511" last_build_size="268674"/>
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692496497" last_build_size="204730"/>
<Report name="LCMXO2_640HC_impl1.tw1" last_build_time="1692496498" last_build_size="17550"/>
<Report name="LCMXO2_640HC_impl1.twr" last_build_time="1692496511" last_build_size="90277"/>
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692496497" last_build_size="193033"/>
<Report name="LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692496501" last_build_size="164487"/>
<Report name="LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692496501" last_build_size="1365291"/>
<Report name="LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692496499" last_build_size="163556"/>
<Report name="LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692496499" last_build_size="201461"/>
<Report name="LCMXO2_640HC_impl1_vho.sdf" last_build_time="1692496520" last_build_size="181438"/>
<Report name="LCMXO2_640HC_impl1_vho.vho" last_build_time="1692496520" last_build_size="1408234"/>
<Report name="LCMXO2_640HC_impl1_vo.sdf" last_build_time="1692496519" last_build_size="180465"/>
<Report name="LCMXO2_640HC_impl1_vo.vo" last_build_time="1692496519" last_build_size="212142"/>
</Strategy> </Strategy>
</BuildStatus> </BuildStatus>

3151
CPLD/LCMXO2-640HC/impl1/IBIS/LCMXO2_640HC_impl1.ibs Normal file
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142
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.alt
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@ -1,71 +1,71 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved * NOTE All Rights Reserved *
NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 * NOTE DATE CREATED: Sat Aug 19 21:55:27 2023 *
NOTE DESIGN NAME: RAM2GS * NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS * NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout * NOTE PINS RD[0] : 36 : inout *
NOTE PINS Dout[0] : 76 : out * NOTE PINS Dout[0] : 76 : out *
NOTE PINS PHI2 : 8 : in * NOTE PINS PHI2 : 8 : in *
NOTE PINS RDQML : 48 : out * NOTE PINS RDQML : 48 : out *
NOTE PINS RDQMH : 51 : out * NOTE PINS RDQMH : 51 : out *
NOTE PINS nRCAS : 52 : out * NOTE PINS nRCAS : 52 : out *
NOTE PINS nRRAS : 54 : out * NOTE PINS nRRAS : 54 : out *
NOTE PINS nRWE : 49 : out * NOTE PINS nRWE : 49 : out *
NOTE PINS RCKE : 53 : out * NOTE PINS RCKE : 53 : out *
NOTE PINS RCLK : 62 : in * NOTE PINS RCLK : 62 : in *
NOTE PINS nRCS : 57 : out * NOTE PINS nRCS : 57 : out *
NOTE PINS RD[7] : 43 : inout * NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout * NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout * NOTE PINS RD[5] : 41 : inout *
NOTE PINS RD[4] : 40 : inout * NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout * NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout * NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout * NOTE PINS RD[1] : 37 : inout *
NOTE PINS RA[11] : 59 : out * NOTE PINS RA[11] : 59 : out *
NOTE PINS RA[10] : 64 : out * NOTE PINS RA[10] : 64 : out *
NOTE PINS RA[9] : 63 : out * NOTE PINS RA[9] : 63 : out *
NOTE PINS RA[8] : 65 : out * NOTE PINS RA[8] : 65 : out *
NOTE PINS RA[7] : 75 : out * NOTE PINS RA[7] : 75 : out *
NOTE PINS RA[6] : 68 : out * NOTE PINS RA[6] : 68 : out *
NOTE PINS RA[5] : 70 : out * NOTE PINS RA[5] : 70 : out *
NOTE PINS RA[4] : 74 : out * NOTE PINS RA[4] : 74 : out *
NOTE PINS RA[3] : 71 : out * NOTE PINS RA[3] : 71 : out *
NOTE PINS RA[2] : 69 : out * NOTE PINS RA[2] : 69 : out *
NOTE PINS RA[1] : 67 : out * NOTE PINS RA[1] : 67 : out *
NOTE PINS RA[0] : 66 : out * NOTE PINS RA[0] : 66 : out *
NOTE PINS RBA[1] : 60 : out * NOTE PINS RBA[1] : 60 : out *
NOTE PINS RBA[0] : 58 : out * NOTE PINS RBA[0] : 58 : out *
NOTE PINS LED : 34 : out * NOTE PINS LED : 34 : out *
NOTE PINS nFWE : 15 : in * NOTE PINS nFWE : 15 : in *
NOTE PINS nCRAS : 17 : in * NOTE PINS nCRAS : 17 : in *
NOTE PINS nCCAS : 9 : in * NOTE PINS nCCAS : 9 : in *
NOTE PINS Dout[7] : 82 : out * NOTE PINS Dout[7] : 82 : out *
NOTE PINS Dout[6] : 78 : out * NOTE PINS Dout[6] : 78 : out *
NOTE PINS Dout[5] : 84 : out * NOTE PINS Dout[5] : 84 : out *
NOTE PINS Dout[4] : 83 : out * NOTE PINS Dout[4] : 83 : out *
NOTE PINS Dout[3] : 85 : out * NOTE PINS Dout[3] : 85 : out *
NOTE PINS Dout[2] : 87 : out * NOTE PINS Dout[2] : 87 : out *
NOTE PINS Dout[1] : 86 : out * NOTE PINS Dout[1] : 86 : out *
NOTE PINS Din[7] : 1 : in * NOTE PINS Din[7] : 1 : in *
NOTE PINS Din[6] : 2 : in * NOTE PINS Din[6] : 2 : in *
NOTE PINS Din[5] : 98 : in * NOTE PINS Din[5] : 98 : in *
NOTE PINS Din[4] : 99 : in * NOTE PINS Din[4] : 99 : in *
NOTE PINS Din[3] : 97 : in * NOTE PINS Din[3] : 97 : in *
NOTE PINS Din[2] : 88 : in * NOTE PINS Din[2] : 88 : in *
NOTE PINS Din[1] : 96 : in * NOTE PINS Din[1] : 96 : in *
NOTE PINS Din[0] : 3 : in * NOTE PINS Din[0] : 3 : in *
NOTE PINS CROW[1] : 16 : in * NOTE PINS CROW[1] : 16 : in *
NOTE PINS CROW[0] : 10 : in * NOTE PINS CROW[0] : 10 : in *
NOTE PINS MAin[9] : 32 : in * NOTE PINS MAin[9] : 32 : in *
NOTE PINS MAin[8] : 25 : in * NOTE PINS MAin[8] : 25 : in *
NOTE PINS MAin[7] : 18 : in * NOTE PINS MAin[7] : 18 : in *
NOTE PINS MAin[6] : 24 : in * NOTE PINS MAin[6] : 24 : in *
NOTE PINS MAin[5] : 19 : in * NOTE PINS MAin[5] : 19 : in *
NOTE PINS MAin[4] : 20 : in * NOTE PINS MAin[4] : 20 : in *
NOTE PINS MAin[3] : 21 : in * NOTE PINS MAin[3] : 21 : in *
NOTE PINS MAin[2] : 13 : in * NOTE PINS MAin[2] : 13 : in *
NOTE PINS MAin[1] : 12 : in * NOTE PINS MAin[1] : 12 : in *
NOTE PINS MAin[0] : 14 : in * NOTE PINS MAin[0] : 14 : in *
NOTE CONFIGURATION MODE: NONE * NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on * NOTE COMPRESSION: on *

85
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.areasrr
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@ -1,42 +1,43 @@
---------------------------------------------------------------------- ----------------------------------------------------------------------
Report for cell RAM2GS.verilog Report for cell RAM2GS.verilog
Register bits: 109 of 640 (17%) Register bits: 111 of 640 (17%)
PIC Latch: 0 PIC Latch: 0
I/O cells: 63 I/O cells: 63
Cell usage: Cell usage:
cell count Res Usage(%) cell count Res Usage(%)
BB 8 100.0 BB 8 100.0
CCU2D 10 100.0 CCU2D 10 100.0
EFB 1 100.0 EFB 1 100.0
FD1P3AX 27 100.0 FD1P3AX 28 100.0
FD1P3IX 3 100.0 FD1P3IX 2 100.0
FD1S3AX 51 100.0 FD1S3AX 52 100.0
FD1S3IX 3 100.0 FD1S3IX 4 100.0
GSR 1 100.0 GSR 1 100.0
IB 25 100.0 IB 25 100.0
IFS1P3DX 9 100.0 IFS1P3DX 9 100.0
INV 8 100.0 INV 6 100.0
OB 30 100.0 OB 30 100.0
OFS1P3BX 4 100.0 OFS1P3BX 4 100.0
OFS1P3DX 11 100.0 OFS1P3DX 11 100.0
OFS1P3JX 1 100.0 OFS1P3JX 1 100.0
ORCALUT4 206 100.0 ORCALUT4 199 100.0
PFUMX 1 100.0 PFUMX 3 100.0
PUR 1 100.0 PUR 1 100.0
VHI 2 100.0 VHI 2 100.0
VLO 2 100.0 VLO 2 100.0
SUB MODULES SUB MODULES
REFB 1 100.0 REFB 1 100.0
TOTAL 405 TOTAL 400
---------------------------------------------------------------------- ----------------------------------------------------------------------
Report for cell REFB.netlist Report for cell REFB.netlist
Instance path: ufmefb Instance path: ufmefb
Cell usage: Cell usage:
cell count Res Usage(%) cell count Res Usage(%)
EFB 1 100.0 EFB 1 100.0
VHI 1 50.0 ORCALUT4 1 0.5
VLO 1 50.0 VHI 1 50.0
VLO 1 50.0
TOTAL 3
TOTAL 4

162
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.bgn
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@ -1,86 +1,86 @@
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:44 2023 Sat Aug 19 21:55:24 2023
Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. Design name: RAM2GS
Design name: RAM2GS NCD version: 3.3
NCD version: 3.3 Vendor: LATTICE
Vendor: LATTICE Device: LCMXO2-640HC
Device: LCMXO2-640HC Package: TQFP100
Package: TQFP100 Performance: 4
Performance: 4 Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.39.
Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
Running DRC. DRC detected 0 errors and 0 warnings.
DRC detected 0 errors and 0 warnings. Reading Preference File from LCMXO2_640HC_impl1.prf.
Reading Preference File from LCMXO2_640HC_impl1.prf.
Preference Summary:
Preference Summary: +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | Preference | Current Setting |
| Preference | Current Setting | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | RamCfg | Reset** |
| RamCfg | Reset** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | MCCLK_FREQ | 2.08** |
| MCCLK_FREQ | 2.08** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** |
| CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | INBUF | ON** |
| INBUF | ON** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** |
| JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | SDM_PORT | DISABLE** |
| SDM_PORT | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** |
| SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** |
| MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | I2C_PORT | DISABLE** |
| I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | MUX_CONFIGURATION_PORTS | DISABLE** |
| MUX_CONFIGURATION_PORTS | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | CONFIGURATION | CFG** |
| CONFIGURATION | CFG** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON** |
| COMPRESS_CONFIG | ON** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | MY_ASSP | OFF** |
| MY_ASSP | OFF** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | ONE_TIME_PROGRAM | OFF** |
| ONE_TIME_PROGRAM | OFF** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | ENABLE_TRANSFR | DISABLE** |
| ENABLE_TRANSFR | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | SHAREDEBRINIT | DISABLE** |
| SHAREDEBRINIT | DISABLE** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** |
| BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+
+---------------------------------+---------------------------------+ * Default setting.
* Default setting. ** The specified setting matches the default setting.
** The specified setting matches the default setting.
Creating bit map...
Creating bit map...
Bitstream Status: Final Version 1.95.
Bitstream Status: Final Version 1.95.
Saving bit stream in "LCMXO2_640HC_impl1.jed".
Saving bit stream in "LCMXO2_640HC_impl1.jed".
===========
=========== UFM Summary.
UFM Summary. ===========
=========== UFM Size: 191 Pages (128*191 Bits).
UFM Size: 191 Pages (128*191 Bits). UFM Utilization: General Purpose Flash Memory.
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). Initialized UFM Pages: 1 Page (Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total CPU Time: 1 secs Total REAL Time: 3 secs
Total REAL Time: 2 secs Peak Memory Usage: 266 MB
Peak Memory Usage: 245 MB

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.pad
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PAD Specification File PAD Specification File
*************************** ***************************
PART TYPE: LCMXO2-640HC PART TYPE: LCMXO2-640HC
Performance Grade: 4 Performance Grade: 4
PACKAGE: TQFP100 PACKAGE: TQFP100
Package Status: Final Version 1.39 Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023 Sat Aug 19 21:55:06 2023
Pinout by Port Name: Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | | Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | | LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | | PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank: Vccio by Bank:
+------+-------+ +------+-------+
| Bank | Vccio | | Bank | Vccio |
+------+-------+ +------+-------+
| 0 | 3.3V | | 0 | 3.3V |
| 1 | 3.3V | | 1 | 3.3V |
| 2 | 3.3V | | 2 | 3.3V |
| 3 | 3.3V | | 3 | 3.3V |
+------+-------+ +------+-------+
Vref by Bank: Vref by Bank:
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) | | Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
Pinout by Pin Number: Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | | Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | | 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | | 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | | 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | | 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
| 7/3 | unused, PULL:DOWN | | | PL3A | | | | | 7/3 | unused, PULL:DOWN | | | PL3A | | | |
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | | 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | | 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | | 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | | 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | | 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | | 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | | 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | | 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | | 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | | 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | | 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | | 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | | 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | | 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | | 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | | 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
| 28/2 | unused, PULL:DOWN | | | PB4B | | | | | 28/2 | unused, PULL:DOWN | | | PB4B | | | |
| 29/2 | unused, PULL:DOWN | | | PB4C | | | | | 29/2 | unused, PULL:DOWN | | | PB4C | | | |
| 30/2 | unused, PULL:DOWN | | | PB4D | | | | | 30/2 | unused, PULL:DOWN | | | PB4D | | | |
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | | 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | | 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | | 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | | 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | | 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | | 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | | 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | | 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | | 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | | 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | | | 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | unused, PULL:DOWN | | | PB14B | | | | | 47/2 | unused, PULL:DOWN | | | PB14B | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | | 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | | 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | | 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | | 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | | 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | | 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | | 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | | 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | | 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | | 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | | 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | | 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | | 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | | 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | | 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | | 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | | 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | | 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | | 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | | 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | | 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | | 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | | 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | | 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | | 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | | 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | | 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | | 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | | 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | | 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | | 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | | 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | | 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | | 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | | PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins: sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | | Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | | PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | | PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | | PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | | PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins: Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "CROW[0]" SITE "10"; LOCATE COMP "CROW[0]" SITE "10";
LOCATE COMP "CROW[1]" SITE "16"; LOCATE COMP "CROW[1]" SITE "16";
LOCATE COMP "Din[0]" SITE "3"; LOCATE COMP "Din[0]" SITE "3";
LOCATE COMP "Din[1]" SITE "96"; LOCATE COMP "Din[1]" SITE "96";
LOCATE COMP "Din[2]" SITE "88"; LOCATE COMP "Din[2]" SITE "88";
LOCATE COMP "Din[3]" SITE "97"; LOCATE COMP "Din[3]" SITE "97";
LOCATE COMP "Din[4]" SITE "99"; LOCATE COMP "Din[4]" SITE "99";
LOCATE COMP "Din[5]" SITE "98"; LOCATE COMP "Din[5]" SITE "98";
LOCATE COMP "Din[6]" SITE "2"; LOCATE COMP "Din[6]" SITE "2";
LOCATE COMP "Din[7]" SITE "1"; LOCATE COMP "Din[7]" SITE "1";
LOCATE COMP "Dout[0]" SITE "76"; LOCATE COMP "Dout[0]" SITE "76";
LOCATE COMP "Dout[1]" SITE "86"; LOCATE COMP "Dout[1]" SITE "86";
LOCATE COMP "Dout[2]" SITE "87"; LOCATE COMP "Dout[2]" SITE "87";
LOCATE COMP "Dout[3]" SITE "85"; LOCATE COMP "Dout[3]" SITE "85";
LOCATE COMP "Dout[4]" SITE "83"; LOCATE COMP "Dout[4]" SITE "83";
LOCATE COMP "Dout[5]" SITE "84"; LOCATE COMP "Dout[5]" SITE "84";
LOCATE COMP "Dout[6]" SITE "78"; LOCATE COMP "Dout[6]" SITE "78";
LOCATE COMP "Dout[7]" SITE "82"; LOCATE COMP "Dout[7]" SITE "82";
LOCATE COMP "LED" SITE "34"; LOCATE COMP "LED" SITE "34";
LOCATE COMP "MAin[0]" SITE "14"; LOCATE COMP "MAin[0]" SITE "14";
LOCATE COMP "MAin[1]" SITE "12"; LOCATE COMP "MAin[1]" SITE "12";
LOCATE COMP "MAin[2]" SITE "13"; LOCATE COMP "MAin[2]" SITE "13";
LOCATE COMP "MAin[3]" SITE "21"; LOCATE COMP "MAin[3]" SITE "21";
LOCATE COMP "MAin[4]" SITE "20"; LOCATE COMP "MAin[4]" SITE "20";
LOCATE COMP "MAin[5]" SITE "19"; LOCATE COMP "MAin[5]" SITE "19";
LOCATE COMP "MAin[6]" SITE "24"; LOCATE COMP "MAin[6]" SITE "24";
LOCATE COMP "MAin[7]" SITE "18"; LOCATE COMP "MAin[7]" SITE "18";
LOCATE COMP "MAin[8]" SITE "25"; LOCATE COMP "MAin[8]" SITE "25";
LOCATE COMP "MAin[9]" SITE "32"; LOCATE COMP "MAin[9]" SITE "32";
LOCATE COMP "PHI2" SITE "8"; LOCATE COMP "PHI2" SITE "8";
LOCATE COMP "RA[0]" SITE "66"; LOCATE COMP "RA[0]" SITE "66";
LOCATE COMP "RA[10]" SITE "64"; LOCATE COMP "RA[10]" SITE "64";
LOCATE COMP "RA[11]" SITE "59"; LOCATE COMP "RA[11]" SITE "59";
LOCATE COMP "RA[1]" SITE "67"; LOCATE COMP "RA[1]" SITE "67";
LOCATE COMP "RA[2]" SITE "69"; LOCATE COMP "RA[2]" SITE "69";
LOCATE COMP "RA[3]" SITE "71"; LOCATE COMP "RA[3]" SITE "71";
LOCATE COMP "RA[4]" SITE "74"; LOCATE COMP "RA[4]" SITE "74";
LOCATE COMP "RA[5]" SITE "70"; LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68"; LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65"; LOCATE COMP "RA[8]" SITE "65";
LOCATE COMP "RA[9]" SITE "63"; LOCATE COMP "RA[9]" SITE "63";
LOCATE COMP "RBA[0]" SITE "58"; LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60"; LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "62"; LOCATE COMP "RCLK" SITE "62";
LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36"; LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37"; LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38"; LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39"; LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40"; LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41"; LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42"; LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43"; LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "nCCAS" SITE "9"; LOCATE COMP "nCCAS" SITE "9";
LOCATE COMP "nCRAS" SITE "17"; LOCATE COMP "nCRAS" SITE "17";
LOCATE COMP "nFWE" SITE "15"; LOCATE COMP "nFWE" SITE "15";
LOCATE COMP "nRCAS" SITE "52"; LOCATE COMP "nRCAS" SITE "52";
LOCATE COMP "nRCS" SITE "57"; LOCATE COMP "nRCS" SITE "57";
LOCATE COMP "nRRAS" SITE "54"; LOCATE COMP "nRRAS" SITE "54";
LOCATE COMP "nRWE" SITE "49"; LOCATE COMP "nRWE" SITE "49";
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023 Sat Aug 19 21:55:09 2023

453
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1.par
View File

@ -1,237 +1,216 @@
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1. Placement level-cost: 5-1.
Routing Iterations: 6 Routing Iterations: 6
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2GS Design name: RAM2GS
NCD version: 3.3 NCD version: 3.3
Vendor: LATTICE Vendor: LATTICE
Device: LCMXO2-640HC Device: LCMXO2-640HC
Package: TQFP100 Package: TQFP100
Performance: 4 Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39. Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4. Performance Hardware Data Status: Final Version 34.4.
License checked out. License checked out.
Ignore Preference Error(s): True Ignore Preference Error(s): True
Device utilization summary: Device utilization summary:
PIO (prelim) 63+4(JTAG)/80 84% used PIO (prelim) 63+4(JTAG)/80 84% used
63+4(JTAG)/79 85% bonded 63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used IOLOGIC 25/80 31% used
SLICE 117/320 36% used SLICE 113/320 35% used
EFB 1/1 100% used EFB 1/1 100% used
Number of Signals: 380 Number of Signals: 374
Number of Connections: 1008 Number of Connections: 978
Pin Constraint Summary: Pin Constraint Summary:
63 out of 63 pins locked (100% locked). 63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources: The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46) RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 19) PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10) nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources: The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset.
No signal is selected as Global Set/Reset. Starting Placer Phase 0.
Starting Placer Phase 0. ............
.............. Finished Placer Phase 0. REAL time: 0 secs
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
Starting Placer Phase 1. ....................
................... Placer score = 53481.
Placer score = 55012. Finished Placer Phase 1. REAL time: 5 secs
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
Starting Placer Phase 2. .
. Placer score = 53406
Placer score = 54994 Finished Placer Phase 2. REAL time: 5 secs
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
------------------ Clock Report ------------------
Global Clock Resources:
Global Clock Resources: CLK_PIN : 0 out of 8 (0%)
CLK_PIN : 0 out of 8 (0%) General PIO: 4 out of 80 (5%)
General PIO: 4 out of 80 (5%) DCM : 0 out of 2 (0%)
DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 PRIMARY : 3 out of 8 (37%)
SECONDARY: 1 out of 8 (12%)
PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%) --------------- End of Clock Report ---------------
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
I/O Usage Summary (final): 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
63 + 4(JTAG) out of 80 (83.8%) PIO sites used. Number of PIO comps: 63; differential: 0.
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. Number of Vref pins used: 0.
Number of PIO comps: 63; differential: 0.
Number of Vref pins used: 0. I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
I/O Bank Usage Summary: | I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+ +----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref | | 0 | 13 / 19 ( 68%) | 3.3V | - |
+----------+----------------+------------+-----------+ | 1 | 20 / 20 (100%) | 3.3V | - |
| 0 | 13 / 19 ( 68%) | 3.3V | - | | 2 | 12 / 20 ( 60%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - | | 3 | 18 / 20 ( 90%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - | +----------+----------------+------------+-----------+
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+ Total placer CPU time: 5 secs
Total placer CPU time: 3 secs Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. 0 connections routed; 978 unrouted.
Starting router resource preassignment
0 connections routed; 1008 unrouted. WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Starting router resource preassignment WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. Completed router resource preassignment. Real time: 8 secs
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Start NBR router at 21:55:09 08/19/23
Signal=wb_clk loads=1 clock_loads=1
*****************************************************************
Completed router resource preassignment. Real time: 5 secs Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
Start NBR router at 20:59:43 08/16/23 solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
***************************************************************** be completed when no conflicts exist and all connections
Info: NBR allows conflicts(one node used by more than one signal) are routed.
in the earlier iterations. In each iteration, it tries to Note: NBR uses a different method to calculate timing slacks. The
solve the conflicts while keeping the critical connections worst slack and total negative slack may not be the same as
routed as short as possible. The routing process is said to that in TRCE report. You should always run TRCE to verify
be completed when no conflicts exist and all connections your design.
are routed. *****************************************************************
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as Start NBR special constraint process at 21:55:09 08/19/23
that in TRCE report. You should always run TRCE to verify
your design. Start NBR section for initial routing at 21:55:10 08/19/23
***************************************************************** Level 1, iteration 1
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Start NBR special constraint process at 20:59:43 08/16/23 Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1
Start NBR section for initial routing at 20:59:43 08/16/23 0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Level 1, iteration 1 Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; Level 3, iteration 1
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Level 2, iteration 1 Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; Level 4, iteration 1
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Level 3, iteration 1 Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0
Level 4, iteration 1 Info: Initial congestion area at 75% usage is 0 (0.00%)
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Start NBR section for normal routing at 21:55:10 08/19/23
Level 4, iteration 1
Info: Initial congestion level at 75% usage is 0 3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Info: Initial congestion area at 75% usage is 0 (0.00%) Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2
Start NBR section for normal routing at 20:59:43 08/16/23 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Level 1, iteration 1 Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Start NBR section for re-routing at 21:55:10 08/19/23
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Level 4, iteration 1
Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 21:55:10 08/19/23
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
Level 4, iteration 0 End NBR router with 0 unrouted connection
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; NBR Summary
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs -----------
Level 4, iteration 0 Number of unrouted connections : 0 (0.00%)
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Number of connections with timing violations : 0 (0.00%)
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs Estimated worst slack<setup> : 6.966ns
Level 4, iteration 1 Timing score<setup> : 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -----------
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Start NBR section for re-routing at 20:59:44 08/16/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Total CPU time 9 secs
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs Total REAL time: 9 secs
Completely routed.
Start NBR section for post-routing at 20:59:44 08/16/23 End of route. 978 routed (100.00%); 0 unrouted.
End NBR router with 0 unrouted connection Hold time timing score: 0, hold timing errors: 0
NBR Summary Timing score: 0
-----------
Number of unrouted connections : 0 (0.00%) Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 4.922ns
Timing score<setup> : 0 All signals are completely routed.
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
Signal=wb_clk loads=1 clock_loads=1 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
Total CPU time 6 secs PAR_SUMMARY::Number of errors = 0
Total REAL time: 7 secs
Completely routed. Total CPU time to completion: 9 secs
End of route. 1008 routed (100.00%); 0 unrouted. Total REAL time to completion: 10 secs
Hold time timing score: 0, hold timing errors: 0 par done!
Timing score: 0 Note: user must run 'Trace' for timing closure signoff.
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
All signals are completely routed. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.

89
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/5_1_par.asd
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@ -1,47 +1,42 @@
[ActiveSupport PAR] [ActiveSupport PAR]
; Global primary clocks ; Global primary clocks
GLOBAL_PRIMARY_USED = 3; GLOBAL_PRIMARY_USED = 3;
; Global primary clock #0 ; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 46; GLOBAL_PRIMARY_0_LOADNUM = 47;
; Global primary clock #1 ; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_1_LOADNUM = 19; GLOBAL_PRIMARY_1_LOADNUM = 21;
; Global primary clock #2 ; Global primary clock #2
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c; GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_2_LOADNUM = 10; GLOBAL_PRIMARY_2_LOADNUM = 10;
; # of global secondary clocks ; # of global secondary clocks
GLOBAL_SECONDARY_USED = 2; GLOBAL_SECONDARY_USED = 1;
; Global secondary clock #0 ; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i; GLOBAL_SECONDARY_0_SIGNALNAME = nCCAS_c;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE; GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_0_LOADNUM = 10; GLOBAL_SECONDARY_0_LOADNUM = 10;
GLOBAL_SECONDARY_0_SIGTYPE = CE; GLOBAL_SECONDARY_0_SIGTYPE = CLK;
; Global secondary clock #1 ; I/O Bank 0 Usage
GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c; BANK_0_USED = 13;
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO; BANK_0_AVAIL = 19;
GLOBAL_SECONDARY_1_LOADNUM = 10; BANK_0_VCCIO = 3.3V;
GLOBAL_SECONDARY_1_SIGTYPE = CLK; BANK_0_VREF1 = NA;
; I/O Bank 0 Usage ; I/O Bank 1 Usage
BANK_0_USED = 13; BANK_1_USED = 20;
BANK_0_AVAIL = 19; BANK_1_AVAIL = 20;
BANK_0_VCCIO = 3.3V; BANK_1_VCCIO = 3.3V;
BANK_0_VREF1 = NA; BANK_1_VREF1 = NA;
; I/O Bank 1 Usage ; I/O Bank 2 Usage
BANK_1_USED = 20; BANK_2_USED = 12;
BANK_1_AVAIL = 20; BANK_2_AVAIL = 20;
BANK_1_VCCIO = 3.3V; BANK_2_VCCIO = 3.3V;
BANK_1_VREF1 = NA; BANK_2_VREF1 = NA;
; I/O Bank 2 Usage ; I/O Bank 3 Usage
BANK_2_USED = 12; BANK_3_USED = 18;
BANK_2_AVAIL = 20; BANK_3_AVAIL = 20;
BANK_2_VCCIO = 3.3V; BANK_3_VCCIO = 3.3V;
BANK_2_VREF1 = NA; BANK_3_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 18;
BANK_3_AVAIL = 20;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;

54
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.dir/LCMXO2_640HC_impl1.par
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@ -1,27 +1,27 @@
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------ ---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed 5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved. * : Design saved.
Total (real) run time for 1-seed: 7 secs Total (real) run time for 1-seed: 10 secs
par done! par done!
Note: user must run 'Trace' for timing closure signoff. Note: user must run 'Trace' for timing closure signoff.

2
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.drc
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@ -1 +1 @@
DRC detected 0 errors and 0 warnings. DRC detected 0 errors and 0 warnings.

8666
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi
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File diff suppressed because it is too large Load Diff

18
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.htm
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<html> <html>
<head> <head>
<title>syntmp/LCMXO2_640HC_impl1_srr.htm log file</title> <title>syntmp/LCMXO2_640HC_impl1_srr.htm log file</title>
</head> </head>
<frameset cols="20%, 80%"> <frameset cols="20%, 80%">
<frame src="syntmp/LCMXO2_640HC_impl1_toc.htm" name="tocFrame" /> <frame src="syntmp/LCMXO2_640HC_impl1_toc.htm" name="tocFrame" />
<frame src="syntmp/LCMXO2_640HC_impl1_srr.htm" name="srrFrame"/> <frame src="syntmp/LCMXO2_640HC_impl1_srr.htm" name="srrFrame"/>
</frameset> </frameset>
</html> </html>

2868
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed
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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.log
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---- MParTrce Tool Log File ---- ---- MParTrce Tool Log File ----
==== Par Standard Out ==== ==== Par Standard Out ====
==== End of Par Standard Out ==== ==== End of Par Standard Out ====

936
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mrp
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@ -1,468 +1,468 @@
Lattice Mapping Report File for Design Module 'RAM2GS' Lattice Mapping Report File for Design Module 'RAM2GS'
Design Information Design Information
------------------ ------------------
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Target Vendor: LATTICE Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100 Target Device: LCMXO2-640HCTQFP100
Target Performance: 4 Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 08/16/23 20:59:36 Mapped on: 08/19/23 21:54:57
Design Summary Design Summary
-------------- --------------
Number of registers: 109 out of 877 (12%) Number of registers: 111 out of 877 (13%)
PFU registers: 84 out of 640 (13%) PFU registers: 86 out of 640 (13%)
PIO registers: 25 out of 237 (11%) PIO registers: 25 out of 237 (11%)
Number of SLICEs: 117 out of 320 (37%) Number of SLICEs: 113 out of 320 (35%)
SLICEs as Logic/ROM: 117 out of 320 (37%) SLICEs as Logic/ROM: 113 out of 320 (35%)
SLICEs as RAM: 0 out of 240 (0%) SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%) SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 230 out of 640 (36%) Number of LUT4s: 222 out of 640 (35%)
Number used as logic LUTs: 210 Number used as logic LUTs: 202
Number used as distributed RAM: 0 Number used as distributed RAM: 0
Number used as ripple logic: 20 Number used as ripple logic: 20
Number used as shift registers: 0 Number used as shift registers: 0
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%) Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
Number of block RAMs: 0 out of 2 (0%) Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%) Number of GSRs: 0 out of 1 (0%)
EFB used : Yes EFB used : Yes
JTAG used : No JTAG used : No
Readback used : No Readback used : No
Oscillator used : No Oscillator used : No
Startup used : No Startup used : No
POR : On POR : On
Bandgap : On Bandgap : On
Number of Power Controller: 0 out of 1 (0%) Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%) Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%) Number of DCMA: 0 out of 2 (0%)
Notes:- Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic) distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and 2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic. ripple logic.
Number of clocks: 5 Number of clocks: 4
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK ) Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk ) Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) Number of Clock Enables: 6
Number of Clock Enables: 7 Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
Net N_245_i: 1 loads, 1 LSLICEs Net XOR8MEG18: 6 loads, 6 LSLICEs
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Page 1 Page 1
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
Design Summary (cont) Design Summary (cont)
--------------------- ---------------------
Net InitReady: 1 loads, 1 LSLICEs Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs Net un1_FS_38_i: 2 loads, 2 LSLICEs
Net N_18: 2 loads, 2 LSLICEs Net N_253_i: 2 loads, 2 LSLICEs
Net XOR8MEG18: 3 loads, 3 LSLICEs Number of LSRs: 5
Net N_193_i: 2 loads, 2 LSLICEs Net RA10s_i: 1 loads, 0 LSLICEs
Number of LSRs: 5 Net wb_rst10: 3 loads, 3 LSLICEs
Net RA10s_i: 1 loads, 0 LSLICEs Net wb_rst: 1 loads, 0 LSLICEs
Net wb_clk23: 3 loads, 3 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs Net RASr2: 2 loads, 2 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0
Net RASr2: 2 loads, 2 LSLICEs Top 10 highest fanout non-clock nets:
Number of nets driven by tri-state buffers: 0 Net InitReady: 33 loads
Top 10 highest fanout non-clock nets: Net FS[13]: 22 loads
Net InitReady: 42 loads Net FS[12]: 21 loads
Net FS[12]: 27 loads Net FS[14]: 20 loads
Net FS[10]: 25 loads Net wb_rst11: 18 loads
Net FS[11]: 22 loads Net FS[10]: 16 loads
Net FS[7]: 17 loads Net Ready: 16 loads
Net FS[6]: 16 loads Net FS[11]: 15 loads
Net Ready: 15 loads Net FS[9]: 15 loads
Net Ready_fast: 14 loads Net Ready_fast: 14 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
Number of warnings: 1
Number of errors: 0
Number of warnings: 1
Number of errors: 0
Design Errors/Warnings
----------------------
Design Errors/Warnings
---------------------- WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
temporarily disable certain features of the device including Power Functionality is restored after the Flash Memory (UFM/Configuration)
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. Interface is disabled using Disable Configuration Interface command 0x26
Functionality is restored after the Flash Memory (UFM/Configuration) followed by Bypass command 0xFF.
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF. IO (PIO) Attributes
-------------------
IO (PIO) Attributes
------------------- +---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
+---------------------+-----------+-----------+------------+ | | | IO_TYPE | Register |
| IO Name | Direction | Levelmode | IO | +---------------------+-----------+-----------+------------+
| | | IO_TYPE | Register | | RD[0] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | OUT | | Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | | | PHI2 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN | | RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | | | RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
Page 2 Page 2
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont) IO (PIO) Attributes (cont)
-------------------------- --------------------------
| RDQMH | OUTPUT | LVCMOS33 | | | nRCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRCAS | OUTPUT | LVCMOS33 | OUT | | nRRAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVCMOS33 | OUT | | nRWE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRWE | OUTPUT | LVCMOS33 | OUT | | RCKE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | | | RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | | | nRCS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT | | RD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | OUT | | RD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | OUT | | RD[5] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | OUT | | RD[4] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | OUT | | RD[3] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | OUT | | RD[2] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | OUT | | RD[1] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | OUT | | RA[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[11] | OUTPUT | LVCMOS33 | OUT | | RA[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[10] | OUTPUT | LVCMOS33 | OUT | | RA[9] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[9] | OUTPUT | LVCMOS33 | | | RA[8] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[8] | OUTPUT | LVCMOS33 | | | RA[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[7] | OUTPUT | LVCMOS33 | | | RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[6] | OUTPUT | LVCMOS33 | | | RA[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | | | RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | | | RA[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[3] | OUTPUT | LVCMOS33 | | | RA[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[2] | OUTPUT | LVCMOS33 | | | RA[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[1] | OUTPUT | LVCMOS33 | | | RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RA[0] | OUTPUT | LVCMOS33 | | | RBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT | | RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT | | LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
Page 3 Page 3
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont) IO (PIO) Attributes (cont)
-------------------------- --------------------------
| LED | OUTPUT | LVCMOS33 | | | nFWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVCMOS33 | | | nCRAS | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVCMOS33 | | | nCCAS | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nCCAS | INPUT | LVCMOS33 | | | Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | | | Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | | | Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | | | Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | | | Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | | | Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | | | Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | | | Din[7] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | IN | | Din[6] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | IN | | Din[5] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | IN | | Din[4] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | IN | | Din[3] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | IN | | Din[2] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | IN | | Din[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | IN | | Din[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | IN | | CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| CROW[1] | INPUT | LVCMOS33 | | | CROW[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | | | MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | | | MAin[8] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[8] | INPUT | LVCMOS33 | | | MAin[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[7] | INPUT | LVCMOS33 | | | MAin[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[6] | INPUT | LVCMOS33 | | | MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[5] | INPUT | LVCMOS33 | | | MAin[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | | | MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | | | MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
Page 4 Page 4
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
IO (PIO) Attributes (cont) IO (PIO) Attributes (cont)
-------------------------- --------------------------
| MAin[2] | INPUT | LVCMOS33 | | | MAin[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVCMOS33 | | | MAin[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ Removed logic
-------------
Removed logic
------------- Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Block GSR_INST undriven or does not drive anything - clipped. Signal RASr2_i was merged into signal RASr2
Signal nCRAS_c_i was merged into signal nCRAS_c Signal XOR8MEG.CN was merged into signal PHI2_c
Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
Signal InitReady_i was merged into signal InitReady Signal GND undriven or does not drive anything - clipped.
Signal XOR8MEG.CN was merged into signal PHI2_c Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal GND undriven or does not drive anything - clipped. Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped. Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped. Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped. Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped. Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped. Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped. Signal ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped. Signal ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ufmefb/TCOC undriven or does not drive anything - clipped. Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ufmefb/TCINT undriven or does not drive anything - clipped. Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped. Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped. Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped. Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped. Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped. Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Page 5 Page 5
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
Removed logic (cont) Removed logic (cont)
-------------------- --------------------
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped. Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped. Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped. Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped. Signal N_1 undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped. Block nCRAS_pad_RNIBPVB was optimized away.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. Block RASr2_RNIAFR1 was optimized away.
Signal N_1 undriven or does not drive anything - clipped. Block XOR8MEG.CN was optimized away.
Block nCRAS_pad_RNIBPVB was optimized away. Block XOR8MEG_3_u_0_am was optimized away.
Block RASr2_RNIAFR1 was optimized away. Block GND was optimized away.
Block wb_rst_RNO_0 was optimized away. Block ufmefb/VCC was optimized away.
Block XOR8MEG.CN was optimized away. Block ufmefb/GND was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
Embedded Functional Block Connection Summary
--------------------------------------------
Embedded Functional Block Connection Summary Desired WISHBONE clock frequency: 66.7 MHz
-------------------------------------------- Clock source: RCLK_c
Reset source: wb_rst
Desired WISHBONE clock frequency: 62.5 MHz Functions mode:
Clock source: wb_clk I2C #1 (Primary) Function: DISABLED
Reset source: wb_rst I2C #2 (Secondary) Function: DISABLED
Functions mode: SPI Function: DISABLED
I2C #1 (Primary) Function: DISABLED Timer/Counter Function: DISABLED
I2C #2 (Secondary) Function: DISABLED Timer/Counter Mode: WB
SPI Function: DISABLED UFM Connection: ENABLED
Timer/Counter Function: DISABLED PLL0 Connection: DISABLED
Timer/Counter Mode: WB PLL1 Connection: DISABLED
UFM Connection: ENABLED I2C Function Summary:
PLL0 Connection: DISABLED --------------------
PLL1 Connection: DISABLED None
I2C Function Summary: SPI Function Summary:
-------------------- --------------------
None None
SPI Function Summary: Timer/Counter Function Summary:
-------------------- ------------------------------
None None
Timer/Counter Function Summary: UFM Function Summary:
------------------------------ --------------------
None UFM Utilization: General Purpose Flash Memory
Page 6 Page 6
Design: RAM2GS Date: 08/16/23 20:59:36 Design: RAM2GS Date: 08/19/23 21:54:57
Embedded Functional Block Connection Summary (cont) Embedded Functional Block Connection Summary (cont)
--------------------------------------------------- ---------------------------------------------------
UFM Function Summary: Initialized UFM Pages: 1 Pages (1*128 Bits)
-------------------- Available General
UFM Utilization: General Purpose Flash Memory Purpose Flash Memory: 191 Pages (191*128 Bits)
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General EBR Blocks with Unique
Purpose Flash Memory: 191 Pages (191*128 Bits) Initialization Data: 0
EBR Blocks with Unique WID EBR Instance
Initialization Data: 0 --- ------------
WID EBR Instance
--- ------------ ASIC Components
---------------
ASIC Components Instance Name: ufmefb/EFBInst_0
--------------- Type: EFB
Instance Name: ufmefb/EFBInst_0 Run Time and Memory Usage
Type: EFB -------------------------
Run Time and Memory Usage Total CPU Time: 0 secs
------------------------- Total REAL Time: 0 secs
Peak Memory Usage: 57 MB
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 37 MB
Page 7 Page 7
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved. reserved.

9
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.mt Normal file
View File

@ -0,0 +1,9 @@
-v
1
-gt
-mapchkpnt 0
-sethld

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ncd
View File

Binary file not shown.

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngd
View File

Binary file not shown.

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.ngo
View File

Binary file not shown.

18
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.p2t
View File

@ -1,9 +1,9 @@
-w -w
-l 5 -l 5
-i 6 -i 6
-n 1 -n 1
-t 1 -t 1
-s 1 -s 1
-c 0 -c 0
-e 0 -e 0
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1

546
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.pad
View File

@ -1,273 +1,273 @@
PAD Specification File PAD Specification File
*************************** ***************************
PART TYPE: LCMXO2-640HC PART TYPE: LCMXO2-640HC
Performance Grade: 4 Performance Grade: 4
PACKAGE: TQFP100 PACKAGE: TQFP100
Package Status: Final Version 1.39 Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023 Sat Aug 19 21:55:06 2023
Pinout by Port Name: Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | | Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW | | LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | | PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL | | RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | | RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL | | nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW | | nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank: Vccio by Bank:
+------+-------+ +------+-------+
| Bank | Vccio | | Bank | Vccio |
+------+-------+ +------+-------+
| 0 | 3.3V | | 0 | 3.3V |
| 1 | 3.3V | | 1 | 3.3V |
| 2 | 3.3V | | 2 | 3.3V |
| 3 | 3.3V | | 3 | 3.3V |
+------+-------+ +------+-------+
Vref by Bank: Vref by Bank:
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) | | Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
+------+-----+-----------------+---------+ +------+-----+-----------------+---------+
Pinout by Pin Number: Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | | Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | | | 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | | | 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | | 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | | 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
| 7/3 | unused, PULL:DOWN | | | PL3A | | | | | 7/3 | unused, PULL:DOWN | | | PL3A | | | |
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | | | 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | | | 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | | | 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | | | 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | | | 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | | | 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | | | 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | | | 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | | | 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | | | 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | | | 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | | | 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | | | 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | | | 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | | | 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | | | 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
| 28/2 | unused, PULL:DOWN | | | PB4B | | | | | 28/2 | unused, PULL:DOWN | | | PB4B | | | |
| 29/2 | unused, PULL:DOWN | | | PB4C | | | | | 29/2 | unused, PULL:DOWN | | | PB4C | | | |
| 30/2 | unused, PULL:DOWN | | | PB4D | | | | | 30/2 | unused, PULL:DOWN | | | PB4D | | | |
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | | 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | | | 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | | | 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | | 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | | 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | | 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | | 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | | 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | | 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | | 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | | 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | | 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | | | 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | unused, PULL:DOWN | | | PB14B | | | | | 47/2 | unused, PULL:DOWN | | | PB14B | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | | 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | | 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | | | 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | | 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | | | 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | | 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | | | 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | | 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | | 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | | 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | | 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | | 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | | 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | | 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | | 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | | | 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | | | 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | | | 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | | | 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | | | 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | | | 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | | | 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | | | 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | | 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | | | 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | | 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | | | 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | | | 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | | | 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | | | 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | | | 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | | | 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | | 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | | 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | | 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | | 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | | 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | | | 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | | | 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | | | 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | | | 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | | PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins: sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | | Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | | PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | | PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | | PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | | PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+ +----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins: Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "CROW[0]" SITE "10"; LOCATE COMP "CROW[0]" SITE "10";
LOCATE COMP "CROW[1]" SITE "16"; LOCATE COMP "CROW[1]" SITE "16";
LOCATE COMP "Din[0]" SITE "3"; LOCATE COMP "Din[0]" SITE "3";
LOCATE COMP "Din[1]" SITE "96"; LOCATE COMP "Din[1]" SITE "96";
LOCATE COMP "Din[2]" SITE "88"; LOCATE COMP "Din[2]" SITE "88";
LOCATE COMP "Din[3]" SITE "97"; LOCATE COMP "Din[3]" SITE "97";
LOCATE COMP "Din[4]" SITE "99"; LOCATE COMP "Din[4]" SITE "99";
LOCATE COMP "Din[5]" SITE "98"; LOCATE COMP "Din[5]" SITE "98";
LOCATE COMP "Din[6]" SITE "2"; LOCATE COMP "Din[6]" SITE "2";
LOCATE COMP "Din[7]" SITE "1"; LOCATE COMP "Din[7]" SITE "1";
LOCATE COMP "Dout[0]" SITE "76"; LOCATE COMP "Dout[0]" SITE "76";
LOCATE COMP "Dout[1]" SITE "86"; LOCATE COMP "Dout[1]" SITE "86";
LOCATE COMP "Dout[2]" SITE "87"; LOCATE COMP "Dout[2]" SITE "87";
LOCATE COMP "Dout[3]" SITE "85"; LOCATE COMP "Dout[3]" SITE "85";
LOCATE COMP "Dout[4]" SITE "83"; LOCATE COMP "Dout[4]" SITE "83";
LOCATE COMP "Dout[5]" SITE "84"; LOCATE COMP "Dout[5]" SITE "84";
LOCATE COMP "Dout[6]" SITE "78"; LOCATE COMP "Dout[6]" SITE "78";
LOCATE COMP "Dout[7]" SITE "82"; LOCATE COMP "Dout[7]" SITE "82";
LOCATE COMP "LED" SITE "34"; LOCATE COMP "LED" SITE "34";
LOCATE COMP "MAin[0]" SITE "14"; LOCATE COMP "MAin[0]" SITE "14";
LOCATE COMP "MAin[1]" SITE "12"; LOCATE COMP "MAin[1]" SITE "12";
LOCATE COMP "MAin[2]" SITE "13"; LOCATE COMP "MAin[2]" SITE "13";
LOCATE COMP "MAin[3]" SITE "21"; LOCATE COMP "MAin[3]" SITE "21";
LOCATE COMP "MAin[4]" SITE "20"; LOCATE COMP "MAin[4]" SITE "20";
LOCATE COMP "MAin[5]" SITE "19"; LOCATE COMP "MAin[5]" SITE "19";
LOCATE COMP "MAin[6]" SITE "24"; LOCATE COMP "MAin[6]" SITE "24";
LOCATE COMP "MAin[7]" SITE "18"; LOCATE COMP "MAin[7]" SITE "18";
LOCATE COMP "MAin[8]" SITE "25"; LOCATE COMP "MAin[8]" SITE "25";
LOCATE COMP "MAin[9]" SITE "32"; LOCATE COMP "MAin[9]" SITE "32";
LOCATE COMP "PHI2" SITE "8"; LOCATE COMP "PHI2" SITE "8";
LOCATE COMP "RA[0]" SITE "66"; LOCATE COMP "RA[0]" SITE "66";
LOCATE COMP "RA[10]" SITE "64"; LOCATE COMP "RA[10]" SITE "64";
LOCATE COMP "RA[11]" SITE "59"; LOCATE COMP "RA[11]" SITE "59";
LOCATE COMP "RA[1]" SITE "67"; LOCATE COMP "RA[1]" SITE "67";
LOCATE COMP "RA[2]" SITE "69"; LOCATE COMP "RA[2]" SITE "69";
LOCATE COMP "RA[3]" SITE "71"; LOCATE COMP "RA[3]" SITE "71";
LOCATE COMP "RA[4]" SITE "74"; LOCATE COMP "RA[4]" SITE "74";
LOCATE COMP "RA[5]" SITE "70"; LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68"; LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75"; LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65"; LOCATE COMP "RA[8]" SITE "65";
LOCATE COMP "RA[9]" SITE "63"; LOCATE COMP "RA[9]" SITE "63";
LOCATE COMP "RBA[0]" SITE "58"; LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60"; LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53"; LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "62"; LOCATE COMP "RCLK" SITE "62";
LOCATE COMP "RDQMH" SITE "51"; LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48"; LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36"; LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37"; LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38"; LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39"; LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40"; LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41"; LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42"; LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43"; LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "nCCAS" SITE "9"; LOCATE COMP "nCCAS" SITE "9";
LOCATE COMP "nCRAS" SITE "17"; LOCATE COMP "nCRAS" SITE "17";
LOCATE COMP "nFWE" SITE "15"; LOCATE COMP "nFWE" SITE "15";
LOCATE COMP "nRCAS" SITE "52"; LOCATE COMP "nRCAS" SITE "52";
LOCATE COMP "nRCS" SITE "57"; LOCATE COMP "nRCS" SITE "57";
LOCATE COMP "nRRAS" SITE "54"; LOCATE COMP "nRRAS" SITE "54";
LOCATE COMP "nRWE" SITE "49"; LOCATE COMP "nRWE" SITE "49";
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023 Sat Aug 19 21:55:09 2023

507
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.par
View File

@ -1,264 +1,243 @@
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------ ---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed 5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved. * : Design saved.
Total (real) run time for 1-seed: 7 secs Total (real) run time for 1-seed: 10 secs
par done! par done!
Note: user must run 'Trace' for timing closure signoff. Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1. Placement level-cost: 5-1.
Routing Iterations: 6 Routing Iterations: 6
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2GS Design name: RAM2GS
NCD version: 3.3 NCD version: 3.3
Vendor: LATTICE Vendor: LATTICE
Device: LCMXO2-640HC Device: LCMXO2-640HC
Package: TQFP100 Package: TQFP100
Performance: 4 Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39. Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4. Performance Hardware Data Status: Final Version 34.4.
License checked out. License checked out.
Ignore Preference Error(s): True Ignore Preference Error(s): True
Device utilization summary: Device utilization summary:
PIO (prelim) 63+4(JTAG)/80 84% used PIO (prelim) 63+4(JTAG)/80 84% used
63+4(JTAG)/79 85% bonded 63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used IOLOGIC 25/80 31% used
SLICE 117/320 36% used SLICE 113/320 35% used
EFB 1/1 100% used EFB 1/1 100% used
Number of Signals: 380 Number of Signals: 374
Number of Connections: 1008 Number of Connections: 978
Pin Constraint Summary: Pin Constraint Summary:
63 out of 63 pins locked (100% locked). 63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources: The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46) RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 19) PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10) nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources: The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset.
No signal is selected as Global Set/Reset. Starting Placer Phase 0.
Starting Placer Phase 0. ............
.............. Finished Placer Phase 0. REAL time: 0 secs
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
Starting Placer Phase 1. ....................
................... Placer score = 53481.
Placer score = 55012. Finished Placer Phase 1. REAL time: 5 secs
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
Starting Placer Phase 2. .
. Placer score = 53406
Placer score = 54994 Finished Placer Phase 2. REAL time: 5 secs
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
------------------ Clock Report ------------------
Global Clock Resources:
Global Clock Resources: CLK_PIN : 0 out of 8 (0%)
CLK_PIN : 0 out of 8 (0%) General PIO: 4 out of 80 (5%)
General PIO: 4 out of 80 (5%) DCM : 0 out of 2 (0%)
DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19 PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0 PRIMARY : 3 out of 8 (37%)
SECONDARY: 1 out of 8 (12%)
PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%) --------------- End of Clock Report ---------------
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
I/O Usage Summary (final): 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
63 + 4(JTAG) out of 80 (83.8%) PIO sites used. Number of PIO comps: 63; differential: 0.
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. Number of Vref pins used: 0.
Number of PIO comps: 63; differential: 0.
Number of Vref pins used: 0. I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
I/O Bank Usage Summary: | I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+ +----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref | | 0 | 13 / 19 ( 68%) | 3.3V | - |
+----------+----------------+------------+-----------+ | 1 | 20 / 20 (100%) | 3.3V | - |
| 0 | 13 / 19 ( 68%) | 3.3V | - | | 2 | 12 / 20 ( 60%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - | | 3 | 18 / 20 ( 90%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - | +----------+----------------+------------+-----------+
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+ Total placer CPU time: 5 secs
Total placer CPU time: 3 secs Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. 0 connections routed; 978 unrouted.
Starting router resource preassignment
0 connections routed; 1008 unrouted. WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Starting router resource preassignment WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. Completed router resource preassignment. Real time: 8 secs
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Start NBR router at 21:55:09 08/19/23
Signal=wb_clk loads=1 clock_loads=1
*****************************************************************
Completed router resource preassignment. Real time: 5 secs Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
Start NBR router at 20:59:43 08/16/23 solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
***************************************************************** be completed when no conflicts exist and all connections
Info: NBR allows conflicts(one node used by more than one signal) are routed.
in the earlier iterations. In each iteration, it tries to Note: NBR uses a different method to calculate timing slacks. The
solve the conflicts while keeping the critical connections worst slack and total negative slack may not be the same as
routed as short as possible. The routing process is said to that in TRCE report. You should always run TRCE to verify
be completed when no conflicts exist and all connections your design.
are routed. *****************************************************************
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as Start NBR special constraint process at 21:55:09 08/19/23
that in TRCE report. You should always run TRCE to verify
your design. Start NBR section for initial routing at 21:55:10 08/19/23
***************************************************************** Level 1, iteration 1
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Start NBR special constraint process at 20:59:43 08/16/23 Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1
Start NBR section for initial routing at 20:59:43 08/16/23 0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Level 1, iteration 1 Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; Level 3, iteration 1
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Level 2, iteration 1 Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; Level 4, iteration 1
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs 10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Level 3, iteration 1 Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0
Level 4, iteration 1 Info: Initial congestion area at 75% usage is 0 (0.00%)
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Start NBR section for normal routing at 21:55:10 08/19/23
Level 4, iteration 1
Info: Initial congestion level at 75% usage is 0 3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Info: Initial congestion area at 75% usage is 0 (0.00%) Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2
Start NBR section for normal routing at 20:59:43 08/16/23 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Level 1, iteration 1 Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Start NBR section for re-routing at 21:55:10 08/19/23
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs Level 4, iteration 1
Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 21:55:10 08/19/23
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
Level 4, iteration 0 End NBR router with 0 unrouted connection
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; NBR Summary
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs -----------
Level 4, iteration 0 Number of unrouted connections : 0 (0.00%)
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Number of connections with timing violations : 0 (0.00%)
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs Estimated worst slack<setup> : 6.966ns
Level 4, iteration 1 Timing score<setup> : 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -----------
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Start NBR section for re-routing at 20:59:44 08/16/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Total CPU time 9 secs
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs Total REAL time: 9 secs
Completely routed.
Start NBR section for post-routing at 20:59:44 08/16/23 End of route. 978 routed (100.00%); 0 unrouted.
End NBR router with 0 unrouted connection Hold time timing score: 0, hold timing errors: 0
NBR Summary Timing score: 0
-----------
Number of unrouted connections : 0 (0.00%) Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 4.922ns
Timing score<setup> : 0 All signals are completely routed.
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
Signal=wb_clk loads=1 clock_loads=1 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
Total CPU time 6 secs PAR_SUMMARY::Number of errors = 0
Total REAL time: 7 secs
Completely routed. Total CPU time to completion: 9 secs
End of route. 1008 routed (100.00%); 0 unrouted. Total REAL time to completion: 10 secs
Hold time timing score: 0, hold timing errors: 0 par done!
Timing score: 0 Note: user must run 'Trace' for timing closure signoff.
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
All signals are completely routed. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.

150
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.prf
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@ -1,75 +1,75 @@
SCHEMATIC START ; SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023 # map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ; LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "Dout[0]" SITE "76" ; LOCATE COMP "Dout[0]" SITE "76" ;
LOCATE COMP "PHI2" SITE "8" ; LOCATE COMP "PHI2" SITE "8" ;
LOCATE COMP "RDQML" SITE "48" ; LOCATE COMP "RDQML" SITE "48" ;
LOCATE COMP "RDQMH" SITE "51" ; LOCATE COMP "RDQMH" SITE "51" ;
LOCATE COMP "nRCAS" SITE "52" ; LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRRAS" SITE "54" ; LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRWE" SITE "49" ; LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "RCKE" SITE "53" ; LOCATE COMP "RCKE" SITE "53" ;
LOCATE COMP "RCLK" SITE "62" ; LOCATE COMP "RCLK" SITE "62" ;
LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "RD[7]" SITE "43" ; LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ; LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ; LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ; LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ; LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ; LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ; LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[10]" SITE "64" ; LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[9]" SITE "63" ; LOCATE COMP "RA[9]" SITE "63" ;
LOCATE COMP "RA[8]" SITE "65" ; LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[7]" SITE "75" ; LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[6]" SITE "68" ; LOCATE COMP "RA[6]" SITE "68" ;
LOCATE COMP "RA[5]" SITE "70" ; LOCATE COMP "RA[5]" SITE "70" ;
LOCATE COMP "RA[4]" SITE "74" ; LOCATE COMP "RA[4]" SITE "74" ;
LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[3]" SITE "71" ;
LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[2]" SITE "69" ;
LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[1]" SITE "67" ;
LOCATE COMP "RA[0]" SITE "66" ; LOCATE COMP "RA[0]" SITE "66" ;
LOCATE COMP "RBA[1]" SITE "60" ; LOCATE COMP "RBA[1]" SITE "60" ;
LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "RBA[0]" SITE "58" ;
LOCATE COMP "LED" SITE "34" ; LOCATE COMP "LED" SITE "34" ;
LOCATE COMP "nFWE" SITE "15" ; LOCATE COMP "nFWE" SITE "15" ;
LOCATE COMP "nCRAS" SITE "17" ; LOCATE COMP "nCRAS" SITE "17" ;
LOCATE COMP "nCCAS" SITE "9" ; LOCATE COMP "nCCAS" SITE "9" ;
LOCATE COMP "Dout[7]" SITE "82" ; LOCATE COMP "Dout[7]" SITE "82" ;
LOCATE COMP "Dout[6]" SITE "78" ; LOCATE COMP "Dout[6]" SITE "78" ;
LOCATE COMP "Dout[5]" SITE "84" ; LOCATE COMP "Dout[5]" SITE "84" ;
LOCATE COMP "Dout[4]" SITE "83" ; LOCATE COMP "Dout[4]" SITE "83" ;
LOCATE COMP "Dout[3]" SITE "85" ; LOCATE COMP "Dout[3]" SITE "85" ;
LOCATE COMP "Dout[2]" SITE "87" ; LOCATE COMP "Dout[2]" SITE "87" ;
LOCATE COMP "Dout[1]" SITE "86" ; LOCATE COMP "Dout[1]" SITE "86" ;
LOCATE COMP "Din[7]" SITE "1" ; LOCATE COMP "Din[7]" SITE "1" ;
LOCATE COMP "Din[6]" SITE "2" ; LOCATE COMP "Din[6]" SITE "2" ;
LOCATE COMP "Din[5]" SITE "98" ; LOCATE COMP "Din[5]" SITE "98" ;
LOCATE COMP "Din[4]" SITE "99" ; LOCATE COMP "Din[4]" SITE "99" ;
LOCATE COMP "Din[3]" SITE "97" ; LOCATE COMP "Din[3]" SITE "97" ;
LOCATE COMP "Din[2]" SITE "88" ; LOCATE COMP "Din[2]" SITE "88" ;
LOCATE COMP "Din[1]" SITE "96" ; LOCATE COMP "Din[1]" SITE "96" ;
LOCATE COMP "Din[0]" SITE "3" ; LOCATE COMP "Din[0]" SITE "3" ;
LOCATE COMP "CROW[1]" SITE "16" ; LOCATE COMP "CROW[1]" SITE "16" ;
LOCATE COMP "CROW[0]" SITE "10" ; LOCATE COMP "CROW[0]" SITE "10" ;
LOCATE COMP "MAin[9]" SITE "32" ; LOCATE COMP "MAin[9]" SITE "32" ;
LOCATE COMP "MAin[8]" SITE "25" ; LOCATE COMP "MAin[8]" SITE "25" ;
LOCATE COMP "MAin[7]" SITE "18" ; LOCATE COMP "MAin[7]" SITE "18" ;
LOCATE COMP "MAin[6]" SITE "24" ; LOCATE COMP "MAin[6]" SITE "24" ;
LOCATE COMP "MAin[5]" SITE "19" ; LOCATE COMP "MAin[5]" SITE "19" ;
LOCATE COMP "MAin[4]" SITE "20" ; LOCATE COMP "MAin[4]" SITE "20" ;
LOCATE COMP "MAin[3]" SITE "21" ; LOCATE COMP "MAin[3]" SITE "21" ;
LOCATE COMP "MAin[2]" SITE "13" ; LOCATE COMP "MAin[2]" SITE "13" ;
LOCATE COMP "MAin[1]" SITE "12" ; LOCATE COMP "MAin[1]" SITE "12" ;
LOCATE COMP "MAin[0]" SITE "14" ; LOCATE COMP "MAin[0]" SITE "14" ;
FREQUENCY PORT "PHI2" 2.900000 MHz ; FREQUENCY PORT "PHI2" 2.900000 MHz ;
FREQUENCY PORT "nCCAS" 2.900000 MHz ; FREQUENCY PORT "nCCAS" 2.900000 MHz ;
FREQUENCY PORT "nCRAS" 2.900000 MHz ; FREQUENCY PORT "nCRAS" 2.900000 MHz ;
FREQUENCY PORT "RCLK" 62.500000 MHz ; FREQUENCY PORT "RCLK" 62.500000 MHz ;
SCHEMATIC END ; SCHEMATIC END ;
BLOCK RESETPATHS ; BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ; BLOCK ASYNCPATHS ;
COMMERCIAL ; COMMERCIAL ;

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.t2b
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@ -2,4 +2,4 @@
-g RamCfg:Reset -g RamCfg:Reset
-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" -path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC"

423
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.tw1 Normal file
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Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
Physical Path Details:
Data path SLICE_16 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
--------
9.577 (30.6% logic, 69.4% route), 6 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

2219
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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_bgn.html
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@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:58:50 2023 Sat Aug 19 21:55:24 2023
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd. Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
Design name: RAM2GS Design name: RAM2GS
@ -91,9 +91,9 @@ UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190). Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 1 secs Total CPU Time: 3 secs
Total REAL Time: 2 secs Total REAL Time: 3 secs
Peak Memory Usage: 246 MB Peak Memory Usage: 266 MB

306
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_cck.rpt
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@ -1,153 +1,153 @@
Copyright (C) 1994-2021 Synopsys, Inc. Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited. Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R) Tool: Synplify Pro (R)
Build: R-2021.03L-SP1 Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2 OS: Windows 6.2
Hostname: ZANEPC Hostname: ZANEMACWIN11
Implementation : impl1 Implementation : impl1
# Written on Wed Aug 16 20:59:31 2023 # Written on Sat Aug 19 21:54:51 2023
##### DESIGN INFO ####################################################### ##### DESIGN INFO #######################################################
Top View: "RAM2GS" Top View: "RAM2GS"
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
##### SUMMARY ############################################################ ##### SUMMARY ############################################################
Found 0 issues in 0 out of 4 constraints Found 0 issues in 0 out of 4 constraints
##### DETAILS ############################################################ ##### DETAILS ############################################################
Clock Relationships Clock Relationships
******************* *******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 | No paths | No paths | No paths System RCLK | 16.000 | No paths | No paths | No paths
RCLK System | 16.000 | No paths | No paths | No paths RCLK System | 16.000 | No paths | No paths | No paths
RCLK RCLK | 16.000 | No paths | No paths | No paths RCLK RCLK | 16.000 | No paths | No paths | No paths
RCLK PHI2 | 2.000 | No paths | 1.000 | No paths RCLK PHI2 | 2.000 | No paths | 1.000 | No paths
RCLK nCRAS | No paths | No paths | 1.000 | No paths RCLK nCRAS | No paths | No paths | 1.000 | No paths
PHI2 RCLK | No paths | No paths | No paths | 1.000 PHI2 RCLK | No paths | No paths | No paths | 1.000
PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000 PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
nCRAS RCLK | No paths | No paths | No paths | 1.000 nCRAS RCLK | No paths | No paths | No paths | 1.000
=================================================================================================================================== ===================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small. @W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small. @W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small. @W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small. @W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
Unconstrained Start/End Points Unconstrained Start/End Points
****************************** ******************************
p:CROW[0] p:CROW[0]
p:CROW[1] p:CROW[1]
p:Din[0] p:Din[0]
p:Din[1] p:Din[1]
p:Din[2] p:Din[2]
p:Din[3] p:Din[3]
p:Din[4] p:Din[4]
p:Din[5] p:Din[5]
p:Din[6] p:Din[6]
p:Din[7] p:Din[7]
p:Dout[0] p:Dout[0]
p:Dout[1] p:Dout[1]
p:Dout[2] p:Dout[2]
p:Dout[3] p:Dout[3]
p:Dout[4] p:Dout[4]
p:Dout[5] p:Dout[5]
p:Dout[6] p:Dout[6]
p:Dout[7] p:Dout[7]
p:MAin[0] p:MAin[0]
p:MAin[1] p:MAin[1]
p:MAin[2] p:MAin[2]
p:MAin[3] p:MAin[3]
p:MAin[4] p:MAin[4]
p:MAin[5] p:MAin[5]
p:MAin[6] p:MAin[6]
p:MAin[7] p:MAin[7]
p:MAin[8] p:MAin[8]
p:MAin[9] p:MAin[9]
p:RA[0] p:RA[0]
p:RA[1] p:RA[1]
p:RA[2] p:RA[2]
p:RA[3] p:RA[3]
p:RA[4] p:RA[4]
p:RA[5] p:RA[5]
p:RA[6] p:RA[6]
p:RA[7] p:RA[7]
p:RA[8] p:RA[8]
p:RA[9] p:RA[9]
p:RA[10] p:RA[10]
p:RA[11] p:RA[11]
p:RBA[0] p:RBA[0]
p:RBA[1] p:RBA[1]
p:RCKE p:RCKE
p:RDQMH p:RDQMH
p:RDQML p:RDQML
p:RD[0] (bidir end point) p:RD[0] (bidir end point)
p:RD[0] (bidir start point) p:RD[0] (bidir start point)
p:RD[1] (bidir end point) p:RD[1] (bidir end point)
p:RD[1] (bidir start point) p:RD[1] (bidir start point)
p:RD[2] (bidir end point) p:RD[2] (bidir end point)
p:RD[2] (bidir start point) p:RD[2] (bidir start point)
p:RD[3] (bidir end point) p:RD[3] (bidir end point)
p:RD[3] (bidir start point) p:RD[3] (bidir start point)
p:RD[4] (bidir end point) p:RD[4] (bidir end point)
p:RD[4] (bidir start point) p:RD[4] (bidir start point)
p:RD[5] (bidir end point) p:RD[5] (bidir end point)
p:RD[5] (bidir start point) p:RD[5] (bidir start point)
p:RD[6] (bidir end point) p:RD[6] (bidir end point)
p:RD[6] (bidir start point) p:RD[6] (bidir start point)
p:RD[7] (bidir end point) p:RD[7] (bidir end point)
p:RD[7] (bidir start point) p:RD[7] (bidir start point)
p:nFWE p:nFWE
p:nRCAS p:nRCAS
p:nRCS p:nRCS
p:nRRAS p:nRRAS
p:nRWE p:nRWE
Inapplicable constraints Inapplicable constraints
************************ ************************
(none) (none)
Applicable constraints with issues Applicable constraints with issues
********************************** **********************************
(none) (none)
Constraints with matching wildcard expressions Constraints with matching wildcard expressions
********************************************** **********************************************
(none) (none)
Library Report Library Report
************** **************
# End of Constraint Checker Report # End of Constraint Checker Report

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<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
// Design: RAM2GS
// Package: TQFP100
// ncd File: lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Sat Aug 19 21:55:13 2023
// M: Minimum Performance Grade
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 6, 5, 4):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.553 4 -0.117 M
CROW[1] nCRAS F 2.019 4 0.001 M
Din[0] PHI2 F 4.715 4 3.636 4
Din[0] nCCAS F 0.790 4 0.535 4
Din[1] PHI2 F 5.021 4 3.516 4
Din[1] nCCAS F 1.086 4 0.264 4
Din[2] PHI2 F 3.385 4 3.516 4
Din[2] nCCAS F 0.282 4 0.948 4
Din[3] PHI2 F 4.644 4 3.516 4
Din[3] nCCAS F 1.278 4 0.095 4
Din[4] PHI2 F 4.335 4 3.516 4
Din[4] nCCAS F 2.446 4 -0.199 M
Din[5] PHI2 F 3.662 4 3.516 4
Din[5] nCCAS F 0.907 4 0.402 4
Din[6] PHI2 F 4.869 4 3.636 4
Din[6] nCCAS F 1.378 4 0.023 M
Din[7] PHI2 F 4.138 4 3.636 4
Din[7] nCCAS F 2.072 4 -0.120 M
MAin[0] PHI2 F 5.613 4 0.006 M
MAin[0] nCRAS F 0.244 4 1.146 4
MAin[1] PHI2 F 3.409 4 0.354 6
MAin[1] nCRAS F 0.244 4 1.146 4
MAin[2] PHI2 F 5.391 4 0.132 M
MAin[2] nCRAS F 0.250 4 1.141 4
MAin[3] PHI2 F 4.627 4 0.087 M
MAin[3] nCRAS F 0.507 4 0.910 4
MAin[4] PHI2 F 5.665 4 -0.133 M
MAin[4] nCRAS F 0.675 4 0.777 4
MAin[5] PHI2 F 5.569 4 0.129 M
MAin[5] nCRAS F 0.050 4 1.238 4
MAin[6] PHI2 F 5.717 4 -0.141 M
MAin[6] nCRAS F 0.242 4 1.146 4
MAin[7] PHI2 F 5.943 4 -0.173 M
MAin[7] nCRAS F 0.170 4 1.228 4
MAin[8] nCRAS F 0.759 4 0.696 4
MAin[9] nCRAS F 0.516 4 0.891 4
PHI2 RCLK R -0.312 M 3.167 4
nCCAS RCLK R 2.600 4 -0.176 M
nCCAS nCRAS F 3.106 4 -0.235 M
nCRAS RCLK R 1.803 4 -0.055 M
nFWE PHI2 F 4.680 4 0.261 M
nFWE nCRAS F 2.234 4 1.143 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 9.922 4 2.878 M
LED nCRAS F 10.555 4 3.057 M
RA[0] RCLK R 11.638 4 3.406 M
RA[0] nCRAS F 11.771 4 3.430 M
RA[10] RCLK R 8.141 4 2.620 M
RA[11] PHI2 R 8.610 4 2.756 M
RA[1] RCLK R 11.674 4 3.407 M
RA[1] nCRAS F 10.635 4 3.155 M
RA[2] RCLK R 12.933 4 3.729 M
RA[2] nCRAS F 11.858 4 3.449 M
RA[3] RCLK R 12.587 4 3.664 M
RA[3] nCRAS F 11.255 4 3.298 M
RA[4] RCLK R 11.721 4 3.433 M
RA[4] nCRAS F 11.153 4 3.297 M
RA[5] RCLK R 12.544 4 3.620 M
RA[5] nCRAS F 11.480 4 3.360 M
RA[6] RCLK R 12.984 4 3.775 M
RA[6] nCRAS F 11.528 4 3.407 M
RA[7] RCLK R 12.553 4 3.625 M
RA[7] nCRAS F 11.610 4 3.368 M
RA[8] RCLK R 11.836 4 3.453 M
RA[8] nCRAS F 10.797 4 3.201 M
RA[9] RCLK R 11.182 4 3.271 M
RA[9] nCRAS F 11.135 4 3.279 M
RBA[0] nCRAS F 8.439 4 2.703 M
RBA[1] nCRAS F 8.439 4 2.703 M
RCKE RCLK R 10.083 4 3.081 M
RDQMH RCLK R 11.381 4 3.325 M
RDQML RCLK R 10.735 4 3.173 M
RD[0] nCCAS F 8.223 4 2.594 M
RD[1] nCCAS F 8.223 4 2.594 M
RD[2] nCCAS F 8.223 4 2.594 M
RD[3] nCCAS F 8.223 4 2.594 M
RD[4] nCCAS F 8.223 4 2.594 M
RD[5] nCCAS F 8.223 4 2.594 M
RD[6] nCCAS F 8.223 4 2.594 M
RD[7] nCCAS F 8.223 4 2.594 M
nRCAS RCLK R 8.141 4 2.620 M
nRCS RCLK R 8.141 4 2.620 M
nRRAS RCLK R 8.141 4 2.620 M
nRWE RCLK R 8.121 4 2.627 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M
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48
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.asd
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@ -1,24 +1,24 @@
[ActiveSupport MAP] [ActiveSupport MAP]
Device = LCMXO2-640HC; Device = LCMXO2-640HC;
Package = TQFP100; Package = TQFP100;
Performance = 4; Performance = 4;
LUTS_avail = 640; LUTS_avail = 640;
LUTS_used = 230; LUTS_used = 222;
FF_avail = 719; FF_avail = 719;
FF_used = 109; FF_used = 111;
INPUT_LVCMOS33 = 25; INPUT_LVCMOS33 = 25;
OUTPUT_LVCMOS33 = 30; OUTPUT_LVCMOS33 = 30;
BIDI_LVCMOS33 = 8; BIDI_LVCMOS33 = 8;
IO_avail = 79; IO_avail = 79;
IO_used = 63; IO_used = 63;
EBR_avail = 2; EBR_avail = 2;
EBR_used = 0; EBR_used = 0;
; ;
; start of EFB statistics ; start of EFB statistics
I2C = 0; I2C = 0;
SPI = 0; SPI = 0;
TimerCounter = 0; TimerCounter = 0;
UFM = 1; UFM = 1;
PLL = 0; PLL = 0;
; end of EFB statistics ; end of EFB statistics
; ;

289
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam
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@ -1,145 +1,144 @@
[ START MERGED ] [ START MERGED ]
RASr2_i RASr2 RASr2_i RASr2
XOR8MEG.CN PHI2_c XOR8MEG.CN PHI2_c
nCRAS_c_i nCRAS_c XOR8MEG_3_u_0_am XOR8MEG
InitReady_i InitReady nCRAS_c_i nCRAS_c
[ END MERGED ] [ END MERGED ]
[ START CLIPPED ] [ START CLIPPED ]
GND GND
ufmefb/VCC ufmefb/VCC
ufmefb/GND ufmefb/GND
FS_s_0_S1[17] FS_s_0_S1[17]
FS_s_0_COUT[17] FS_s_0_COUT[17]
ufmefb/CFGSTDBY ufmefb/CFGSTDBY
ufmefb/CFGWAKE ufmefb/CFGWAKE
ufmefb/wbc_ufm_irq ufmefb/wbc_ufm_irq
ufmefb/TCOC ufmefb/TCOC
ufmefb/TCINT ufmefb/TCINT
ufmefb/SPIIRQO ufmefb/SPIIRQO
ufmefb/SPICSNEN ufmefb/SPICSNEN
ufmefb/SPIMCSN7 ufmefb/SPIMCSN7
ufmefb/SPIMCSN6 ufmefb/SPIMCSN6
ufmefb/SPIMCSN5 ufmefb/SPIMCSN5
ufmefb/SPIMCSN4 ufmefb/SPIMCSN4
ufmefb/SPIMCSN3 ufmefb/SPIMCSN3
ufmefb/SPIMCSN2 ufmefb/SPIMCSN2
ufmefb/SPIMCSN1 ufmefb/SPIMCSN1
ufmefb/SPIMCSN0 ufmefb/SPIMCSN0
ufmefb/SPIMOSIEN ufmefb/SPIMOSIEN
ufmefb/SPIMOSIO ufmefb/SPIMOSIO
ufmefb/SPIMISOEN ufmefb/SPIMISOEN
ufmefb/SPIMISOO ufmefb/SPIMISOO
ufmefb/SPISCKEN ufmefb/SPISCKEN
ufmefb/SPISCKO ufmefb/SPISCKO
ufmefb/I2C2IRQO ufmefb/I2C2IRQO
ufmefb/I2C1IRQO ufmefb/I2C1IRQO
ufmefb/I2C2SDAOEN ufmefb/I2C2SDAOEN
ufmefb/I2C2SDAO ufmefb/I2C2SDAO
ufmefb/I2C2SCLOEN ufmefb/I2C2SCLOEN
ufmefb/I2C2SCLO ufmefb/I2C2SCLO
ufmefb/I2C1SDAOEN ufmefb/I2C1SDAOEN
ufmefb/I2C1SDAO ufmefb/I2C1SDAO
ufmefb/I2C1SCLOEN ufmefb/I2C1SCLOEN
ufmefb/I2C1SCLO ufmefb/I2C1SCLO
ufmefb/PLLDATO0 ufmefb/PLLDATO0
ufmefb/PLLDATO1 ufmefb/PLLDATO1
ufmefb/PLLDATO2 ufmefb/PLLDATO2
ufmefb/PLLDATO3 ufmefb/PLLDATO3
ufmefb/PLLDATO4 ufmefb/PLLDATO4
ufmefb/PLLDATO5 ufmefb/PLLDATO5
ufmefb/PLLDATO6 ufmefb/PLLDATO6
ufmefb/PLLDATO7 ufmefb/PLLDATO7
ufmefb/PLLADRO0 ufmefb/PLLADRO0
ufmefb/PLLADRO1 ufmefb/PLLADRO1
ufmefb/PLLADRO2 ufmefb/PLLADRO2
ufmefb/PLLADRO3 ufmefb/PLLADRO3
ufmefb/PLLADRO4 ufmefb/PLLADRO4
ufmefb/PLLWEO ufmefb/PLLWEO
ufmefb/PLL1STBO ufmefb/PLL1STBO
ufmefb/PLL0STBO ufmefb/PLL0STBO
ufmefb/PLLRSTO ufmefb/PLLRSTO
ufmefb/PLLCLKO ufmefb/PLLCLKO
ufmefb/wb_ack_o ufmefb/wb_dat_o_1[2]
ufmefb/wb_dat_o_1[2] ufmefb/wb_dat_o_1[3]
ufmefb/wb_dat_o_1[3] ufmefb/wb_dat_o_1[4]
ufmefb/wb_dat_o_1[4] ufmefb/wb_dat_o_1[5]
ufmefb/wb_dat_o_1[5] ufmefb/wb_dat_o_1[6]
ufmefb/wb_dat_o_1[6] ufmefb/wb_dat_o_1[7]
ufmefb/wb_dat_o_1[7] FS_cry_0_S0[0]
FS_cry_0_S0[0] N_1
N_1 [ END CLIPPED ]
[ END CLIPPED ] [ START DESIGN PREFS ]
[ START DESIGN PREFS ] SCHEMATIC START ;
SCHEMATIC START ; # map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "RD[0]" SITE "36" ; LOCATE COMP "Dout[0]" SITE "76" ;
LOCATE COMP "Dout[0]" SITE "76" ; LOCATE COMP "PHI2" SITE "8" ;
LOCATE COMP "PHI2" SITE "8" ; LOCATE COMP "RDQML" SITE "48" ;
LOCATE COMP "RDQML" SITE "48" ; LOCATE COMP "RDQMH" SITE "51" ;
LOCATE COMP "RDQMH" SITE "51" ; LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRCAS" SITE "52" ; LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRRAS" SITE "54" ; LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "nRWE" SITE "49" ; LOCATE COMP "RCKE" SITE "53" ;
LOCATE COMP "RCKE" SITE "53" ; LOCATE COMP "RCLK" SITE "62" ;
LOCATE COMP "RCLK" SITE "62" ; LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "nRCS" SITE "57" ; LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[7]" SITE "43" ; LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[6]" SITE "42" ; LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[5]" SITE "41" ; LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[4]" SITE "40" ; LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[3]" SITE "39" ; LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[2]" SITE "38" ; LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RD[1]" SITE "37" ; LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[11]" SITE "59" ; LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[10]" SITE "64" ; LOCATE COMP "RA[9]" SITE "63" ;
LOCATE COMP "RA[9]" SITE "63" ; LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[8]" SITE "65" ; LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[7]" SITE "75" ; LOCATE COMP "RA[6]" SITE "68" ;
LOCATE COMP "RA[6]" SITE "68" ; LOCATE COMP "RA[5]" SITE "70" ;
LOCATE COMP "RA[5]" SITE "70" ; LOCATE COMP "RA[4]" SITE "74" ;
LOCATE COMP "RA[4]" SITE "74" ; LOCATE COMP "RA[3]" SITE "71" ;
LOCATE COMP "RA[3]" SITE "71" ; LOCATE COMP "RA[2]" SITE "69" ;
LOCATE COMP "RA[2]" SITE "69" ; LOCATE COMP "RA[1]" SITE "67" ;
LOCATE COMP "RA[1]" SITE "67" ; LOCATE COMP "RA[0]" SITE "66" ;
LOCATE COMP "RA[0]" SITE "66" ; LOCATE COMP "RBA[1]" SITE "60" ;
LOCATE COMP "RBA[1]" SITE "60" ; LOCATE COMP "RBA[0]" SITE "58" ;
LOCATE COMP "RBA[0]" SITE "58" ; LOCATE COMP "LED" SITE "34" ;
LOCATE COMP "LED" SITE "34" ; LOCATE COMP "nFWE" SITE "15" ;
LOCATE COMP "nFWE" SITE "15" ; LOCATE COMP "nCRAS" SITE "17" ;
LOCATE COMP "nCRAS" SITE "17" ; LOCATE COMP "nCCAS" SITE "9" ;
LOCATE COMP "nCCAS" SITE "9" ; LOCATE COMP "Dout[7]" SITE "82" ;
LOCATE COMP "Dout[7]" SITE "82" ; LOCATE COMP "Dout[6]" SITE "78" ;
LOCATE COMP "Dout[6]" SITE "78" ; LOCATE COMP "Dout[5]" SITE "84" ;
LOCATE COMP "Dout[5]" SITE "84" ; LOCATE COMP "Dout[4]" SITE "83" ;
LOCATE COMP "Dout[4]" SITE "83" ; LOCATE COMP "Dout[3]" SITE "85" ;
LOCATE COMP "Dout[3]" SITE "85" ; LOCATE COMP "Dout[2]" SITE "87" ;
LOCATE COMP "Dout[2]" SITE "87" ; LOCATE COMP "Dout[1]" SITE "86" ;
LOCATE COMP "Dout[1]" SITE "86" ; LOCATE COMP "Din[7]" SITE "1" ;
LOCATE COMP "Din[7]" SITE "1" ; LOCATE COMP "Din[6]" SITE "2" ;
LOCATE COMP "Din[6]" SITE "2" ; LOCATE COMP "Din[5]" SITE "98" ;
LOCATE COMP "Din[5]" SITE "98" ; LOCATE COMP "Din[4]" SITE "99" ;
LOCATE COMP "Din[4]" SITE "99" ; LOCATE COMP "Din[3]" SITE "97" ;
LOCATE COMP "Din[3]" SITE "97" ; LOCATE COMP "Din[2]" SITE "88" ;
LOCATE COMP "Din[2]" SITE "88" ; LOCATE COMP "Din[1]" SITE "96" ;
LOCATE COMP "Din[1]" SITE "96" ; LOCATE COMP "Din[0]" SITE "3" ;
LOCATE COMP "Din[0]" SITE "3" ; LOCATE COMP "CROW[1]" SITE "16" ;
LOCATE COMP "CROW[1]" SITE "16" ; LOCATE COMP "CROW[0]" SITE "10" ;
LOCATE COMP "CROW[0]" SITE "10" ; LOCATE COMP "MAin[9]" SITE "32" ;
LOCATE COMP "MAin[9]" SITE "32" ; LOCATE COMP "MAin[8]" SITE "25" ;
LOCATE COMP "MAin[8]" SITE "25" ; LOCATE COMP "MAin[7]" SITE "18" ;
LOCATE COMP "MAin[7]" SITE "18" ; LOCATE COMP "MAin[6]" SITE "24" ;
LOCATE COMP "MAin[6]" SITE "24" ; LOCATE COMP "MAin[5]" SITE "19" ;
LOCATE COMP "MAin[5]" SITE "19" ; LOCATE COMP "MAin[4]" SITE "20" ;
LOCATE COMP "MAin[4]" SITE "20" ; LOCATE COMP "MAin[3]" SITE "21" ;
LOCATE COMP "MAin[3]" SITE "21" ; LOCATE COMP "MAin[2]" SITE "13" ;
LOCATE COMP "MAin[2]" SITE "13" ; LOCATE COMP "MAin[1]" SITE "12" ;
LOCATE COMP "MAin[1]" SITE "12" ; LOCATE COMP "MAin[0]" SITE "14" ;
LOCATE COMP "MAin[0]" SITE "14" ; FREQUENCY PORT "PHI2" 2.900000 MHz ;
FREQUENCY PORT "PHI2" 2.900000 MHz ; FREQUENCY PORT "nCCAS" 2.900000 MHz ;
FREQUENCY PORT "nCCAS" 2.900000 MHz ; FREQUENCY PORT "nCRAS" 2.900000 MHz ;
FREQUENCY PORT "nCRAS" 2.900000 MHz ; FREQUENCY PORT "RCLK" 62.500000 MHz ;
FREQUENCY PORT "RCLK" 62.500000 MHz ; SCHEMATIC END ;
SCHEMATIC END ; [ END DESIGN PREFS ]
[ END DESIGN PREFS ]

42
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.hrr
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@ -1,20 +1,22 @@
--------------------------------------------------- ---------------------------------------------------
Report for cell RAM2GS Report for cell RAM2GS
Instance path: RAM2GS Instance path: RAM2GS
Cell usage: Cell usage:
cell count Res Usage(%) cell count Res Usage(%)
SLIC 117.00 100.0 SLIC 113.00 100.0
IOLGC 25.00 100.0 IOLGC 25.00 100.0
LUT4 210.00 100.0 LUT4 202.00 100.0
IOREG 25 100.0 IOREG 25 100.0
IOBUF 63 100.0 IOBUF 63 100.0
PFUREG 84 100.0 PFUREG 86 100.0
RIPPLE 10 100.0 RIPPLE 10 100.0
SUB MODULES SUB MODULES
cell count SLC Usage(%) cell count SLC Usage(%)
REFB 1 0.0 REFB 1 0.4
--------------------------------------------------- ---------------------------------------------------
Report for cell REFB Report for cell REFB
Instance path: RAM2GS/ufmefb Instance path: RAM2GS/ufmefb
Cell usage: Cell usage:
cell count Res Usage(%) cell count Res Usage(%)
SLIC 0.50 0.4
LUT4 1.00 0.5

BIN
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.ncd
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88
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_mrp.html
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@ -15,27 +15,27 @@
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Target Vendor: LATTICE Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100 Target Device: LCMXO2-640HCTQFP100
Target Performance: 4 Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 08/16/23 20:59:36 Mapped on: 08/19/23 21:54:57
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B> <A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 109 out of 877 (12%) Number of registers: 111 out of 877 (13%)
PFU registers: 84 out of 640 (13%) PFU registers: 86 out of 640 (13%)
PIO registers: 25 out of 237 (11%) PIO registers: 25 out of 237 (11%)
Number of SLICEs: 117 out of 320 (37%) Number of SLICEs: 113 out of 320 (35%)
SLICEs as Logic/ROM: 117 out of 320 (37%) SLICEs as Logic/ROM: 113 out of 320 (35%)
SLICEs as RAM: 0 out of 240 (0%) SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%) SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 230 out of 640 (36%) Number of LUT4s: 222 out of 640 (35%)
Number used as logic LUTs: 210 Number used as logic LUTs: 202
Number used as distributed RAM: 0 Number used as distributed RAM: 0
Number used as ripple logic: 20 Number used as ripple logic: 20
Number used as shift registers: 0 Number used as shift registers: 0
@ -58,39 +58,37 @@ Mapped on: 08/16/23 20:59:36
distributed RAMs) + 2*(Number of ripple logic) distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and 2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic. ripple logic.
Number of clocks: 5 Number of clocks: 4
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 ) Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK ) Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS ) Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS ) Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 7 Number of Clock Enables: 6
Net N_245_i: 1 loads, 1 LSLICEs Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs Net XOR8MEG18: 6 loads, 6 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Net InitReady: 1 loads, 1 LSLICEs Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs Net un1_FS_38_i: 2 loads, 2 LSLICEs
Net N_18: 2 loads, 2 LSLICEs Net N_253_i: 2 loads, 2 LSLICEs
Net XOR8MEG18: 3 loads, 3 LSLICEs
Net N_193_i: 2 loads, 2 LSLICEs
Number of LSRs: 5 Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs Net RA10s_i: 1 loads, 0 LSLICEs
Net wb_clk23: 3 loads, 3 LSLICEs Net wb_rst10: 3 loads, 3 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs Net wb_rst: 1 loads, 0 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net RASr2: 2 loads, 2 LSLICEs Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0 Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets: Top 10 highest fanout non-clock nets:
Net InitReady: 42 loads Net InitReady: 33 loads
Net FS[12]: 27 loads Net FS[13]: 22 loads
Net FS[10]: 25 loads Net FS[12]: 21 loads
Net FS[11]: 22 loads Net FS[14]: 20 loads
Net FS[7]: 17 loads Net wb_rst11: 18 loads
Net FS[6]: 16 loads Net FS[10]: 16 loads
Net Ready: 15 loads Net Ready: 16 loads
Net FS[11]: 15 loads
Net FS[9]: 15 loads
Net Ready_fast: 14 loads Net Ready_fast: 14 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
@ -127,9 +125,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | | | RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RDQMH | OUTPUT | LVCMOS33 | | | RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRCAS | OUTPUT | LVCMOS33 | OUT | | nRCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVCMOS33 | OUT | | nRRAS | OUTPUT | LVCMOS33 | OUT |
@ -184,9 +182,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT | | RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | | | LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVCMOS33 | | | nFWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVCMOS33 | | | nCRAS | INPUT | LVCMOS33 | |
@ -241,9 +239,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | | | MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[2] | INPUT | LVCMOS33 | | | MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVCMOS33 | | | MAin[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+ +---------------------+-----------+-----------+------------+
| MAin[0] | INPUT | LVCMOS33 | | | MAin[0] | INPUT | LVCMOS33 | |
@ -256,8 +254,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
Block GSR_INST undriven or does not drive anything - clipped. Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2 Signal RASr2_i was merged into signal RASr2
Signal InitReady_i was merged into signal InitReady
Signal XOR8MEG.CN was merged into signal PHI2_c Signal XOR8MEG.CN was merged into signal PHI2_c
Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
Signal GND undriven or does not drive anything - clipped. Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped. Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped. Signal ufmefb/GND undriven or does not drive anything - clipped.
@ -299,9 +297,9 @@ Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
@ -313,7 +311,6 @@ Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped. Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
@ -324,8 +321,8 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped. Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away. Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away. Block RASr2_RNIAFR1 was optimized away.
Block wb_rst_RNO_0 was optimized away.
Block XOR8MEG.CN was optimized away. Block XOR8MEG.CN was optimized away.
Block XOR8MEG_3_u_0_am was optimized away.
Block GND was optimized away. Block GND was optimized away.
Block ufmefb/VCC was optimized away. Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away. Block ufmefb/GND was optimized away.
@ -336,8 +333,8 @@ Block ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B> <A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 62.5 MHz Desired WISHBONE clock frequency: 66.7 MHz
Clock source: wb_clk Clock source: RCLK_c
Reset source: wb_rst Reset source: wb_rst
Functions mode: Functions mode:
I2C #1 (Primary) Function: DISABLED I2C #1 (Primary) Function: DISABLED
@ -357,10 +354,10 @@ Block ufmefb/GND was optimized away.
Timer/Counter Function Summary: Timer/Counter Function Summary:
------------------------------ ------------------------------
None None
UFM Function Summary: UFM Function Summary:
-------------------- --------------------
UFM Utilization: General Purpose Flash Memory UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits) Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General Available General
Purpose Flash Memory: 191 Pages (191*128 Bits) Purpose Flash Memory: 191 Pages (191*128 Bits)
@ -387,7 +384,7 @@ Instance Name: ufmefb/EFBInst_0
Total CPU Time: 0 secs Total CPU Time: 0 secs
Total REAL Time: 0 secs Total REAL Time: 0 secs
Peak Memory Usage: 37 MB Peak Memory Usage: 57 MB
@ -417,6 +414,9 @@ Instance Name: ufmefb/EFBInst_0

18
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_multi_srs_gen.htm
View File

@ -1,9 +1,9 @@
<html> <html>
<head> <head>
<title>syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file</title> <title>syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file</title>
</head> </head>
<frameset cols="20%, 80%"> <frameset cols="20%, 80%">
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm" name="tocFrame" /> <frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm" name="tocFrame" />
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm" name="srrFrame"/> <frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm" name="srrFrame"/>
</frameset> </frameset>
</html> </html>

2
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_ngd.asd
View File

@ -1 +1 @@
[ActiveSupport NGD] [ActiveSupport NGD]

4
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_pad.html
View File

@ -14,7 +14,7 @@ Performance Grade: 4
PACKAGE: TQFP100 PACKAGE: TQFP100
Package Status: Final Version 1.39 Package Status: Final Version 1.39
Wed Aug 16 20:59:41 2023 Sat Aug 19 21:55:06 2023
Pinout by Port Name: Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:42 2023 Sat Aug 19 21:55:09 2023

125
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_par.html
View File

@ -12,11 +12,11 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
@ -25,22 +25,22 @@ Preference file: LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------ ---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 4.922 0 0.088 0 07 Completed 5_1 * 0 6.966 0 0.304 0 10 Completed
* : Design saved. * : Design saved.
Total (real) run time for 1-seed: 7 secs Total (real) run time for 1-seed: 10 secs
par done! par done!
Note: user must run &apos;Trace&apos; for timing closure signoff. Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;LCMXO2_640HC_impl1_map.ncd&quot; Lattice Place and Route Report for Design &quot;LCMXO2_640HC_impl1_map.ncd&quot;
Wed Aug 16 20:59:37 2023 Sat Aug 19 21:55:01 2023
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B> <A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.12.1.454. PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
Preference file: LCMXO2_640HC_impl1.prf. Preference file: LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1. Placement level-cost: 5-1.
Routing Iterations: 6 Routing Iterations: 6
@ -66,45 +66,44 @@ Ignore Preference Error(s): True
63+4(JTAG)/79 85% bonded 63+4(JTAG)/79 85% bonded
IOLOGIC 25/80 31% used IOLOGIC 25/80 31% used
SLICE 117/320 36% used SLICE 113/320 35% used
EFB 1/1 100% used EFB 1/1 100% used
Number of Signals: 380 Number of Signals: 374
Number of Connections: 1008 Number of Connections: 978
Pin Constraint Summary: Pin Constraint Summary:
63 out of 63 pins locked (100% locked). 63 out of 63 pins locked (100% locked).
The following 3 signals are selected to use the primary clock routing resources: The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 46) RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 19) PHI2_c (driver: PHI2, clk load #: 21)
nCRAS_c (driver: nCRAS, clk load #: 10) nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal &quot;RCLK_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;RCLK&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal &quot;RCLK_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;RCLK&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;PHI2_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI2&quot; is located at &quot;8&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal &quot;PHI2_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI2&quot; is located at &quot;8&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources: The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset. No signal is selected as Global Set/Reset.
Starting Placer Phase 0. Starting Placer Phase 0.
.............. ............
Finished Placer Phase 0. REAL time: 0 secs Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1. Starting Placer Phase 1.
................... ....................
Placer score = 55012. Placer score = 53481.
Finished Placer Phase 1. REAL time: 4 secs Finished Placer Phase 1. REAL time: 5 secs
Starting Placer Phase 2. Starting Placer Phase 2.
. .
Placer score = 54994 Placer score = 53406
Finished Placer Phase 2. REAL time: 4 secs Finished Placer Phase 2. REAL time: 5 secs
@ -117,14 +116,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%) DCC : 0 out of 8 (0%)
Global Clocks: Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 46 PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 47
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 19 PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 21
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL6B)&quot;, clk load = 10 PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL6B)&quot;, clk load = 10
SECONDARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL3C)&quot;, clk load = 8, ce load = 0, sr load = 0 SECONDARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL3C)&quot;, clk load = 8, ce load = 0, sr load = 0
SECONDARY &quot;un1_wb_clk32_i&quot; from F0 on comp &quot;SLICE_103&quot; on site &quot;R6C8B&quot;, clk load = 0, ce load = 10, sr load = 0
PRIMARY : 3 out of 8 (37%) PRIMARY : 3 out of 8 (37%)
SECONDARY: 2 out of 8 (25%) SECONDARY: 1 out of 8 (12%)
@ -145,21 +143,18 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - | | 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+ +----------+----------------+------------+-----------+
Total placer CPU time: 3 secs Total placer CPU time: 5 secs
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1008 unrouted. 0 connections routed; 978 unrouted.
Starting router resource preassignment Starting router resource preassignment
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Completed router resource preassignment. Real time: 8 secs
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 5 secs Start NBR router at 21:55:09 08/19/23
Start NBR router at 20:59:43 08/16/23
***************************************************************** *****************************************************************
Info: NBR allows conflicts(one node used by more than one signal) Info: NBR allows conflicts(one node used by more than one signal)
@ -174,54 +169,41 @@ Note: NBR uses a different method to calculate timing slacks. The
your design. your design.
***************************************************************** *****************************************************************
Start NBR special constraint process at 20:59:43 08/16/23 Start NBR special constraint process at 21:55:09 08/19/23
Start NBR section for initial routing at 20:59:43 08/16/23 Start NBR section for initial routing at 21:55:10 08/19/23
Level 1, iteration 1 Level 1, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 7.085ns/0.000ns; real time: 9 secs
Level 2, iteration 1 Level 2, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 7.138ns/0.000ns; real time: 9 secs
Level 3, iteration 1 Level 3, iteration 1
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score; 0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 7.276ns/0.000ns; real time: 9 secs
Level 4, iteration 1 Level 4, iteration 1
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Info: Initial congestion level at 75% usage is 0 Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%) Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:59:43 08/16/23 Start NBR section for normal routing at 21:55:10 08/19/23
Level 1, iteration 1
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs
Level 4, iteration 1 Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 2 Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23 Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
Level 4, iteration 0
Start NBR section for re-routing at 21:55:10 08/19/23
Level 4, iteration 1 Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;hold &gt;: 0.083ns/0.000ns; real time: 6 secs Estimated worst slack/total negative slack&lt;setup&gt;: 6.966ns/0.000ns; real time: 9 secs
Level 4, iteration 0
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.902ns/0.000ns; real time: 6 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.902ns/0.000ns; real time: 6 secs
Start NBR section for re-routing at 20:59:44 08/16/23 Start NBR section for post-routing at 21:55:10 08/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 4.922ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 20:59:44 08/16/23
End NBR router with 0 unrouted connection End NBR router with 0 unrouted connection
@ -229,20 +211,17 @@ NBR Summary
----------- -----------
Number of unrouted connections : 0 (0.00%) Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%) Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 4.922ns Estimated worst slack&lt;setup&gt; : 6.966ns
Timing score&lt;setup&gt; : 0 Timing score&lt;setup&gt; : 0
----------- -----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Total CPU time 9 secs
Signal=wb_clk loads=1 clock_loads=1 Total REAL time: 9 secs
Total CPU time 6 secs
Total REAL time: 7 secs
Completely routed. Completely routed.
End of route. 1008 routed (100.00%); 0 unrouted. End of route. 978 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0 Hold time timing score: 0, hold timing errors: 0
@ -256,14 +235,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 4.922 PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 6.966
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000 PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.088 PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.304
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000 PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0 PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs Total CPU time to completion: 9 secs
Total REAL time to completion: 7 secs Total REAL time to completion: 10 secs
par done! par done!

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<html>
<head>
<title>syntmp/LCMXO2_640HC_impl1_premap_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frame src="syntmp/LCMXO2_640HC_impl1_premap_toc.htm" name="tocFrame" />
<frame src="syntmp/LCMXO2_640HC_impl1_premap_srr.htm" name="srrFrame"/>
</frameset>
</html>

126
CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_scck.rpt
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@ -1,63 +1,63 @@
Copyright (C) 1994-2021 Synopsys, Inc. Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited. Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R) Tool: Synplify Pro (R)
Build: R-2021.03L-SP1 Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2 OS: Windows 6.2
Hostname: ZANEPC Hostname: ZANEMACWIN11
Implementation : impl1 Implementation : impl1
# Written on Wed Aug 16 20:59:30 2023 # Written on Sat Aug 19 21:54:50 2023
##### FILES SYNTAX CHECKED ############################################## ##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc" Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
#Run constraint checker to find more issues with constraints. #Run constraint checker to find more issues with constraints.
######################################################################### #########################################################################
No issues found in constraint syntax. No issues found in constraint syntax.
Clock Summary Clock Summary
************* *************
Start Requested Requested Clock Clock Clock Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load Level Clock Frequency Period Type Group Load
---------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65 0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18 0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14 0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8 0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - System 100.0 MHz 10.000 system system_clkgroup 0
======================================================================================== ========================================================================================
Clock Load Summary Clock Load Summary
****************** ******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example Clock Load Pin Seq Example Seq Example Comb Example
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
RCLK 65 RCLK(port) CASr2.C - - RCLK 65 RCLK(port) CASr2.C - -
PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv) PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv) nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv) nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
System 0 - - - - System 0 - - - -
========================================================================================= =========================================================================================

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_summary.html
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@ -24,9 +24,9 @@
</TR> </TR>
<TR> <TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD> <TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD> <TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR> </TR>
<TR> <TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
@ -62,15 +62,15 @@
</TR> </TR>
<TR> <TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/16 20:59:46</SPAN></TD> <TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/20 05:55:58</SPAN></TD>
</TR> </TR>
<TR> <TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD> <TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
</TR> </TR>
<TR> <TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD> <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD> <TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD>
</TR> </TR>
</small></TABLE> </small></TABLE>
<BR> <BR>

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.html
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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
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# #
# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R. # Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
# #
# Period Constraints # Period Constraints
FREQUENCY PORT "PHI2" 2.9 MHz; FREQUENCY PORT "PHI2" 2.9 MHz;
FREQUENCY PORT "nCCAS" 2.9 MHz; FREQUENCY PORT "nCCAS" 2.9 MHz;
FREQUENCY PORT "nCRAS" 2.9 MHz; FREQUENCY PORT "nCRAS" 2.9 MHz;
FREQUENCY PORT "RCLK" 62.5 MHz; FREQUENCY PORT "RCLK" 62.5 MHz;
# Output Constraints # Output Constraints
# Input Constraints # Input Constraints
# Point-to-point Delay Constraints # Point-to-point Delay Constraints
# Block Path Constraints # Block Path Constraints
BLOCK ASYNCPATHS; BLOCK ASYNCPATHS;
# End of generated Logical Preferences. # End of generated Logical Preferences.

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CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.tcl
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@ -1,66 +1,66 @@
#-- Lattice Semiconductor Corporation Ltd. #-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file #-- Synplify OEM project file
#device options #device options
set_option -technology MACHXO2 set_option -technology MACHXO2
set_option -part LCMXO2_640HC set_option -part LCMXO2_640HC
set_option -package TG100C set_option -package TG100C
set_option -speed_grade -4 set_option -speed_grade -4
#compilation/mapping options #compilation/mapping options
set_option -symbolic_fsm_compiler true set_option -symbolic_fsm_compiler true
set_option -resource_sharing true set_option -resource_sharing true
#use verilog 2001 standard option #use verilog 2001 standard option
set_option -vlog_std v2001 set_option -vlog_std v2001
#map options #map options
set_option -frequency 100 set_option -frequency 100
set_option -maxfan 1000 set_option -maxfan 1000
set_option -auto_constrain_io 0 set_option -auto_constrain_io 0
set_option -disable_io_insertion false set_option -disable_io_insertion false
set_option -retiming false; set_option -pipe true set_option -retiming false; set_option -pipe true
set_option -force_gsr false set_option -force_gsr false
set_option -compiler_compatible 0 set_option -compiler_compatible 0
set_option -dup false set_option -dup false
add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc} add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
set_option -default_enum_encoding default set_option -default_enum_encoding default
#simulation options #simulation options
#timing analysis options #timing analysis options
#automatic place and route (vendor) options #automatic place and route (vendor) options
set_option -write_apr_constraint 1 set_option -write_apr_constraint 1
#synplifyPro options #synplifyPro options
set_option -fix_gated_and_generated_clocks 1 set_option -fix_gated_and_generated_clocks 1
set_option -update_models_cp 0 set_option -update_models_cp 0
set_option -resolve_multiple_driver 0 set_option -resolve_multiple_driver 0
set_option -seqshift_no_replicate 0 set_option -seqshift_no_replicate 0
#-- add_file options #-- add_file options
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC} set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v} add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v} add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
#-- top module name #-- top module name
set_option -top_module RAM2GS set_option -top_module RAM2GS
#-- set result format/file last #-- set result format/file last
project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi} project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
#-- error message log file #-- error message log file
project -log_file {LCMXO2_640HC_impl1.srf} project -log_file {LCMXO2_640HC_impl1.srf}
#-- set any command lines input by customer #-- set any command lines input by customer
#-- run Synplify with 'arrange HDL file' #-- run Synplify with 'arrange HDL file'
project -run project -run -clean

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<HTML>
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
Report: 53.254MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
Report: 102.312MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.226ns
The internal maximum frequency of the following component is 102.312 MHz
Logical Details: Cell type Pin name Component name
Destination: EFB WBCLKI ufmefb/EFBInst_0
Delay: 9.774ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 6.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from RCLK_c +)
Destination: FF Data in nRCS_0io (to RCLK_c +)
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
Physical Path Details:
Data path SLICE_16 to nRCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
--------
9.577 (30.6% logic, 69.4% route), 6 logic levels.
Report: 102.312MHz is the maximum frequency for this preference.
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Aug 19 21:54:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
Design file: lcmxo2_640hc_impl1_map.ncd
Preference file: lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
158 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
844 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.12">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>MachXO2</Family>
<Name>LCMXO2-640HC</Name>
<IDCode>0x012b9043</IDCode>
<Package>All</Package>
<PON>LCMXO2-640HC</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.jed</File>
<FileTime>08/19/23 07:23:26</FileTime>
<JedecChecksum>0xC8BF</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>152</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>FLASH</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
<TCKDelay>1</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
</CableOptions>
</ispXCF>

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Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
// Design: RAM2GS
// Package: TQFP100
// ncd File: lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Sat Aug 19 21:55:13 2023
// M: Minimum Performance Grade
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 6, 5, 4):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.553 4 -0.117 M
CROW[1] nCRAS F 2.019 4 0.001 M
Din[0] PHI2 F 4.715 4 3.636 4
Din[0] nCCAS F 0.790 4 0.535 4
Din[1] PHI2 F 5.021 4 3.516 4
Din[1] nCCAS F 1.086 4 0.264 4
Din[2] PHI2 F 3.385 4 3.516 4
Din[2] nCCAS F 0.282 4 0.948 4
Din[3] PHI2 F 4.644 4 3.516 4
Din[3] nCCAS F 1.278 4 0.095 4
Din[4] PHI2 F 4.335 4 3.516 4
Din[4] nCCAS F 2.446 4 -0.199 M
Din[5] PHI2 F 3.662 4 3.516 4
Din[5] nCCAS F 0.907 4 0.402 4
Din[6] PHI2 F 4.869 4 3.636 4
Din[6] nCCAS F 1.378 4 0.023 M
Din[7] PHI2 F 4.138 4 3.636 4
Din[7] nCCAS F 2.072 4 -0.120 M
MAin[0] PHI2 F 5.613 4 0.006 M
MAin[0] nCRAS F 0.244 4 1.146 4
MAin[1] PHI2 F 3.409 4 0.354 6
MAin[1] nCRAS F 0.244 4 1.146 4
MAin[2] PHI2 F 5.391 4 0.132 M
MAin[2] nCRAS F 0.250 4 1.141 4
MAin[3] PHI2 F 4.627 4 0.087 M
MAin[3] nCRAS F 0.507 4 0.910 4
MAin[4] PHI2 F 5.665 4 -0.133 M
MAin[4] nCRAS F 0.675 4 0.777 4
MAin[5] PHI2 F 5.569 4 0.129 M
MAin[5] nCRAS F 0.050 4 1.238 4
MAin[6] PHI2 F 5.717 4 -0.141 M
MAin[6] nCRAS F 0.242 4 1.146 4
MAin[7] PHI2 F 5.943 4 -0.173 M
MAin[7] nCRAS F 0.170 4 1.228 4
MAin[8] nCRAS F 0.759 4 0.696 4
MAin[9] nCRAS F 0.516 4 0.891 4
PHI2 RCLK R -0.312 M 3.167 4
nCCAS RCLK R 2.600 4 -0.176 M
nCCAS nCRAS F 3.106 4 -0.235 M
nCRAS RCLK R 1.803 4 -0.055 M
nFWE PHI2 F 4.680 4 0.261 M
nFWE nCRAS F 2.234 4 1.143 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 9.922 4 2.878 M
LED nCRAS F 10.555 4 3.057 M
RA[0] RCLK R 11.638 4 3.406 M
RA[0] nCRAS F 11.771 4 3.430 M
RA[10] RCLK R 8.141 4 2.620 M
RA[11] PHI2 R 8.610 4 2.756 M
RA[1] RCLK R 11.674 4 3.407 M
RA[1] nCRAS F 10.635 4 3.155 M
RA[2] RCLK R 12.933 4 3.729 M
RA[2] nCRAS F 11.858 4 3.449 M
RA[3] RCLK R 12.587 4 3.664 M
RA[3] nCRAS F 11.255 4 3.298 M
RA[4] RCLK R 11.721 4 3.433 M
RA[4] nCRAS F 11.153 4 3.297 M
RA[5] RCLK R 12.544 4 3.620 M
RA[5] nCRAS F 11.480 4 3.360 M
RA[6] RCLK R 12.984 4 3.775 M
RA[6] nCRAS F 11.528 4 3.407 M
RA[7] RCLK R 12.553 4 3.625 M
RA[7] nCRAS F 11.610 4 3.368 M
RA[8] RCLK R 11.836 4 3.453 M
RA[8] nCRAS F 10.797 4 3.201 M
RA[9] RCLK R 11.182 4 3.271 M
RA[9] nCRAS F 11.135 4 3.279 M
RBA[0] nCRAS F 8.439 4 2.703 M
RBA[1] nCRAS F 8.439 4 2.703 M
RCKE RCLK R 10.083 4 3.081 M
RDQMH RCLK R 11.381 4 3.325 M
RDQML RCLK R 10.735 4 3.173 M
RD[0] nCCAS F 8.223 4 2.594 M
RD[1] nCCAS F 8.223 4 2.594 M
RD[2] nCCAS F 8.223 4 2.594 M
RD[3] nCCAS F 8.223 4 2.594 M
RD[4] nCCAS F 8.223 4 2.594 M
RD[5] nCCAS F 8.223 4 2.594 M
RD[6] nCCAS F 8.223 4 2.594 M
RD[7] nCCAS F 8.223 4 2.594 M
nRCAS RCLK R 8.141 4 2.620 M
nRCS RCLK R 8.141 4 2.620 M
nRRAS RCLK R 8.141 4 2.620 M
nRWE RCLK R 8.121 4 2.627 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M

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[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 47.556 MHz (2.900 MHz);
Fmax_1 = 150.150 MHz (2.900 MHz);
Fmax_2 = 150.150 MHz (2.900 MHz);
Fmax_3 = 102.312 MHz (62.500 MHz);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = - (-);
Fmax_1 = - (-);
Fmax_2 = - (-);
Fmax_3 = - (-);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;

162
CPLD/LCMXO2-640HC/impl1/run_options.txt
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@ -1,81 +1,81 @@
#-- Synopsys, Inc. #-- Synopsys, Inc.
#-- Version R-2021.03L-SP1 #-- Version R-2021.03L-SP1
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt #-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
#-- Written on Wed Aug 16 20:59:29 2023 #-- Written on Sat Aug 19 21:54:48 2023
#project files #project files
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc" add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v" add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v" add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
#implementation: "impl1" #implementation: "impl1"
impl -add impl1 -type fpga impl -add impl1 -type fpga
# #
#implementation attributes #implementation attributes
set_option -vlog_std v2001 set_option -vlog_std v2001
set_option -project_relative_includes 1 set_option -project_relative_includes 1
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC} set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
#device options #device options
set_option -technology MACHXO2 set_option -technology MACHXO2
set_option -part LCMXO2_640HC set_option -part LCMXO2_640HC
set_option -package TG100C set_option -package TG100C
set_option -speed_grade -4 set_option -speed_grade -4
set_option -part_companion "" set_option -part_companion ""
#compilation/mapping options #compilation/mapping options
set_option -top_module "RAM2GS" set_option -top_module "RAM2GS"
# hdl_compiler_options # hdl_compiler_options
set_option -distributed_compile 0 set_option -distributed_compile 0
set_option -hdl_strict_syntax 0 set_option -hdl_strict_syntax 0
# mapper_without_write_options # mapper_without_write_options
set_option -frequency 100 set_option -frequency 100
set_option -srs_instrumentation 1 set_option -srs_instrumentation 1
# mapper_options # mapper_options
set_option -write_verilog 0 set_option -write_verilog 0
set_option -write_structural_verilog 0 set_option -write_structural_verilog 0
set_option -write_vhdl 0 set_option -write_vhdl 0
# Lattice XP # Lattice XP
set_option -maxfan 1000 set_option -maxfan 1000
set_option -disable_io_insertion 0 set_option -disable_io_insertion 0
set_option -retiming 0 set_option -retiming 0
set_option -pipe 1 set_option -pipe 1
set_option -forcegsr false set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1 set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1 set_option -rw_check_on_ram 1
set_option -update_models_cp 0 set_option -update_models_cp 0
set_option -syn_edif_array_rename 1 set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1 set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0 set_option -seqshift_no_replicate 0
# NFilter # NFilter
set_option -no_sequential_opt 0 set_option -no_sequential_opt 0
# sequential_optimization_options # sequential_optimization_options
set_option -symbolic_fsm_compiler 1 set_option -symbolic_fsm_compiler 1
# Compiler Options # Compiler Options
set_option -compiler_compatible 0 set_option -compiler_compatible 0
set_option -resource_sharing 1 set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1 set_option -multi_file_compilation_unit 1
# Compiler Options # Compiler Options
set_option -auto_infer_blackbox 0 set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options #automatic place and route (vendor) options
set_option -write_apr_constraint 1 set_option -write_apr_constraint 1
#set result format/file last #set result format/file last
project -result_file "./LCMXO2_640HC_impl1.edi" project -result_file "./LCMXO2_640HC_impl1.edi"
#set log file #set log file
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
impl -active "impl1" impl -active "impl1"

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CPLD/LCMXO2-640HC/impl1/scratchproject.prs
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@ -1,80 +1,80 @@
#-- Synopsys, Inc. #-- Synopsys, Inc.
#-- Version R-2021.03L-SP1 #-- Version R-2021.03L-SP1
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs #-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
#project files #project files
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc" add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v" add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v" add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
#implementation: "impl1" #implementation: "impl1"
impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga impl -add Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
# #
#implementation attributes #implementation attributes
set_option -vlog_std v2001 set_option -vlog_std v2001
set_option -project_relative_includes 1 set_option -project_relative_includes 1
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/} set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC} set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
#device options #device options
set_option -technology MACHXO2 set_option -technology MACHXO2
set_option -part LCMXO2_640HC set_option -part LCMXO2_640HC
set_option -package TG100C set_option -package TG100C
set_option -speed_grade -4 set_option -speed_grade -4
set_option -part_companion "" set_option -part_companion ""
#compilation/mapping options #compilation/mapping options
set_option -top_module "RAM2GS" set_option -top_module "RAM2GS"
# hdl_compiler_options # hdl_compiler_options
set_option -distributed_compile 0 set_option -distributed_compile 0
set_option -hdl_strict_syntax 0 set_option -hdl_strict_syntax 0
# mapper_without_write_options # mapper_without_write_options
set_option -frequency 100 set_option -frequency 100
set_option -srs_instrumentation 1 set_option -srs_instrumentation 1
# mapper_options # mapper_options
set_option -write_verilog 0 set_option -write_verilog 0
set_option -write_structural_verilog 0 set_option -write_structural_verilog 0
set_option -write_vhdl 0 set_option -write_vhdl 0
# Lattice XP # Lattice XP
set_option -maxfan 1000 set_option -maxfan 1000
set_option -disable_io_insertion 0 set_option -disable_io_insertion 0
set_option -retiming 0 set_option -retiming 0
set_option -pipe 1 set_option -pipe 1
set_option -forcegsr false set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1 set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1 set_option -rw_check_on_ram 1
set_option -update_models_cp 0 set_option -update_models_cp 0
set_option -syn_edif_array_rename 1 set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1 set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0 set_option -seqshift_no_replicate 0
# NFilter # NFilter
set_option -no_sequential_opt 0 set_option -no_sequential_opt 0
# sequential_optimization_options # sequential_optimization_options
set_option -symbolic_fsm_compiler 1 set_option -symbolic_fsm_compiler 1
# Compiler Options # Compiler Options
set_option -compiler_compatible 0 set_option -compiler_compatible 0
set_option -resource_sharing 1 set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1 set_option -multi_file_compilation_unit 1
# Compiler Options # Compiler Options
set_option -auto_infer_blackbox 0 set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options #automatic place and route (vendor) options
set_option -write_apr_constraint 1 set_option -write_apr_constraint 1
#set result format/file last #set result format/file last
project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi" project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
#set log file #set log file
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf" set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
impl -active "impl1" impl -active "impl1"

171
CPLD/LCMXO2-640HC/impl1/stdout.log
View File

@ -1,82 +1,89 @@
Running in Lattice mode Running in Lattice mode
Synplify Pro (R) Synplify Pro (R)
Version R-2021.03L-SP1 for win64 - Aug 10, 2021 Version R-2021.03L-SP1 for win64 - Aug 10, 2021
Copyright (c) 1988 - 2021 Synopsys, Inc. Copyright (c) 1988 - 2021 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys, This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction, of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. or distribution of this software is strictly prohibited.
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC Hostname: ZANEMACWIN11
Date: Wed Aug 16 20:59:29 2023 Date: Sat Aug 19 21:54:47 2023
Version: R-2021.03L-SP1 Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
ProductType: synplify_pro ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr" log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground Running: impl1 in foreground
Running proj_1|impl1 Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1 Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:59:29 2023 # Sat Aug 19 21:54:48 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1 Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:59:29 2023 # Sat Aug 19 21:54:48 2023
Running: compiler (Compile Input) on proj_1|impl1 Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:59:29 2023 # Sat Aug 19 21:54:48 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
compiler completed
# Wed Aug 16 20:59:30 2023 compiler completed
# Sat Aug 19 21:54:49 2023
Return Code: 0
Run Time:00h:00m:01s Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Wed Aug 16 20:59:30 2023 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
Up-To-Date: multi_srs_gen. No run necessary # Sat Aug 19 21:54:49 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1 multi_srs_gen completed
# Sat Aug 19 21:54:50 2023
Running: premap (Premap) on proj_1|impl1
# Wed Aug 16 20:59:30 2023 Return Code: 0
Run Time:00h:00m:01s
premap completed with warnings Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
# Wed Aug 16 20:59:32 2023 Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1
Return Code: 1
Run Time:00h:00m:02s Running: premap (Premap) on proj_1|impl1
Complete: Compile on proj_1|impl1 # Sat Aug 19 21:54:50 2023
Running Flow: map (Map) on proj_1|impl1 premap completed with warnings
# Wed Aug 16 20:59:32 2023 # Sat Aug 19 21:54:51 2023
License granted for 4 parallel jobs
Return Code: 1
Running: fpga_mapper (Map & Optimize) on proj_1|impl1 Run Time:00h:00m:01s
# Wed Aug 16 20:59:32 2023 Complete: Compile on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
Running Flow: map (Map) on proj_1|impl1
fpga_mapper completed with warnings # Sat Aug 19 21:54:51 2023
# Wed Aug 16 20:59:35 2023 License granted for 4 parallel jobs
Return Code: 1 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
Run Time:00h:00m:03s # Sat Aug 19 21:54:51 2023
Complete: Map on proj_1|impl1 Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1 fpga_mapper completed with warnings
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl" # Sat Aug 19 21:54:55 2023
exit status=0
exit status=0 Return Code: 1
Save changes for project: Run Time:00h:00m:04s
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj Complete: Map on proj_1|impl1
batch mode default:no Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

178
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.1
View File

@ -1,89 +1,89 @@
Running in Lattice mode Running in Lattice mode
Synplify Pro (R) Synplify Pro (R)
Version R-2021.03L-SP1 for win64 - Aug 10, 2021 Version R-2021.03L-SP1 for win64 - Aug 10, 2021
Copyright (c) 1988 - 2021 Synopsys, Inc. Copyright (c) 1988 - 2021 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys, This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction, of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. or distribution of this software is strictly prohibited.
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC Hostname: ZANEMACWIN11
Date: Wed Aug 16 20:57:40 2023 Date: Sat Aug 19 07:28:27 2023
Version: R-2021.03L-SP1 Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
ProductType: synplify_pro ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr" log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground Running: impl1 in foreground
Running proj_1|impl1 Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1 Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:57:40 2023 # Sat Aug 19 07:28:28 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1 Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:57:40 2023 # Sat Aug 19 07:28:28 2023
Running: compiler (Compile Input) on proj_1|impl1 Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:57:40 2023 # Sat Aug 19 07:28:28 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
compiler completed compiler completed
# Wed Aug 16 20:57:43 2023 # Sat Aug 19 07:28:29 2023
Return Code: 0 Return Code: 0
Run Time:00h:00m:03s Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
# Wed Aug 16 20:57:43 2023 # Sat Aug 19 07:28:29 2023
multi_srs_gen completed multi_srs_gen completed
# Wed Aug 16 20:57:43 2023 # Sat Aug 19 07:28:29 2023
Return Code: 0 Return Code: 0
Run Time:00h:00m:00s Run Time:00h:00m:00s
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Compile Process on proj_1|impl1 Complete: Compile Process on proj_1|impl1
Running: premap (Premap) on proj_1|impl1 Running: premap (Premap) on proj_1|impl1
# Wed Aug 16 20:57:43 2023 # Sat Aug 19 07:28:29 2023
premap completed with warnings premap completed with warnings
# Wed Aug 16 20:57:45 2023 # Sat Aug 19 07:28:31 2023
Return Code: 1 Return Code: 1
Run Time:00h:00m:02s Run Time:00h:00m:02s
Complete: Compile on proj_1|impl1 Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1 Running Flow: map (Map) on proj_1|impl1
# Wed Aug 16 20:57:45 2023 # Sat Aug 19 07:28:31 2023
License granted for 4 parallel jobs License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1 Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Wed Aug 16 20:57:45 2023 # Sat Aug 19 07:28:31 2023
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings fpga_mapper completed with warnings
# Wed Aug 16 20:57:49 2023 # Sat Aug 19 07:28:34 2023
Return Code: 1 Return Code: 1
Run Time:00h:00m:04s Run Time:00h:00m:03s
Complete: Map on proj_1|impl1 Complete: Map on proj_1|impl1
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1 Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl" TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0 exit status=0
exit status=0 exit status=0
Save changes for project: Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no batch mode default:no

148
CPLD/LCMXO2-640HC/impl1/stdout.log.bak.2
View File

@ -1,59 +1,89 @@
Running in Lattice mode Running in Lattice mode
Synplify Pro (R) Synplify Pro (R)
Version R-2021.03L-SP1 for win64 - Aug 10, 2021 Version R-2021.03L-SP1 for win64 - Aug 10, 2021
Copyright (c) 1988 - 2021 Synopsys, Inc. Copyright (c) 1988 - 2021 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys, This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction, of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. or distribution of this software is strictly prohibited.
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
Install: C:\lscc\diamond\3.12\synpbase Install: C:\lscc\diamond\3.12\synpbase
Hostname: ZANEPC Hostname: ZANEMACWIN11
Date: Wed Aug 16 20:52:48 2023 Date: Sat Aug 19 07:27:36 2023
Version: R-2021.03L-SP1 Version: R-2021.03L-SP1
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
ProductType: synplify_pro ProductType: synplify_pro
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr" log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
Running: impl1 in foreground Running: impl1 in foreground
Running proj_1|impl1 Running proj_1|impl1
Running Flow: compile (Compile) on proj_1|impl1 Running Flow: compile (Compile) on proj_1|impl1
# Wed Aug 16 20:52:48 2023 # Sat Aug 19 07:27:37 2023
Running Flow: compile_flow (Compile Process) on proj_1|impl1 Running Flow: compile_flow (Compile Process) on proj_1|impl1
# Wed Aug 16 20:52:48 2023 # Sat Aug 19 07:27:37 2023
Running: compiler (Compile Input) on proj_1|impl1 Running: compiler (Compile Input) on proj_1|impl1
# Wed Aug 16 20:52:48 2023 # Sat Aug 19 07:27:37 2023
compiler exited with errors Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
Job failed on: proj_1|impl1
compiler completed
Job: "compiler" terminated with error status: 2 # Sat Aug 19 07:27:38 2023
See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
# Wed Aug 16 20:52:49 2023 Return Code: 0
Run Time:00h:00m:01s
Return Code: 2
Run Time:00h:00m:01s Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
Complete: Compile Process on proj_1|impl1 # Sat Aug 19 07:27:38 2023
Complete: Compile on proj_1|impl1
Complete: Logic Synthesis on proj_1|impl1 multi_srs_gen completed
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf # Sat Aug 19 07:27:38 2023
Error: At line 65 while processing "LCMXO2_640HC_impl1_synplify.tcl"
2 Return Code: 0
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl" Run Time:00h:00m:00s
TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl" Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
exit status=9 Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
exit status=9 Complete: Compile Process on proj_1|impl1
Save changes for project:
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj Running: premap (Premap) on proj_1|impl1
batch mode default:no # Sat Aug 19 07:27:38 2023
premap completed with warnings
# Sat Aug 19 07:27:40 2023
Return Code: 1
Run Time:00h:00m:02s
Complete: Compile on proj_1|impl1
Running Flow: map (Map) on proj_1|impl1
# Sat Aug 19 07:27:40 2023
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
# Sat Aug 19 07:27:40 2023
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
fpga_mapper completed with warnings
# Sat Aug 19 07:27:43 2023
Return Code: 1
Run Time:00h:00m:03s
Complete: Map on proj_1|impl1
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
Complete: Logic Synthesis on proj_1|impl1
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
exit status=0
exit status=0
Save changes for project:
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
batch mode default:no

Some files were not shown because too many files have changed in this diff Show More