Macintosh-HW
/
68030tk
mirror of https://github.com/kr239/68030tk.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
68030tk/Logic/68030_tk.out

1828 lines
135 KiB
Plaintext
Raw Normal View History

Cleaned up a bit
2016-01-24 19:26:06 +00:00
dma improved
2017-12-30 00:39:22 +00:00
122 "number of signals after reading design file"
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21
70 RW 5 352 6 2 5 7 70 -1 2 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
78 SIZE_1_ 5 343 7 1 5 78 -1 3 0 21
69 SIZE_0_ 5 353 6 1 5 69 -1 3 0 21
68 A_0_ 5 347 6 1 5 68 -1 3 0 21
40 BERR 5 -1 4 1 0 40 -1 1 0 21
29 DTACK 5 -1 3 1 5 29 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21
82 BGACK_030 5 348 7 0 82 -1 3 0 21
34 VMA 5 351 3 0 34 -1 3 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 346 3 0 28 -1 2 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
313 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21
312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
309 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
302 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
340 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21
327 SM_AMIGA_1_ 3 -1 1 3 1 3 5 -1 -1 3 0 21
326 SM_AMIGA_4_ 3 -1 3 3 0 3 5 -1 -1 3 0 21
325 SM_AMIGA_6_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21
341 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21
303 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21
300 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21
339 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21
332 RST_DLY_0_ 3 -1 2 2 2 6 -1 -1 4 0 21
329 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 4 0 21
351 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
337 SM_AMIGA_5_ 3 -1 5 2 3 5 -1 -1 3 0 21
328 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
323 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
336 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
335 inst_DSACK1_INT 3 -1 3 2 3 7 -1 -1 2 0 21
334 RST_DLY_2_ 3 -1 6 2 2 6 -1 -1 2 0 21
333 RST_DLY_1_ 3 -1 6 2 2 6 -1 -1 2 1 21
330 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 2 0 21
324 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
315 inst_DTACK_DMA 3 -1 7 2 3 7 -1 -1 2 0 21
301 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
316 inst_CLK_OUT_PRE_D 3 -1 4 2 0 2 -1 -1 1 0 21
307 CLK_000_D_3_ 3 -1 6 2 1 5 -1 -1 1 0 21
306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21
350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
331 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
310 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
338 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
353 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
343 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
352 RN_RW 3 70 6 1 6 70 -1 2 0 21
346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
311 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
342 CIIN_0 3 -1 2 1 4 -1 -1 1 0 21
321 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21
320 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
319 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21
318 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
317 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
308 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21
293 un10_ciin_i 3 -1 4 1 2 -1 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
60 CLK_OSZI 9 -1 0 60 -1
Cleaned up and the preempting DSACK is unneccessary?!?
2016-08-25 20:30:49 +00:00
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
67 IPL_2_ 1 -1 -1 2 1 7 67 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
59 A_1_ 1 -1 -1 2 2 6 59 -1
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
dma improved
2017-12-30 00:39:22 +00:00
2 RESET 1 -1 -1 2 1 2 2 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
63 CLK_030 1 -1 -1 1 0 63 -1
dma improved
2017-12-30 00:39:22 +00:00
35 VPA 1 -1 -1 1 3 35 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 1 10 -1
121 "number of signals after reading design file"
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 6 1 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
79 RW_000 5 344 7 3 2 4 6 79 -1 4 0 21
68 A_0_ 5 347 6 2 1 2 68 -1 3 0 21
70 RW 5 351 6 2 1 7 70 -1 2 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 342 7 1 2 78 -1 3 0 21
69 SIZE_0_ 5 352 6 1 2 69 -1 3 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
29 DTACK 5 -1 3 1 0 29 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21
82 BGACK_030 5 346 7 0 82 -1 3 0 21
34 VMA 5 350 3 0 34 -1 3 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 345 3 0 28 -1 2 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
346 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
312 CLK_000_D_0_ 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 21
311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
308 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
302 inst_BGACK_030_INT_D 3 -1 7 4 2 5 6 7 -1 -1 1 0 21
296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
326 SM_AMIGA_1_ 3 -1 0 3 0 5 6 -1 -1 3 0 21
325 SM_AMIGA_4_ 3 -1 6 3 0 1 6 -1 -1 3 0 21
340 CLK_OUT_INTreg 3 -1 2 3 1 2 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
328 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21
350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
339 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
336 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
335 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
334 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
329 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21
323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
314 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
305 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21
349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
330 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
309 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
331 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
351 RN_RW 3 70 6 1 6 70 -1 2 0 21
345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
333 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
332 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
310 inst_AMIGA_DS 3 -1 6 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
320 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
318 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
316 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
315 inst_CLK_OUT_PRE_D 3 -1 4 1 2 -1 -1 1 0 21
313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
306 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
59 A_1_ 1 -1 -1 2 2 5 59 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
dma improved
2017-12-30 00:39:22 +00:00
2 RESET 1 -1 -1 2 1 2 2 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 2 63 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 1 35 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 1 10 -1
120 "number of signals after reading design file"
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
79 RW_000 5 344 7 3 2 4 6 79 -1 4 0 21
70 RW 5 351 6 2 2 7 70 -1 2 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 342 7 1 1 78 -1 3 0 21
69 SIZE_0_ 5 352 6 1 1 69 -1 3 0 21
68 A_0_ 5 345 6 1 1 68 -1 3 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
29 DTACK 5 -1 3 1 0 29 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
82 BGACK_030 5 349 7 0 82 -1 3 0 21
34 VMA 5 350 3 0 34 -1 3 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 348 3 0 28 -1 2 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
313 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21
312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21
309 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21
297 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
327 SM_AMIGA_1_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
326 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21
341 CLK_OUT_INTreg 3 -1 7 3 1 2 6 -1 -1 1 0 21
303 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21
300 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
302 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
329 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21
350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
340 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
337 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 3 0 21
328 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
324 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21
336 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
335 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21
330 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21
322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
315 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 2 0 21
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
316 inst_CLK_OUT_PRE_D 3 -1 6 2 2 7 -1 -1 1 0 21
314 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
306 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
331 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
310 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
339 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
338 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
332 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
dma improved
2017-12-30 00:39:22 +00:00
342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
351 RN_RW 3 70 6 1 6 70 -1 2 0 21
348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
334 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
333 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
311 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
301 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
293 N_266_0 3 -1 4 1 4 -1 -1 2 0 21
321 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
320 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
319 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
318 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
317 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
307 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
13 nEXP_SPACE 1 -1 -1 5 0 3 4 5 7 13 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
Clarified some thing Timing can be adjusted with constants
2016-08-18 22:22:24 +00:00
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 1 1 67 -1
63 CLK_030 1 -1 -1 1 2 63 -1
59 A_1_ 1 -1 -1 1 6 59 -1
35 VPA 1 -1 -1 1 5 35 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 3 10 -1
119 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
79 RW_000 5 346 7 3 0 4 6 79 -1 4 0 21
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
70 RW 5 350 6 2 5 7 70 -1 2 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21
69 SIZE_0_ 5 351 6 1 5 69 -1 3 0 21
68 A_0_ 5 342 6 1 5 68 -1 3 0 21
40 BERR 5 -1 4 1 1 40 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21
82 BGACK_030 5 348 7 0 82 -1 3 0 21
34 VMA 5 349 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 347 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
302 inst_BGACK_030_INT_D 3 -1 4 4 0 2 6 7 -1 -1 1 0 21
301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
295 cpu_est_3_ 3 -1 3 3 1 3 6 -1 -1 4 0 21
293 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21
338 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21
324 SM_AMIGA_4_ 3 -1 6 3 1 5 6 -1 -1 3 0 21
323 SM_AMIGA_6_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
296 cpu_est_0_ 3 -1 5 3 1 3 5 -1 -1 3 0 21
308 inst_RESET_OUT 3 -1 3 3 3 4 7 -1 -1 2 0 21
339 CLK_OUT_INTreg 3 -1 7 3 0 1 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21
294 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 1 1 21
337 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 5 0 21
349 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21
326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
314 inst_CLK_OUT_PRE_D 3 -1 2 2 0 7 -1 -1 1 0 21
313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 2 -1 -1 1 0 21
305 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21
345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
309 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
303 inst_AS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21
346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21
351 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
335 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21
310 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 2 1 2 -1 -1 2 0 21
319 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
318 CLK_000_D_2_ 3 -1 1 1 2 -1 -1 1 0 21
317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
307 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21
306 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 1 -1 -1 6 2 3 4 5 6 7 81 -1
13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 0 63 -1
59 A_1_ 1 -1 -1 1 0 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
29 DTACK 1 -1 -1 1 6 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
119 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
79 RW_000 5 346 7 3 0 4 6 79 -1 4 0 21
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
70 RW 5 350 6 2 5 7 70 -1 2 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21
69 SIZE_0_ 5 351 6 1 5 69 -1 3 0 21
68 A_0_ 5 342 6 1 5 68 -1 3 0 21
40 BERR 5 -1 4 1 1 40 -1 1 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21
82 BGACK_030 5 348 7 0 82 -1 3 0 21
34 VMA 5 349 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 347 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
302 inst_BGACK_030_INT_D 3 -1 4 4 0 2 6 7 -1 -1 1 0 21
301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
295 cpu_est_3_ 3 -1 3 3 1 3 6 -1 -1 4 0 21
293 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21
338 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21
324 SM_AMIGA_4_ 3 -1 6 3 1 5 6 -1 -1 3 0 21
323 SM_AMIGA_6_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
296 cpu_est_0_ 3 -1 5 3 1 3 5 -1 -1 3 0 21
308 inst_RESET_OUT 3 -1 3 3 3 4 7 -1 -1 2 0 21
339 CLK_OUT_INTreg 3 -1 7 3 0 1 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21
294 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 1 1 21
337 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 5 0 21
349 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21
326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
314 inst_CLK_OUT_PRE_D 3 -1 2 2 0 7 -1 -1 1 0 21
313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 2 -1 -1 1 0 21
305 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21
345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
309 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
303 inst_AS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21
346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21
351 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
335 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21
310 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 2 1 2 -1 -1 2 0 21
319 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
318 CLK_000_D_2_ 3 -1 1 1 2 -1 -1 1 0 21
317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
307 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21
306 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 1 -1 -1 6 2 3 4 5 6 7 81 -1
13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 0 63 -1
59 A_1_ 1 -1 -1 1 0 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
29 DTACK 1 -1 -1 1 6 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
120 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
79 RW_000 5 346 7 3 2 4 6 79 -1 4 0 21
70 RW 5 351 6 2 2 7 70 -1 2 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 342 7 1 1 78 -1 3 0 21
69 SIZE_0_ 5 352 6 1 1 69 -1 3 0 21
68 A_0_ 5 344 6 1 1 68 -1 3 0 21
40 BERR 5 -1 4 1 0 40 -1 1 0 21
29 DTACK 5 -1 3 1 0 29 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21
82 BGACK_030 5 349 7 0 82 -1 3 0 21
34 VMA 5 350 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 348 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
312 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21
311 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
324 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21
308 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
326 SM_AMIGA_1_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
325 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21
340 CLK_OUT_INTreg 3 -1 7 3 1 2 6 -1 -1 1 0 21
302 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
328 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21
350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
339 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
336 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 3 0 21
327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
323 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
314 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 3 0 21
293 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21
335 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
334 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21
329 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
315 inst_CLK_OUT_PRE_D 3 -1 6 2 2 7 -1 -1 1 0 21
313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
305 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
330 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
309 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
331 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
351 RN_RW 3 70 6 1 6 70 -1 2 0 21
348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
333 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
332 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
310 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
320 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
317 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
306 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 5 0 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 1 1 67 -1
63 CLK_030 1 -1 -1 1 2 63 -1
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
59 A_1_ 1 -1 -1 1 6 59 -1
dma improved
2017-12-30 00:39:22 +00:00
35 VPA 1 -1 -1 1 5 35 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 3 10 -1
116 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21
79 RW_000 5 343 7 3 1 4 6 79 -1 4 0 21
70 RW 5 -1 6 2 6 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21
68 A_0_ 5 -1 6 1 5 68 -1 2 0 21
40 BERR 5 -1 4 1 0 40 -1 1 0 21
29 DTACK 5 -1 3 1 3 29 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 342 1 0 8 -1 10 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
82 BGACK_030 5 345 7 0 82 -1 3 0 21
34 VMA 5 346 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
Working at 254Mhz in CDTV!
2016-08-24 21:34:13 +00:00
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 344 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
345 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
311 CLK_000_D_0_ 3 -1 2 6 0 2 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
324 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21
295 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
293 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
327 SM_AMIGA_0_ 3 -1 0 3 0 2 7 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 4 3 3 4 6 -1 -1 1 0 21
294 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21
331 RST_DLY_0_ 3 -1 0 2 0 6 -1 -1 4 0 21
328 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 4 0 21
346 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
339 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21
326 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21
325 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21
322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
321 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21
313 inst_DTACK_DMA 3 -1 5 2 3 5 -1 -1 3 0 21
296 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
335 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21
334 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21
333 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21
332 RST_DLY_1_ 3 -1 6 2 0 6 -1 -1 2 1 21
329 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 2 0 21
320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 6 2 2 6 -1 -1 2 0 21
340 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21
314 inst_CLK_OUT_PRE_D 3 -1 3 2 0 1 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 5 2 2 4 -1 -1 1 0 21
304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
330 CLK_030_PE_0_ 3 -1 1 1 1 -1 -1 9 0 21
308 CLK_030_PE_1_ 3 -1 1 1 1 -1 -1 6 0 21
338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
343 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
336 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21
344 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
309 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21
323 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21
319 CLK_000_D_4_ 3 -1 4 1 2 -1 -1 1 0 21
318 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
317 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
315 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 1 3 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 1 63 -1
59 A_1_ 1 -1 -1 1 2 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 2 10 -1
115 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21
70 RW 5 -1 6 2 6 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21
68 A_0_ 5 -1 6 1 2 68 -1 2 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 345 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 343 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21
296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
dma improved
2017-12-30 00:39:22 +00:00
326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
340 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21
330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21
324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21
320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
339 N_280 3 -1 4 1 4 -1 -1 2 0 21
309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21
318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 2 63 -1
59 A_1_ 1 -1 -1 1 5 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
29 DTACK 1 -1 -1 1 0 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
115 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21
70 RW 5 -1 6 2 6 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21
68 A_0_ 5 -1 6 1 2 68 -1 2 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 345 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 343 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21
295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
339 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21
330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21
324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21
320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21
318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 2 63 -1
59 A_1_ 1 -1 -1 1 5 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
29 DTACK 1 -1 -1 1 0 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
115 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21
70 RW 5 -1 6 2 6 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21
68 A_0_ 5 -1 6 1 2 68 -1 2 0 21
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 347 3 0 34 -1 3 0 21
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
28 BG_000 5 343 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21
295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
339 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21
330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
347 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21
324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21
320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21
318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 2 63 -1
59 A_1_ 1 -1 -1 1 5 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
29 DTACK 1 -1 -1 1 0 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
115 "number of signals after reading design file"
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21
70 RW 5 -1 6 2 6 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21
68 A_0_ 5 -1 6 1 2 68 -1 2 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 345 3 0 34 -1 3 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 343 3 0 28 -1 2 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21
296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
dma improved
2017-12-30 00:39:22 +00:00
326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
340 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21
330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21
327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21
324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21
320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21
331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21
328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
dma improved
2017-12-30 00:39:22 +00:00
341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
339 N_154 3 -1 4 1 4 -1 -1 2 0 21
309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21
318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
63 CLK_030 1 -1 -1 1 2 63 -1
59 A_1_ 1 -1 -1 1 5 59 -1
55 IPL_1_ 1 -1 -1 1 1 55 -1
35 VPA 1 -1 -1 1 0 35 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
29 DTACK 1 -1 -1 1 0 29 -1
Horray! No Sync of Pos and Neg edges needed anymore!
2016-08-18 22:42:01 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 6 10 -1
112 "number of signals after reading design file"
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
79 RW_000 5 341 7 3 1 4 6 79 -1 4 0 21
68 A_0_ 5 -1 6 2 0 5 68 -1 2 0 21
70 RW 5 -1 6 2 5 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21
Improved speed on amiga cycles
2016-10-06 19:37:29 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 340 1 0 6 -1 10 0 21
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 345 3 0 34 -1 3 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 343 3 0 28 -1 2 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
310 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
322 SM_AMIGA_6_ 3 -1 6 5 0 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 5 4 3 4 5 7 -1 -1 2 0 21
301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 7 0 21
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
336 SM_AMIGA_i_7_ 3 -1 6 3 2 6 7 -1 -1 3 1 21
325 SM_AMIGA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 6 0 21
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21
335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21
328 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21
326 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 4 0 21
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
333 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21
dma improved
2017-12-30 00:39:22 +00:00
319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
331 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21
330 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21
329 RST_DLY_1_ 3 -1 5 2 5 6 -1 -1 2 1 21
327 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21
320 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21
337 CLK_OUT_INTreg 3 -1 5 2 1 6 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 5 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 3 2 3 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
324 SM_AMIGA_1_ 3 -1 2 1 2 -1 -1 3 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
308 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21
321 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21
317 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21
316 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21
315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
314 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 5 2 3 4 6 7 13 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
59 A_1_ 1 -1 -1 2 0 3 59 -1
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 1 1 66 -1
35 VPA 1 -1 -1 1 6 35 -1
29 DTACK 1 -1 -1 1 1 29 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 3 10 -1
112 "number of signals after reading design file"
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
79 RW_000 5 342 7 3 1 4 6 79 -1 4 0 21
68 A_0_ 5 -1 6 2 0 5 68 -1 2 0 21
70 RW 5 -1 6 2 5 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 341 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 340 1 0 6 -1 10 0 21
82 BGACK_030 5 344 7 0 82 -1 3 0 21
34 VMA 5 345 3 0 34 -1 3 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 343 3 0 28 -1 2 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
310 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
322 SM_AMIGA_6_ 3 -1 6 5 0 2 5 6 7 -1 -1 3 0 21
307 inst_RESET_OUT 3 -1 5 4 3 4 5 7 -1 -1 2 0 21
301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 7 0 21
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
336 SM_AMIGA_i_7_ 3 -1 6 3 2 6 7 -1 -1 3 1 21
325 SM_AMIGA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
294 cpu_est_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 6 0 21
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21
335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21
328 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21
326 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 4 0 21
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
333 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21
323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
331 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21
330 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21
329 RST_DLY_1_ 3 -1 5 2 5 6 -1 -1 2 1 21
327 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21
318 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21
338 CLK_OUT_INTreg 3 -1 5 2 1 6 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 5 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 3 2 3 6 -1 -1 1 0 21
304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
341 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
324 SM_AMIGA_1_ 3 -1 2 1 2 -1 -1 3 0 21
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
337 N_242 3 -1 4 1 4 -1 -1 2 0 21
308 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21
321 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21
317 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21
316 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21
315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
314 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
60 CLK_OSZI 9 -1 0 60 -1
dma improved
2017-12-30 00:39:22 +00:00
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 5 2 3 4 6 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
59 A_1_ 1 -1 -1 2 0 3 59 -1
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
dma improved
2017-12-30 00:39:22 +00:00
66 IPL_0_ 1 -1 -1 1 1 66 -1
35 VPA 1 -1 -1 1 6 35 -1
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
29 DTACK 1 -1 -1 1 1 29 -1
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
20 BG_030 1 -1 -1 1 3 20 -1
dma improved
2017-12-30 00:39:22 +00:00
10 CLK_000 1 -1 -1 1 3 10 -1
108 "number of signals after reading design file"
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
dma improved
2017-12-30 00:39:22 +00:00
81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
79 RW_000 5 336 7 3 2 4 6 79 -1 4 0 21
68 A_0_ 5 -1 6 2 1 6 68 -1 2 0 21
70 RW 5 -1 6 2 2 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 6 69 -1 2 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
40 BERR 5 -1 4 1 0 40 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 340 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 339 1 0 6 -1 10 0 21
82 BGACK_030 5 338 7 0 82 -1 3 0 21
34 VMA 5 341 3 0 34 -1 3 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
dma improved
2017-12-30 00:39:22 +00:00
28 BG_000 5 337 3 0 28 -1 2 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
timing timing timnig ... when will it end?
2016-10-16 17:58:33 +00:00
80 DSACK1 0 7 0 80 -1 1 0 21
Cleaned up BRD-Files
2016-09-15 17:20:42 +00:00
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
309 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21
308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
321 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
324 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
322 SM_AMIGA_4_ 3 -1 6 3 0 2 6 -1 -1 3 0 21
293 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21
332 CLK_OUT_INTreg 3 -1 0 3 1 2 6 -1 -1 1 0 21
Updated some JEDs
2016-10-26 20:26:40 +00:00
299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
dma improved
2017-12-30 00:39:22 +00:00
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 6 0 21
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21
325 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
341 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
333 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
329 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21
323 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
328 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
327 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
326 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
317 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
311 inst_CLK_OUT_PRE_D 3 -1 4 2 0 2 -1 -1 1 0 21
310 inst_CLK_OUT_PRE_50 3 -1 7 2 4 7 -1 -1 1 0 21
304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
331 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
330 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
334 N_60 3 -1 4 1 4 -1 -1 2 0 21
307 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
320 inst_BGACK_030_INT_D 3 -1 4 1 5 -1 -1 1 0 21
316 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21
315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
314 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
313 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
312 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 5 1 5 -1 -1 1 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 1 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 1 3 -1 -1 1 0 21
Updated some JEDs
2016-10-26 20:26:40 +00:00
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
dma improved
2017-12-30 00:39:22 +00:00
13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1
Updated some JEDs
2016-10-26 20:26:40 +00:00
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
dma improved
2017-12-30 00:39:22 +00:00
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
59 A_1_ 1 -1 -1 2 0 2 59 -1
Updated some JEDs
2016-10-26 20:26:40 +00:00
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
Better timing & Resetfix
2016-11-30 22:10:23 +00:00
35 VPA 1 -1 -1 1 6 35 -1
29 DTACK 1 -1 -1 1 5 29 -1
20 BG_030 1 -1 -1 1 3 20 -1
DMA-Fix: Assume $E8-EF 16 bit wide!
2018-01-11 19:21:08 +00:00
10 CLK_000 1 -1 -1 1 3 10 -1
108 "number of signals after reading design file"
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
81 AS_030 5 -1 7 7 0 2 3 4 5 6 7 81 -1 1 0 21
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
79 RW_000 5 336 7 2 4 6 79 -1 4 0 21
68 A_0_ 5 -1 6 2 0 3 68 -1 2 0 21
70 RW 5 -1 6 2 0 7 70 -1 1 0 21
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21
69 SIZE_0_ 5 -1 6 1 0 69 -1 2 0 21
40 BERR 5 -1 4 1 2 40 -1 1 0 21
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21
7 IPL_030_0_ 5 340 1 0 7 -1 10 0 21
6 IPL_030_1_ 5 339 1 0 6 -1 10 0 21
82 BGACK_030 5 338 7 0 82 -1 3 0 21
34 VMA 5 341 3 0 34 -1 3 0 21
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
28 BG_000 5 337 3 0 28 -1 2 0 21
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
80 DSACK1 0 7 0 80 -1 1 0 21
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
309 CLK_000_D_0_ 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21
308 CLK_000_D_1_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21
321 SM_AMIGA_6_ 3 -1 1 5 0 1 2 3 7 -1 -1 3 0 21
293 cpu_est_0_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21
301 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21
296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
294 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
333 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21
324 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 5 3 3 4 5 -1 -1 1 0 21
295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21
303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 6 0 21
302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 6 0 21
331 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 5 0 21
341 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
323 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21
322 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
328 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
327 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
332 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21
311 inst_CLK_OUT_PRE_D 3 -1 7 2 0 6 -1 -1 1 0 21
305 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21
304 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21
340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
330 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
325 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 4 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 4 1 2 -1 -1 4 0 21
329 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21
337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
334 N_205 3 -1 4 1 4 -1 -1 2 0 21
326 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 2 0 21
317 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
307 inst_AMIGA_DS 3 -1 7 1 6 -1 -1 2 0 21
300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 4 1 3 -1 -1 2 0 21
320 inst_BGACK_030_INT_D 3 -1 4 1 5 -1 -1 1 0 21
316 CLK_000_D_4_ 3 -1 5 1 1 -1 -1 1 0 21
315 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
313 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
310 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21
306 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 5 1 3 4 5 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
59 A_1_ 1 -1 -1 1 4 59 -1
35 VPA 1 -1 -1 1 1 35 -1
29 DTACK 1 -1 -1 1 5 29 -1
20 BG_030 1 -1 -1 1 3 20 -1
10 CLK_000 1 -1 -1 1 5 10 -1