mirror of https://github.com/kr239/68030tk.git
Initial push
First VErsion after I decided to use version controll ;)
This commit is contained in:
commit
473a4a745b
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|
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## Windows detritus
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#############
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# Windows image file caches
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# Folder config file
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# Mac crap
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.DS_Store
|
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|
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|
#############
|
||||||
|
## Python
|
||||||
|
#############
|
||||||
|
|
||||||
|
*.py[co]
|
||||||
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|
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# Packages
|
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*.egg
|
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*.egg-info
|
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dist/
|
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build/
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eggs/
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parts/
|
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var/
|
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sdist/
|
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|
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.installed.cfg
|
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# Installer logs
|
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pip-log.txt
|
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|
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|
# Unit test / coverage reports
|
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|
.coverage
|
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.tox
|
||||||
|
|
||||||
|
#Translations
|
||||||
|
*.mo
|
||||||
|
|
||||||
|
#Mr Developer
|
||||||
|
.mr.developer.cfg
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,403 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
-- DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||||
|
|
||||||
|
constant IDLE : AMIGA_STATE := "00";
|
||||||
|
constant AS_SET : AMIGA_STATE := "01";
|
||||||
|
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||||
|
constant END_CYCLE : AMIGA_STATE := "11";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE;
|
||||||
|
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal ZorroII:STD_LOGIC:= '0';
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal E_INT: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
--signal AS_030_delay: STD_LOGIC:='1';
|
||||||
|
signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||||
|
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||||
|
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
cpu_clk: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
if(CLK_CNT="10") then
|
||||||
|
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process cpu_clk;
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= CLK_OUT_INT;
|
||||||
|
|
||||||
|
|
||||||
|
clk_delay: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process clk_delay;
|
||||||
|
|
||||||
|
--ZORROII (Amiga) space?
|
||||||
|
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||||
|
|
||||||
|
--BG_ACK is simple:
|
||||||
|
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif rising_edge(CLK_000) then
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
end process BGACK_030_gen;
|
||||||
|
BGACK_030 <= BGACK_030_INT;
|
||||||
|
|
||||||
|
--DTACK
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||||
|
'1';
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||||
|
else '1';
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
|
||||||
|
-- vma and e clock
|
||||||
|
e_clk: process (CLK_000)
|
||||||
|
begin
|
||||||
|
if rising_edge(CLK_000) then
|
||||||
|
-- next state.
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process e_clk;
|
||||||
|
|
||||||
|
vma_gen: process (CLK_000,AS_030) begin
|
||||||
|
if(AS_030='1') then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
VPA_SYNC <= '1';
|
||||||
|
elsif falling_edge(CLK_000) then
|
||||||
|
VPA_SYNC <= VPA;
|
||||||
|
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||||
|
VMA_INT <= '0'; -- low active !
|
||||||
|
end if;
|
||||||
|
if(cpu_est = E10) then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process vma_gen;
|
||||||
|
|
||||||
|
vma_delay: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
VMA_INT_D<=VMA_INT;
|
||||||
|
end if;
|
||||||
|
end process vma_delay;
|
||||||
|
|
||||||
|
E_INT <= cpu_est(3);
|
||||||
|
E <= E_INT;
|
||||||
|
VMA <= VMA_INT AND VMA_INT_D;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||||
|
-- ELSE '1';
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||||
|
ipl_amiga: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
end process ipl_amiga;
|
||||||
|
|
||||||
|
--BG
|
||||||
|
bg_amiga: process(CLK_030,BG_030)
|
||||||
|
begin
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(falling_edge(CLK_030)) then
|
||||||
|
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <='1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process bg_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--as uds/lds generation
|
||||||
|
UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
|
||||||
|
LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||||
|
|
||||||
|
as_amiga: process(AS_030, CLK_030)
|
||||||
|
begin
|
||||||
|
if(AS_030 = '1') then
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT<= '1';
|
||||||
|
LDS_000_INT<= '1';
|
||||||
|
elsif(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
|
||||||
|
if ( AS_030 = '0' AND -- obviously as must be low
|
||||||
|
CPU_SPACE = '0' AND -- expansion board not in action
|
||||||
|
SM_AMIGA = IDLE AND -- last cycle completed
|
||||||
|
AS_AMIGA_ENABLE = '1' --indicator ready
|
||||||
|
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||||
|
) then
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1') then --read: set udl/lds
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
elsif(RW='0' AND AS_000_INT_D='0')then --write: uds/lds have to wait for one 7m-clock later
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process as_amiga;
|
||||||
|
|
||||||
|
--helper signal for a delayed version of AS_000
|
||||||
|
as_pe_amiga: process(AS_030, CLK_000)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_000_INT_D <= '1';
|
||||||
|
elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
|
||||||
|
AS_000_INT_D <= AS_000_INT;
|
||||||
|
end if;
|
||||||
|
end process as_pe_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
--state machine for amiga-cycle
|
||||||
|
sm_amiga: process(RST, CLK_000)
|
||||||
|
begin
|
||||||
|
if(RST='0') then
|
||||||
|
SM_AMIGA <= IDLE;
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
elsif(falling_edge(CLK_000)) then
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE =>
|
||||||
|
if(AS_000_INT='0') then
|
||||||
|
SM_AMIGA <= AS_SET;
|
||||||
|
end if;
|
||||||
|
when AS_SET =>
|
||||||
|
if(VPA_SYNC = '1' AND DTACK_SYNC='0') then
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH => --here the data is written/read
|
||||||
|
SM_AMIGA <= END_CYCLE;
|
||||||
|
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
SM_AMIGA <= IDLE ;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process sm_amiga;
|
||||||
|
|
||||||
|
--positive edge deleyed statemachine
|
||||||
|
state_amiga_pe: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
SM_AMIGA_LAST <= SM_AMIGA;
|
||||||
|
end if;
|
||||||
|
end process state_amiga_pe;
|
||||||
|
|
||||||
|
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
--dsack generation
|
||||||
|
dtack_sync: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
DTACK_SYNC <= DTACK; --for the AMIGA state machine
|
||||||
|
DTACK_SYNC_D <= DTACK_SYNC;
|
||||||
|
DTACK_SYNC_DD <= DTACK_SYNC_D;
|
||||||
|
end if;
|
||||||
|
end process dtack_sync;
|
||||||
|
|
||||||
|
--dsack generation
|
||||||
|
dsack_CPU: process(AS_030,CLK_030)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_AMIGA_ENABLE <='0';
|
||||||
|
elsif(rising_edge(CLK_030)) then
|
||||||
|
-- this is a indicator, that we have been in idle state
|
||||||
|
-- this avoids that an "old" DTACK is used a second time in a new memory cycle
|
||||||
|
if(SM_AMIGA = IDLE) then
|
||||||
|
AS_AMIGA_ENABLE <= '1';
|
||||||
|
end if;
|
||||||
|
if(SM_AMIGA = END_CYCLE AND AS_AMIGA_ENABLE = '1') then
|
||||||
|
DSACK_INT<="01";
|
||||||
|
AS_AMIGA_ENABLE<='0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process dsack_CPU;
|
||||||
|
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
|
@ -0,0 +1,402 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
-- DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||||
|
|
||||||
|
constant IDLE : AMIGA_STATE := "00";
|
||||||
|
constant AS_SET : AMIGA_STATE := "01";
|
||||||
|
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||||
|
constant END_CYCLE : AMIGA_STATE := "11";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE;
|
||||||
|
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal ZorroII:STD_LOGIC:= '0';
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal E_INT: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
--signal AS_030_delay: STD_LOGIC:='1';
|
||||||
|
signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||||
|
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||||
|
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
cpu_clk: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
if(CLK_CNT="00") then
|
||||||
|
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process cpu_clk;
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= CLK_OUT_INT;
|
||||||
|
|
||||||
|
|
||||||
|
clk_delay: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process clk_delay;
|
||||||
|
|
||||||
|
--ZORROII (Amiga) space?
|
||||||
|
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||||
|
|
||||||
|
--BG_ACK is simple:
|
||||||
|
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif rising_edge(CLK_000) then
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
end process BGACK_030_gen;
|
||||||
|
BGACK_030 <= BGACK_030_INT;
|
||||||
|
|
||||||
|
--DTACK
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||||
|
'1';
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||||
|
else '1';
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
|
||||||
|
-- vma and e clock
|
||||||
|
e_clk: process (CLK_000)
|
||||||
|
begin
|
||||||
|
if rising_edge(CLK_000) then
|
||||||
|
-- next state.
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process e_clk;
|
||||||
|
|
||||||
|
vma_gen: process (CLK_000,AS_030) begin
|
||||||
|
if(AS_030='1') then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
VPA_SYNC <= '1';
|
||||||
|
elsif falling_edge(CLK_000) then
|
||||||
|
VPA_SYNC <= VPA;
|
||||||
|
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||||
|
VMA_INT <= '0'; -- low active !
|
||||||
|
end if;
|
||||||
|
if(cpu_est = E10) then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process vma_gen;
|
||||||
|
|
||||||
|
vma_delay: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
VMA_INT_D<=VMA_INT;
|
||||||
|
end if;
|
||||||
|
end process vma_delay;
|
||||||
|
|
||||||
|
E_INT <= cpu_est(3);
|
||||||
|
E <= E_INT;
|
||||||
|
VMA <= VMA_INT AND VMA_INT_D;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||||
|
-- ELSE '1';
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||||
|
ipl_amiga: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
end process ipl_amiga;
|
||||||
|
|
||||||
|
--BG
|
||||||
|
bg_amiga: process(CLK_030,BG_030)
|
||||||
|
begin
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(falling_edge(CLK_030)) then
|
||||||
|
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <='1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process bg_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--as uds/lds generation
|
||||||
|
UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
|
||||||
|
LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||||
|
|
||||||
|
as_amiga: process(AS_030, CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
|
||||||
|
if ( AS_030 = '0' AND -- obviously as must be low
|
||||||
|
CPU_SPACE = '0' AND -- expansion board not in action
|
||||||
|
SM_AMIGA = IDLE AND -- last cycle completed
|
||||||
|
AS_AMIGA_ENABLE = '1' --indicator ready
|
||||||
|
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||||
|
) then
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1') then --read: set udl/lds
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
elsif(RW='0' AND SM_AMIGA = AS_SET)then --write: uds/lds have to wait for one 7m-clock later
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
elsif(AS_030 = '1' and (SM_AMIGA = END_CYCLE OR SM_AMIGA = IDLE)) then
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT<= '1';
|
||||||
|
LDS_000_INT<= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process as_amiga;
|
||||||
|
|
||||||
|
--helper signal for a delayed version of AS_000
|
||||||
|
as_pe_amiga: process(AS_030, CLK_000)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_000_INT_D <= '1';
|
||||||
|
elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
|
||||||
|
AS_000_INT_D <= AS_000_INT;
|
||||||
|
end if;
|
||||||
|
end process as_pe_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
--state machine for amiga-cycle
|
||||||
|
sm_amiga: process(RST, CLK_000)
|
||||||
|
begin
|
||||||
|
if(RST='0') then
|
||||||
|
SM_AMIGA <= IDLE;
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
elsif(falling_edge(CLK_000)) then
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE =>
|
||||||
|
if(AS_000_INT='0') then
|
||||||
|
SM_AMIGA <= AS_SET;
|
||||||
|
end if;
|
||||||
|
when AS_SET =>
|
||||||
|
if(VPA_SYNC = '1' AND DTACK_SYNC='0') then
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH => --here the data is written/read
|
||||||
|
SM_AMIGA <= END_CYCLE;
|
||||||
|
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
SM_AMIGA <= IDLE ;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process sm_amiga;
|
||||||
|
|
||||||
|
--positive edge deleyed statemachine
|
||||||
|
state_amiga_pe: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
SM_AMIGA_LAST <= SM_AMIGA;
|
||||||
|
end if;
|
||||||
|
end process state_amiga_pe;
|
||||||
|
|
||||||
|
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
--dsack generation
|
||||||
|
dtack_sync: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
DTACK_SYNC <= DTACK; --for the AMIGA state machine
|
||||||
|
DTACK_SYNC_D <= DTACK_SYNC;
|
||||||
|
DTACK_SYNC_DD <= DTACK_SYNC_D;
|
||||||
|
end if;
|
||||||
|
end process dtack_sync;
|
||||||
|
|
||||||
|
--dsack generation
|
||||||
|
dsack_CPU: process(AS_030,CLK_030)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_AMIGA_ENABLE <='0';
|
||||||
|
elsif(rising_edge(CLK_030)) then
|
||||||
|
-- this is a indicator, that we have been in idle state
|
||||||
|
-- this avoids that an "old" DTACK is used a second time in a new memory cycle
|
||||||
|
if(SM_AMIGA = IDLE) then
|
||||||
|
AS_AMIGA_ENABLE <= '1';
|
||||||
|
end if;
|
||||||
|
if(SM_AMIGA = DATA_FETCH AND CLK_000='1' AND AS_AMIGA_ENABLE = '1') then
|
||||||
|
DSACK_INT<="01";
|
||||||
|
AS_AMIGA_ENABLE<='0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process dsack_CPU;
|
||||||
|
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
|
@ -0,0 +1,403 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
-- DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
constant IDLE_P : AMIGA_STATE := "000";
|
||||||
|
constant IDLE_N : AMIGA_STATE := "001";
|
||||||
|
constant AS_SET_P : AMIGA_STATE := "010";
|
||||||
|
constant AS_SET_N : AMIGA_STATE := "011";
|
||||||
|
constant DATA_FETCH_P: AMIGA_STATE := "100";
|
||||||
|
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||||
|
constant END_CYCLE_P : AMIGA_STATE := "110";
|
||||||
|
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE := IDLE_P;
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal E_INT: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||||
|
signal CLK_OUT_PRE: STD_LOGIC:='1';
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_030_D: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
signal RISING_CLK_AMIGA: STD_LOGIC :='0';
|
||||||
|
signal FALLING_CLK_AMIGA: STD_LOGIC :='0';
|
||||||
|
--signal RISING_CLK_030: STD_LOGIC :='0';
|
||||||
|
--signal FALLING_CLK_030: STD_LOGIC :='0';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--the clocks
|
||||||
|
clk: process(RST, CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
if(CLK_CNT=CLK_REF) then
|
||||||
|
CLK_OUT_PRE <= not CLK_OUT_PRE;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
-- the external clock to the processor is generated here
|
||||||
|
CLK_OUT_INT <= CLK_OUT_PRE;
|
||||||
|
--delayed Clocks for edge detection
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
|
||||||
|
--RISING_CLK_030 <= CLK_OUT_PRE and not CLK_030;
|
||||||
|
--FALLING_CLK_030 <= not CLK_OUT_PRE and CLK_030;
|
||||||
|
--edge detection stuff
|
||||||
|
RISING_CLK_AMIGA <= not CLK_000_D and CLK_000;
|
||||||
|
FALLING_CLK_AMIGA <= CLK_000_D and not CLK_000;
|
||||||
|
-- e clock
|
||||||
|
if(CLK_000_D='0' and CLK_000='1')then
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
E_INT <= cpu_est(3);
|
||||||
|
VPA_SYNC <= VPA;
|
||||||
|
end if;
|
||||||
|
end process clk;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--the state process
|
||||||
|
state_machine: process(RST, CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(RST = '0' ) then
|
||||||
|
SM_AMIGA <= IDLE_P;
|
||||||
|
AS_000_INT <='1';
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
CLK_REF <= "11";
|
||||||
|
VMA_INT <= '1';
|
||||||
|
VMA_INT_D <= '1';
|
||||||
|
FPU_CS_INT <= '1';
|
||||||
|
BG_000 <= '1';
|
||||||
|
BGACK_030_INT <= '1';
|
||||||
|
DSACK_INT <= "11";
|
||||||
|
DTACK_DMA <= '1';
|
||||||
|
IPL_030 <= "111";
|
||||||
|
elsif(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif (BGACK_000='1' AND RISING_CLK_AMIGA='1') then -- BGACK_000 is high here!
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--bus grant only in idle state
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(CLK_030 ='0') then
|
||||||
|
if( BG_030= '0' AND (SM_AMIGA = IDLE_N or SM_AMIGA = IDLE_P)
|
||||||
|
and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
|
||||||
|
FPU_CS_INT <= '0';
|
||||||
|
else
|
||||||
|
FPU_CS_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--interrupt buffering to avoid ghost interrupts
|
||||||
|
if(RISING_CLK_AMIGA='1')then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--vma generation
|
||||||
|
if (CLK_000='0') then
|
||||||
|
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||||
|
VMA_INT <= '0'; -- low active !
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--Amiga statemachine
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE_P => --68000:S0 wait for a falling edge
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
VMA_INT <= '1';
|
||||||
|
if(CLK_000='0')then
|
||||||
|
SM_AMIGA<=IDLE_N;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when IDLE_N => --68000:S1 wait for rising edge and look for as
|
||||||
|
if(CLK_000='1')then
|
||||||
|
if( CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||||
|
AS_030 = '0' AND -- obviously as must be low
|
||||||
|
CPU_SPACE = '0'
|
||||||
|
)then
|
||||||
|
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1') then --read: set udl/lds
|
||||||
|
if(AS_030 = '0' AND A(0)='0') then
|
||||||
|
UDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if(AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||||
|
LDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when AS_SET_P => --68000:S2 nothing happens here just wait for negative clock
|
||||||
|
if(CLK_000='0')then
|
||||||
|
SM_AMIGA<=AS_SET_N;
|
||||||
|
end if;
|
||||||
|
when AS_SET_N => --68000:S3 sample dtack and set uds/lds on write and high clock
|
||||||
|
if(CLK_000='1')then
|
||||||
|
if (RW='0') then --write: set udl/lds
|
||||||
|
if(AS_030 = '0' AND A(0)='0') then
|
||||||
|
UDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if(AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||||
|
LDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if(VPA_SYNC = '1' AND DTACK='0') then
|
||||||
|
SM_AMIGA <= DATA_FETCH_P ;
|
||||||
|
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||||
|
SM_AMIGA <= DATA_FETCH_P ;
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH_P=> --68000:S4 nothing happens here just wait for negative clock
|
||||||
|
if(CLK_000='0')then
|
||||||
|
SM_AMIGA<=DATA_FETCH_N;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||||
|
if(CLK_000='1')then
|
||||||
|
SM_AMIGA<=END_CYCLE_P;
|
||||||
|
DSACK_INT<="01";
|
||||||
|
end if;
|
||||||
|
when END_CYCLE_P => --68000:S6: propagate dsack to 68030
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if(CLK_000='0')then
|
||||||
|
SM_AMIGA<=END_CYCLE_N;
|
||||||
|
end if;
|
||||||
|
when END_CYCLE_N =>--68000:S7: deassert signals and go to IDLE on high clock
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if(CLK_000='1')then
|
||||||
|
SM_AMIGA<=IDLE_P;
|
||||||
|
end if;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
--delay for hold time of CIAs
|
||||||
|
VMA_INT_D <= VMA_INT;
|
||||||
|
|
||||||
|
|
||||||
|
--dma stuff
|
||||||
|
--DTACK for DMA cycles
|
||||||
|
if(AS_000_INT ='0' AND DSACK(1) ='0') then
|
||||||
|
DTACK_DMA <= '0';
|
||||||
|
else
|
||||||
|
DTACK_DMA <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process state_machine;
|
||||||
|
|
||||||
|
--output clock assignment
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= CLK_OUT_INT;
|
||||||
|
AVEC_EXP <= SM_AMIGA(0);
|
||||||
|
|
||||||
|
--dtack for dma
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
|
||||||
|
--fpu
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'Z' WHEN not(A(31 downto 24) = x"00") ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
--e and VMA
|
||||||
|
E <= E_INT;
|
||||||
|
VMA <= VMA_INT AND VMA_INT_D;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--as and uds/lds
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
|
||||||
|
--dsack
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
|
@ -0,0 +1,425 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||||
|
|
||||||
|
constant IDLE : AMIGA_STATE := "00";
|
||||||
|
constant AS_SET : AMIGA_STATE := "01";
|
||||||
|
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||||
|
constant END_CYCLE : AMIGA_STATE := "11";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE;
|
||||||
|
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal ZorroII:STD_LOGIC:= '0';
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal E_INT: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
--signal AS_030_delay: STD_LOGIC:='1';
|
||||||
|
signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||||
|
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||||
|
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
cpu_clk: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
if(CLK_CNT="11") then
|
||||||
|
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process cpu_clk;
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= CLK_OUT_INT;
|
||||||
|
|
||||||
|
|
||||||
|
clk_delay: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process clk_delay;
|
||||||
|
|
||||||
|
--ZORROII (Amiga) space?
|
||||||
|
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||||
|
|
||||||
|
--BG_ACK is simple:
|
||||||
|
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif rising_edge(CLK_000) then
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
end process BGACK_030_gen;
|
||||||
|
BGACK_030 <= BGACK_030_INT;
|
||||||
|
|
||||||
|
--DTACK
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||||
|
'1';
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||||
|
else '1';
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
|
||||||
|
-- vma and e clock
|
||||||
|
e_clk: process (CLK_000)
|
||||||
|
begin
|
||||||
|
if falling_edge(CLK_000) then
|
||||||
|
-- next state.
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process e_clk;
|
||||||
|
|
||||||
|
vma_gen: process (CLK_000,AS_030) begin
|
||||||
|
--if(AS_030='1') then
|
||||||
|
-- VMA_INT <= '1';
|
||||||
|
-- VPA_SYNC <= '1';
|
||||||
|
--els
|
||||||
|
if falling_edge(CLK_000) then
|
||||||
|
VPA_SYNC <= VPA;
|
||||||
|
if(cpu_est = E3 AND VPA = '0' AND SM_AMIGA = AS_SET) then
|
||||||
|
VMA_INT <= '0'; -- low active !
|
||||||
|
end if;
|
||||||
|
if(cpu_est = E10) then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process vma_gen;
|
||||||
|
|
||||||
|
vma_delay: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
VMA_INT_D<=VMA_INT;
|
||||||
|
end if;
|
||||||
|
end process vma_delay;
|
||||||
|
|
||||||
|
E_INT <= cpu_est(3);
|
||||||
|
E <= E_INT;
|
||||||
|
VMA <= VMA_INT;-- AND VMA_INT_D;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||||
|
-- ELSE '1';
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||||
|
ipl_amiga: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
end process ipl_amiga;
|
||||||
|
|
||||||
|
--BG
|
||||||
|
bg_amiga: process(CLK_030,BG_030)
|
||||||
|
begin
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(falling_edge(CLK_030)) then
|
||||||
|
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <='1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process bg_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--as uds/lds generation
|
||||||
|
UDS_LOGIC <= '0' WHEN DS_030 = '0' AND A(0)='0' ELSE '1';
|
||||||
|
LDS_LOGIC <= '0' WHEN DS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||||
|
|
||||||
|
as_amiga: process(AS_030, CLK_030)
|
||||||
|
begin
|
||||||
|
--if(AS_030 = '1') then --Read-modify-write cycles do not deassert AS in between but DS does!
|
||||||
|
-- AS_000_INT <= '1';
|
||||||
|
--els
|
||||||
|
if(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE =>
|
||||||
|
if( AS_030 = '0' -- obviously as must be low
|
||||||
|
AND CPU_SPACE = '0' -- expansion board not in action
|
||||||
|
AND SM_AMIGA = IDLE -- last cycle completed
|
||||||
|
AND AS_AMIGA_ENABLE = '1' --indicator ready
|
||||||
|
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||||
|
) then
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1')then -- read: immediate datastrobe!
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when AS_SET =>
|
||||||
|
if( CLK_000 = '1'
|
||||||
|
AND DS_030 = '0'
|
||||||
|
AND RW='0'
|
||||||
|
) then
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH => --here the data is written/read
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process as_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
--helper signal for a delayed version of AS_000
|
||||||
|
as_pe_amiga: process(AS_030, CLK_000)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_000_INT_D <= '1';
|
||||||
|
elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
|
||||||
|
AS_000_INT_D <= AS_000_INT;
|
||||||
|
end if;
|
||||||
|
end process as_pe_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
--state machine for amiga-cycle
|
||||||
|
sm_amiga: process(RST, CLK_000)
|
||||||
|
begin
|
||||||
|
if(RST='0') then
|
||||||
|
SM_AMIGA <= IDLE;
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
elsif(falling_edge(CLK_000)) then
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE =>
|
||||||
|
if(AS_000_INT='0') then
|
||||||
|
SM_AMIGA <= AS_SET;
|
||||||
|
end if;
|
||||||
|
when AS_SET =>
|
||||||
|
if(VPA = '1' AND DTACK='0') then
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
elsif(E8=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle ends on e10 but we have two clocks after this state!
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH => --here the data is written/read
|
||||||
|
SM_AMIGA <= END_CYCLE;
|
||||||
|
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||||
|
DTACK_INT<= '1';
|
||||||
|
SM_AMIGA <= IDLE ;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process sm_amiga;
|
||||||
|
|
||||||
|
--positive edge deleyed statemachine
|
||||||
|
state_amiga_pe: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
|
||||||
|
SM_AMIGA_LAST <= SM_AMIGA;
|
||||||
|
end if;
|
||||||
|
end process state_amiga_pe;
|
||||||
|
|
||||||
|
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
--dsack generation
|
||||||
|
dtack_sync: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
DTACK_SYNC <= DTACK; --for the AMIGA state machine
|
||||||
|
DTACK_SYNC_D <= DTACK_SYNC;
|
||||||
|
DTACK_SYNC_DD <= DTACK_SYNC_D;
|
||||||
|
end if;
|
||||||
|
end process dtack_sync;
|
||||||
|
|
||||||
|
--dsack generation
|
||||||
|
dsack_CPU: process(DS_030,CLK_030)
|
||||||
|
begin
|
||||||
|
if(AS_030 ='1') then --Read-modify-write cycles do not deassert AS in between but DS does!
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_AMIGA_ENABLE <= '0';
|
||||||
|
elsif(falling_edge(CLK_030)) then
|
||||||
|
if(SM_AMIGA = IDLE)then
|
||||||
|
--this is a indicator, that we have been in idle state
|
||||||
|
--this avoids that an "old" DTACK is used a second time in a new memory cycle
|
||||||
|
AS_AMIGA_ENABLE <= '1';
|
||||||
|
elsif(SM_AMIGA_LAST = DATA_FETCH AND AS_AMIGA_ENABLE = '1') then
|
||||||
|
DSACK_INT<="01";
|
||||||
|
AS_AMIGA_ENABLE <= '0';
|
||||||
|
elsif(SM_AMIGA=END_CYCLE) then --Read-modify-write cycles do not deassert AS in between!
|
||||||
|
DSACK_INT<="11";
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process dsack_CPU;
|
||||||
|
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
|
@ -0,0 +1,387 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
-- DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||||
|
|
||||||
|
constant IDLE : AMIGA_STATE := "00";
|
||||||
|
constant AS_SET : AMIGA_STATE := "01";
|
||||||
|
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||||
|
constant END_CYCLE : AMIGA_STATE := "11";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE;
|
||||||
|
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal ZorroII:STD_LOGIC:= '0';
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal E_INT: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||||
|
--signal AS_030_delay: STD_LOGIC:='1';
|
||||||
|
signal SM_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||||
|
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||||
|
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
cpu_clk: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
if(CLK_CNT="01") then
|
||||||
|
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process cpu_clk;
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= CLK_OUT_INT;
|
||||||
|
|
||||||
|
|
||||||
|
clk_delay: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process clk_delay;
|
||||||
|
|
||||||
|
--ZORROII (Amiga) space?
|
||||||
|
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||||
|
|
||||||
|
--BG_ACK is simple:
|
||||||
|
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif rising_edge(CLK_000) then
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
end process BGACK_030_gen;
|
||||||
|
BGACK_030 <= BGACK_030_INT;
|
||||||
|
|
||||||
|
--DTACK
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||||
|
'1';
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||||
|
else '1';
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
|
||||||
|
-- vma and e clock
|
||||||
|
e_clk: process (CLK_000)
|
||||||
|
begin
|
||||||
|
if rising_edge(CLK_000) then
|
||||||
|
-- next state.
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process e_clk;
|
||||||
|
|
||||||
|
vma_gen: process (CLK_000,AS_030) begin
|
||||||
|
if(AS_030='1') then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
VPA_SYNC <= '1';
|
||||||
|
elsif falling_edge(CLK_000) then
|
||||||
|
VPA_SYNC <= VPA;
|
||||||
|
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||||
|
VMA_INT <= '0'; -- low active !
|
||||||
|
end if;
|
||||||
|
if(cpu_est = E10) then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process vma_gen;
|
||||||
|
|
||||||
|
vma_delay: process(CLK_030)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_030)) then
|
||||||
|
VMA_INT_D<=VMA_INT;
|
||||||
|
end if;
|
||||||
|
end process vma_delay;
|
||||||
|
|
||||||
|
E_INT <= cpu_est(3);
|
||||||
|
E <= E_INT;
|
||||||
|
VMA <= VMA_INT AND VMA_INT_D;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||||
|
-- ELSE '1';
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||||
|
ipl_amiga: process(CLK_000)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_000)) then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
end process ipl_amiga;
|
||||||
|
|
||||||
|
--BG
|
||||||
|
bg_amiga: process(CLK_030,BG_030)
|
||||||
|
begin
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(falling_edge(CLK_030)) then
|
||||||
|
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <='1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process bg_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--as uds/lds generation
|
||||||
|
UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
|
||||||
|
LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||||
|
|
||||||
|
|
||||||
|
--state machine for amiga-cycle
|
||||||
|
sm_amiga: process(RST, CLK_030)
|
||||||
|
begin
|
||||||
|
if(RST='0') then
|
||||||
|
SM_AMIGA <= IDLE;
|
||||||
|
DTACK_INT <= '1';
|
||||||
|
DSACK_INT <="11";
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
AS_000_INT <='1';
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
elsif(rising_edge(CLK_030)) then
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE =>
|
||||||
|
if(CLK_000 ='0') then
|
||||||
|
SM_AMIGA_ENABLE<='1';
|
||||||
|
end if;
|
||||||
|
if ( AS_030 = '0' -- obviously as must be low
|
||||||
|
AND CPU_SPACE = '0' -- expansion board not in action
|
||||||
|
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||||
|
AND SM_AMIGA_ENABLE = '1'
|
||||||
|
) then
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1') then --read: set udl/lds
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
end if;
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
SM_AMIGA <= AS_SET;
|
||||||
|
else
|
||||||
|
DSACK_INT<="11";
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
AS_000_INT <='1';
|
||||||
|
end if;
|
||||||
|
when AS_SET =>
|
||||||
|
if(CLK_000 ='0') then
|
||||||
|
SM_AMIGA_ENABLE<='1';
|
||||||
|
end if;
|
||||||
|
if ( CLK_000 = '1' and SM_AMIGA_ENABLE='1' ) then
|
||||||
|
UDS_000_INT <= UDS_LOGIC;
|
||||||
|
LDS_000_INT <= LDS_LOGIC;
|
||||||
|
if(VPA_SYNC = '1' AND DTACK='0') then
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||||
|
DTACK_INT<= '0';
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
SM_AMIGA <= DATA_FETCH ;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH => --here the data is written/read
|
||||||
|
DSACK_INT<="01";
|
||||||
|
if(CLK_000_D ='0') then
|
||||||
|
SM_AMIGA_ENABLE<='1';
|
||||||
|
end if;
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
AS_000_INT <='1';
|
||||||
|
end if;
|
||||||
|
if( CLK_000 = '1' AND SM_AMIGA_ENABLE = '1')then
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
SM_AMIGA <= END_CYCLE;
|
||||||
|
end if;
|
||||||
|
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||||
|
if(CLK_000 ='0') then
|
||||||
|
SM_AMIGA_ENABLE<='1';
|
||||||
|
end if;
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
AS_000_INT <='1';
|
||||||
|
end if;
|
||||||
|
if ( CLK_000 = '1' and SM_AMIGA_ENABLE <='1' ) then
|
||||||
|
SM_AMIGA_ENABLE <='0';
|
||||||
|
SM_AMIGA <= IDLE ;
|
||||||
|
end if;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process sm_amiga;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
|
@ -0,0 +1,3 @@
|
||||||
|
|
||||||
|
|
||||||
|
MODULE BUS68030
|
|
@ -0,0 +1,494 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.std_logic_arith.all;
|
||||||
|
use ieee.std_logic_unsigned.all;
|
||||||
|
|
||||||
|
entity BUS68030 is
|
||||||
|
|
||||||
|
port(
|
||||||
|
AS_030: inout std_logic ;
|
||||||
|
AS_000: inout std_logic ;
|
||||||
|
DS_030: inout std_logic ;
|
||||||
|
UDS_000: inout std_logic;
|
||||||
|
LDS_000: inout std_logic;
|
||||||
|
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
A: inout std_logic_vector ( 31 downto 0 );
|
||||||
|
CPU_SPACE: in std_logic ;
|
||||||
|
BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||||
|
BG_030: in std_logic ;
|
||||||
|
BG_000: out std_logic ;
|
||||||
|
BGACK_030: out std_logic ;
|
||||||
|
BGACK_000: in std_logic ;
|
||||||
|
CLK_030: in std_logic ;
|
||||||
|
CLK_000: in std_logic ;
|
||||||
|
CLK_OSZI: in std_logic ;
|
||||||
|
CLK_DIV_OUT: out std_logic ;
|
||||||
|
CLK_EXP: out std_logic ;
|
||||||
|
FPU_CS: out std_logic ;
|
||||||
|
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||||
|
IPL: in std_logic_vector ( 2 downto 0 );
|
||||||
|
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||||
|
DTACK: inout std_logic ;
|
||||||
|
AVEC: out std_logic ;
|
||||||
|
AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||||
|
E: out std_logic ;
|
||||||
|
VPA: in std_logic ;
|
||||||
|
VMA: out std_logic ;
|
||||||
|
RST: in std_logic ;
|
||||||
|
RESET: out std_logic ;
|
||||||
|
RW: in std_logic ;
|
||||||
|
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||||
|
FC: in std_logic_vector ( 1 downto 0 );
|
||||||
|
AMIGA_BUS_ENABLE: out std_logic ;
|
||||||
|
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||||
|
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||||
|
CIIN: out std_logic
|
||||||
|
);
|
||||||
|
end BUS68030;
|
||||||
|
|
||||||
|
architecture Behavioral of BUS68030 is
|
||||||
|
|
||||||
|
|
||||||
|
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||||
|
|
||||||
|
constant E1 : ESTATE := "0110";
|
||||||
|
constant E2 : ESTATE := "0111";
|
||||||
|
constant E3 : ESTATE := "0100";
|
||||||
|
constant E4 : ESTATE := "0101";
|
||||||
|
constant E5 : ESTATE := "0010";
|
||||||
|
constant E6 : ESTATE := "0011";
|
||||||
|
constant E7 : ESTATE := "1010";
|
||||||
|
constant E8 : ESTATE := "1011";
|
||||||
|
constant E9 : ESTATE := "1100";
|
||||||
|
constant E10 : ESTATE := "1111";
|
||||||
|
-- Illegal states
|
||||||
|
constant E20 : ESTATE := "0000";
|
||||||
|
constant E4a : ESTATE := "0001";
|
||||||
|
constant E21 : ESTATE := "1000";
|
||||||
|
constant E22 : ESTATE := "1001";
|
||||||
|
constant E23 : ESTATE := "1101";
|
||||||
|
constant E24 : ESTATE := "1110";
|
||||||
|
|
||||||
|
signal cpu_est : ESTATE := E20;
|
||||||
|
signal cpu_est_d : ESTATE := E20;
|
||||||
|
|
||||||
|
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
constant IDLE_P : AMIGA_STATE := "000";
|
||||||
|
constant IDLE_N : AMIGA_STATE := "001";
|
||||||
|
constant AS_SET_P : AMIGA_STATE := "010";
|
||||||
|
constant AS_SET_N : AMIGA_STATE := "011";
|
||||||
|
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||||
|
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||||
|
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||||
|
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||||
|
|
||||||
|
signal SM_AMIGA : AMIGA_STATE := IDLE_P;
|
||||||
|
signal SM_AMIGA_D : AMIGA_STATE := IDLE_P;
|
||||||
|
|
||||||
|
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||||
|
signal AS_000_INT:STD_LOGIC:= '1';
|
||||||
|
signal AS_000_START:STD_LOGIC:= '1';
|
||||||
|
signal AS_030_000_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||||
|
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||||
|
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||||
|
signal VPA_D: STD_LOGIC:='1';
|
||||||
|
signal VPA_SYNC: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT: STD_LOGIC:='1';
|
||||||
|
signal VMA_INT_D: STD_LOGIC:='1';
|
||||||
|
signal UDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal LDS_000_INT: STD_LOGIC:='1';
|
||||||
|
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||||
|
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||||
|
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||||
|
signal CLK_000_CNT: STD_LOGIC_VECTOR ( 3 downto 0 ) := "0000";
|
||||||
|
signal CLK_OUT_PRE: STD_LOGIC:='1';
|
||||||
|
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||||
|
signal CLK_030_D: STD_LOGIC:='1';
|
||||||
|
signal CLK_000_D: STD_LOGIC := '1';
|
||||||
|
signal CLK_000_DD: STD_LOGIC := '1';
|
||||||
|
signal RISING_CLK_AMIGA: STD_LOGIC :='0';
|
||||||
|
signal FALLING_CLK_AMIGA: STD_LOGIC :='0';
|
||||||
|
--signal RISING_CLK_030: STD_LOGIC :='0';
|
||||||
|
--signal FALLING_CLK_030: STD_LOGIC :='0';
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--the clocks
|
||||||
|
clk: process(CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(rising_edge(CLK_OSZI)) then
|
||||||
|
--reset buffer
|
||||||
|
RESET <= RST;
|
||||||
|
|
||||||
|
--clk generation : up to now just half the clock
|
||||||
|
if(CLK_CNT="01") then
|
||||||
|
CLK_OUT_PRE <= not CLK_OUT_PRE;
|
||||||
|
CLK_CNT <= "00";
|
||||||
|
else
|
||||||
|
CLK_CNT <= CLK_CNT+1;
|
||||||
|
end if;
|
||||||
|
-- the external clock to the processor is generated here
|
||||||
|
CLK_OUT_INT <= CLK_OUT_PRE; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||||
|
--delayed Clocks for edge detection
|
||||||
|
CLK_000_D <= CLK_000;
|
||||||
|
CLK_000_DD <= CLK_000_D;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--RISING_CLK_030 <= CLK_OUT_PRE and not CLK_030;
|
||||||
|
--FALLING_CLK_030 <= not CLK_OUT_PRE and CLK_030;
|
||||||
|
--edge detection stuff
|
||||||
|
RISING_CLK_AMIGA <= not CLK_000_D and CLK_000;
|
||||||
|
FALLING_CLK_AMIGA <= CLK_000_D and not CLK_000;
|
||||||
|
|
||||||
|
--cycle counter for Amiga-Bus-Timing
|
||||||
|
|
||||||
|
|
||||||
|
if( CLK_000_D /= CLK_000)then --not equal
|
||||||
|
CLK_000_CNT <= "0001";
|
||||||
|
else
|
||||||
|
CLK_000_CNT <= CLK_000_CNT+1; --4bit counter
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- e-clock
|
||||||
|
if(CLK_000_DD = '0' and CLK_000_D = '1') then
|
||||||
|
case (cpu_est) is
|
||||||
|
when E1 => cpu_est <= E2 ;
|
||||||
|
when E2 => cpu_est <= E3 ;
|
||||||
|
when E3 => cpu_est <= E4;
|
||||||
|
when E4 => cpu_est <= E5 ;
|
||||||
|
when E5 => cpu_est <= E6 ;
|
||||||
|
when E6 => cpu_est <= E7 ;
|
||||||
|
when E7 => cpu_est <= E8 ;
|
||||||
|
when E8 => cpu_est <= E9 ;
|
||||||
|
when E9 => cpu_est <= E10;
|
||||||
|
when E10 => cpu_est <= E1 ;
|
||||||
|
-- Illegal states
|
||||||
|
when E4a => cpu_est <= E5 ;
|
||||||
|
when E20 => cpu_est <= E10;
|
||||||
|
when E21 => cpu_est <= E10;
|
||||||
|
when E22 => cpu_est <= E9 ;
|
||||||
|
when E23 => cpu_est <= E9 ;
|
||||||
|
when E24 => cpu_est <= E10;
|
||||||
|
when others =>
|
||||||
|
null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
cpu_est_d <= cpu_est;
|
||||||
|
VPA_D <= VPA;
|
||||||
|
end if;
|
||||||
|
end process clk;
|
||||||
|
|
||||||
|
--eclk: process(CLK_000)
|
||||||
|
--begin
|
||||||
|
-- if(rising_edge(CLK_000)) then
|
||||||
|
-- -- e clock
|
||||||
|
-- case (cpu_est) is
|
||||||
|
-- when E1 => cpu_est <= E2 ;
|
||||||
|
-- when E2 => cpu_est <= E3 ;
|
||||||
|
-- when E3 => cpu_est <= E4;
|
||||||
|
-- when E4 => cpu_est <= E5 ;
|
||||||
|
-- when E5 => cpu_est <= E6 ;
|
||||||
|
-- when E6 => cpu_est <= E7 ;
|
||||||
|
-- when E7 => cpu_est <= E8 ;
|
||||||
|
-- when E8 => cpu_est <= E9 ;
|
||||||
|
-- when E9 => cpu_est <= E10;
|
||||||
|
-- when E10 => cpu_est <= E1 ;
|
||||||
|
-- -- Illegal states
|
||||||
|
-- when E4a => cpu_est <= E5 ;
|
||||||
|
-- when E20 => cpu_est <= E10;
|
||||||
|
-- when E21 => cpu_est <= E10;
|
||||||
|
-- when E22 => cpu_est <= E9 ;
|
||||||
|
-- when E23 => cpu_est <= E9 ;
|
||||||
|
-- when E24 => cpu_est <= E10;
|
||||||
|
-- when others =>
|
||||||
|
-- null;
|
||||||
|
-- end case;
|
||||||
|
-- end if;
|
||||||
|
--end process eclk;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--the state process
|
||||||
|
state_machine: process(RST, CLK_OSZI)
|
||||||
|
begin
|
||||||
|
if(RST = '0' ) then
|
||||||
|
SM_AMIGA <= IDLE_P;
|
||||||
|
AS_000_INT <='1';
|
||||||
|
AS_000_START<= '0';
|
||||||
|
AS_030_000_SYNC <='1';
|
||||||
|
UDS_000_INT <='1';
|
||||||
|
LDS_000_INT <='1';
|
||||||
|
CLK_REF <= "10";
|
||||||
|
VMA_INT <= '1';
|
||||||
|
VMA_INT_D <= '1';
|
||||||
|
FPU_CS_INT <= '1';
|
||||||
|
BG_000 <= '1';
|
||||||
|
BGACK_030_INT <= '1';
|
||||||
|
DSACK_INT <= "11";
|
||||||
|
DTACK_DMA <= '1';
|
||||||
|
DTACK_SYNC <= '1';
|
||||||
|
VPA_SYNC <= '1';
|
||||||
|
IPL_030 <= "111";
|
||||||
|
elsif(rising_edge(CLK_OSZI)) then
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||||
|
if(BGACK_000='0') then
|
||||||
|
BGACK_030_INT <= '0';
|
||||||
|
elsif (BGACK_000='1' AND RISING_CLK_AMIGA='1') then -- BGACK_000 is high here!
|
||||||
|
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--bus grant only in idle state
|
||||||
|
if(BG_030= '1')then
|
||||||
|
BG_000 <= '1';
|
||||||
|
elsif(CLK_030 ='0') then
|
||||||
|
if( BG_030= '0' AND (SM_AMIGA = IDLE_N or SM_AMIGA = IDLE_P)
|
||||||
|
and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||||
|
BG_000 <= '0';
|
||||||
|
else
|
||||||
|
BG_000 <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--CO-Processor Chip select
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--interrupt buffering to avoid ghost interrupts
|
||||||
|
if(RISING_CLK_AMIGA='1')then
|
||||||
|
IPL_030<=IPL;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- as030-sampling and FPU-Select
|
||||||
|
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
AS_030_000_SYNC <= '1';
|
||||||
|
FPU_CS_INT <= '1';
|
||||||
|
elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||||
|
AS_030 = '0') then
|
||||||
|
|
||||||
|
if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
|
||||||
|
FPU_CS_INT <= '0';
|
||||||
|
AS_030_000_SYNC <= '1';
|
||||||
|
else
|
||||||
|
AS_030_000_SYNC <= CPU_SPACE;
|
||||||
|
FPU_CS_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- "async" reset
|
||||||
|
if(AS_030 ='1') then
|
||||||
|
DSACK_INT<="11";
|
||||||
|
AS_000_INT <= '1';
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
DTACK_SYNC <= '1';
|
||||||
|
VPA_SYNC <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- VMA generation
|
||||||
|
--assert
|
||||||
|
if(CLK_000_D='0' AND VPA_SYNC='0')then
|
||||||
|
VMA_INT <= '0';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
--deassert
|
||||||
|
if(CLK_000_D='1' AND AS_000_INT='1')then
|
||||||
|
VMA_INT <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
|
||||||
|
--Amiga statemachine
|
||||||
|
case (SM_AMIGA) is
|
||||||
|
when IDLE_P => --68000:S0 wait for a falling edge
|
||||||
|
if( CLK_000_D='0' )then
|
||||||
|
SM_AMIGA<=IDLE_N;
|
||||||
|
end if;
|
||||||
|
when IDLE_N => --68000:S1 wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||||
|
--AS_000_START <='0';
|
||||||
|
if(CLK_000_D='1' )then --sample AS only at the rising edge!
|
||||||
|
if( AS_030_000_SYNC = '0' )then
|
||||||
|
AS_000_INT <= '0';
|
||||||
|
if (RW='1' and DS_030 = '0') then --read: set udl/lds
|
||||||
|
if(A(0)='0') then
|
||||||
|
UDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||||
|
LDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||||
|
if (RW='1' and DS_030 = '0') then --read: set udl/lds if ds was not ready
|
||||||
|
if(A(0)='0') then
|
||||||
|
UDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||||
|
LDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if(CLK_000_D='0')then
|
||||||
|
SM_AMIGA<=AS_SET_N;
|
||||||
|
end if;
|
||||||
|
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||||
|
if(CLK_000_D='1')then
|
||||||
|
if (RW='0' and DS_030 = '0') then --write: set udl/lds
|
||||||
|
if(A(0)='0') then
|
||||||
|
UDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
UDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||||
|
LDS_000_INT <= '0';
|
||||||
|
else
|
||||||
|
LDS_000_INT <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||||
|
end if;
|
||||||
|
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||||
|
if(CLK_000_D='0' )then
|
||||||
|
if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then
|
||||||
|
SM_AMIGA<=DATA_FETCH_N;
|
||||||
|
--else
|
||||||
|
-- SM_AMIGA<=AS_SET_N; -- no dtack sampled wait one clock: go back to AS_SET_N
|
||||||
|
end if;
|
||||||
|
else -- high clock: sample DTACK
|
||||||
|
if(VPA_D = '1' AND DTACK='0') then
|
||||||
|
DTACK_SYNC <= '0';
|
||||||
|
elsif(VPA_D='0' AND cpu_est=E4) then --vpa/vma cycle: sync VPA on E3
|
||||||
|
VPA_SYNC <= '0';
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||||
|
|
||||||
|
if(CLK_000_D='1')then
|
||||||
|
SM_AMIGA<=DATA_FETCH_P;
|
||||||
|
end if;
|
||||||
|
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||||
|
|
||||||
|
if( CLK_000 ='0')then
|
||||||
|
if( DTACK_SYNC ='0' OR
|
||||||
|
(VPA_SYNC ='0' and cpu_est=E10 ) )then
|
||||||
|
SM_AMIGA<=END_CYCLE_N;
|
||||||
|
--elsif(VPA_SYNC ='0')then
|
||||||
|
-- SM_AMIGA<=DATA_FETCH_N; --wait for right moment to end vpa-cyclus
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
when END_CYCLE_N =>--68000:S7: Latch/Store data and go to IDLE on high clock
|
||||||
|
if(CLK_000_D='1' and AS_000_INT='1' )then
|
||||||
|
SM_AMIGA<=IDLE_P;
|
||||||
|
elsif( CLK_000_D='0' AND CLK_OUT_PRE='1' --assert here (next 68030-Clock will be high)!
|
||||||
|
and AS_030_000_SYNC ='0' -- if the cycle somehow aboarded do not send a dsack!
|
||||||
|
) then --timing is everything!
|
||||||
|
if( (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='0') OR
|
||||||
|
(VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='1') OR
|
||||||
|
(DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='0') OR
|
||||||
|
(DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='1')
|
||||||
|
)then
|
||||||
|
DSACK_INT<="01";
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
--delay for hold time of CIAs
|
||||||
|
VMA_INT_D <= VMA_INT;
|
||||||
|
|
||||||
|
|
||||||
|
--dma stuff
|
||||||
|
--DTACK for DMA cycles
|
||||||
|
if(AS_000_INT ='0' AND DSACK(1) ='0') then
|
||||||
|
DTACK_DMA <= '0';
|
||||||
|
else
|
||||||
|
DTACK_DMA <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
SM_AMIGA_D <= SM_AMIGA;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
end process state_machine;
|
||||||
|
|
||||||
|
--output clock assignment
|
||||||
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||||
|
CLK_EXP <= '1' when SM_AMIGA_D /= SM_AMIGA ELSE '0';
|
||||||
|
AVEC_EXP <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
--dtack for dma
|
||||||
|
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||||
|
DTACK_DMA;
|
||||||
|
|
||||||
|
--fpu
|
||||||
|
FPU_CS <= FPU_CS_INT;
|
||||||
|
|
||||||
|
--if no copro is installed:
|
||||||
|
BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
--cache inhibit: For now: disable
|
||||||
|
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||||
|
--'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||||
|
'Z' WHEN not(A(31 downto 24) = x"00") ELSE
|
||||||
|
'0';
|
||||||
|
|
||||||
|
--bus buffers
|
||||||
|
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||||
|
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||||
|
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||||
|
|
||||||
|
--e and VMA
|
||||||
|
E <= cpu_est(3);
|
||||||
|
VMA <= VMA_INT;
|
||||||
|
|
||||||
|
|
||||||
|
--AVEC
|
||||||
|
AVEC <= '1';
|
||||||
|
|
||||||
|
--as and uds/lds
|
||||||
|
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||||
|
AS_000_INT;
|
||||||
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
UDS_000_INT;
|
||||||
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||||
|
LDS_000_INT;
|
||||||
|
|
||||||
|
--dsack
|
||||||
|
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||||
|
DSACK_INT;
|
||||||
|
BGACK_030 <= BGACK_030_INT;
|
||||||
|
-- signal assignment
|
||||||
|
--DS_030 <= "ZZ";
|
||||||
|
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- DS_030_INT;
|
||||||
|
|
||||||
|
--A(1) <= 'Z';
|
||||||
|
--A(0) <= 'Z';
|
||||||
|
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- A_INT;
|
||||||
|
|
||||||
|
--SIZE <= "ZZ";
|
||||||
|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||||
|
-- SIZE_INT;
|
||||||
|
|
||||||
|
end Behavioral;
|
||||||
|
|
|
@ -0,0 +1,6 @@
|
||||||
|
[synthesis-type]
|
||||||
|
tool=Synplify
|
||||||
|
[STRATEGY-LIST]
|
||||||
|
Normal=True, 1385910337
|
||||||
|
[TOUCHED-REPORT]
|
||||||
|
Design.tt4File=1400149811
|
|
@ -0,0 +1,46 @@
|
||||||
|
[WINDOWS]
|
||||||
|
MAIN_WINDOW_POSITION=0,0,1920,1200
|
||||||
|
LEFT_PANE_WIDTH=634
|
||||||
|
CHILD_FRAME_STATE=Maximal
|
||||||
|
CHILD_WINDOW_SIZE=1920,974
|
||||||
|
CHILD_WINDOW_POS=-8,-30
|
||||||
|
[GUI SETTING]
|
||||||
|
Remember_Setting=1
|
||||||
|
Open_PV_Opt=2
|
||||||
|
Open_PV=0
|
||||||
|
PV_IS_ACTIVE=0
|
||||||
|
ACTIVE_SHEET=Pin Attributes
|
||||||
|
Show_Def_Opt=2
|
||||||
|
Show_Def_Val=1
|
||||||
|
Expand_All_Column=0
|
||||||
|
Show_All_Signals=0
|
||||||
|
Sort_Type=0
|
||||||
|
Sort_Direction=0
|
||||||
|
Skip_Next_Pin=0
|
||||||
|
[Pin Attributes]
|
||||||
|
sort_column_1=Signal/Group Name
|
||||||
|
Type=42,no
|
||||||
|
Signal/Group Name=209,no
|
||||||
|
Group Members=111,no
|
||||||
|
GLB=36,no
|
||||||
|
Macrocell=73,no
|
||||||
|
Pin=32,no
|
||||||
|
Power=50,no
|
||||||
|
Slewrate=64,no
|
||||||
|
[Global Constraints]
|
||||||
|
Constraint Name=117,no
|
||||||
|
Constraint Value=115,no
|
||||||
|
[Resource Reservation]
|
||||||
|
Segment=66,no
|
||||||
|
GLB=36,no
|
||||||
|
Macrocell=73,no
|
||||||
|
Pin=32,no
|
||||||
|
State=43,no
|
||||||
|
[Opt Global Constraints]
|
||||||
|
Constraint Name=162,no
|
||||||
|
Constraint Value=115,no
|
||||||
|
[OPT WINDOWS]
|
||||||
|
MAIN_WINDOW_POSITION=0,0,1920,1200
|
||||||
|
[OPT GUI SETTING]
|
||||||
|
Remember_Setting=1
|
||||||
|
ACTIVE_SHEET=
|
|
@ -0,0 +1,183 @@
|
||||||
|
|
||||||
|
[Device]
|
||||||
|
Family = M4A5;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
Status = Production;
|
||||||
|
EN_PinGLB = Yes;
|
||||||
|
EN_PinMacrocell = Yes;
|
||||||
|
|
||||||
|
[Revision]
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
DATE = 05/15/2014;
|
||||||
|
TIME = 12:30:11;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
Synthesis = Synplify;
|
||||||
|
|
||||||
|
[Ignore Assignments]
|
||||||
|
|
||||||
|
[Clear Assignments]
|
||||||
|
|
||||||
|
[Backannotate Assignments]
|
||||||
|
|
||||||
|
[Global Constraints]
|
||||||
|
Spread_placement = Yes;
|
||||||
|
Zero_hold_time = Yes;
|
||||||
|
|
||||||
|
[Location Assignments]
|
||||||
|
layer = OFF;
|
||||||
|
AS_030 = Pin, 82, -, H, -;
|
||||||
|
A_0_ = Pin, 69, -, G, -;
|
||||||
|
A_16_ = Pin, 96, -, A, -;
|
||||||
|
A_17_ = Pin, 59, -, F, -;
|
||||||
|
A_18_ = Pin, 95, -, A, -;
|
||||||
|
A_19_ = Pin, 97, -, A, -;
|
||||||
|
BGACK_000 = Pin, 28, -, D, -;
|
||||||
|
BG_030 = Pin, 21, -, C, -;
|
||||||
|
CLK_000 = Pin, 11, -, -, -;
|
||||||
|
CLK_030 = Pin, 64, -, -, -;
|
||||||
|
CLK_OSZI = Pin, 61, -, -, -;
|
||||||
|
CPU_SPACE = Pin, 14, -, -, -;
|
||||||
|
FC_0_ = Pin, 57, -, F, -;
|
||||||
|
FC_1_ = Pin, 58, -, F, -;
|
||||||
|
IPL_0_ = Pin, 67, -, G, -;
|
||||||
|
IPL_1_ = Pin, 56, -, F, -;
|
||||||
|
IPL_2_ = Pin, 68, -, G, -;
|
||||||
|
RST = Pin, 86, -, -, -;
|
||||||
|
RW = Pin, 71, -, G, -;
|
||||||
|
SIZE_1_ = Pin, 79, -, H, -;
|
||||||
|
SIZE_0_ = Pin, 70, -, G, -;
|
||||||
|
VPA = Pin, 36, -, -, -;
|
||||||
|
AVEC = Pin, 92, -, A, -;
|
||||||
|
BGACK_030 = Pin, 83, -, H, -;
|
||||||
|
BG_000 = Pin, 29, -, D, -;
|
||||||
|
CLK_DIV_OUT = Pin, 65, -, G, -;
|
||||||
|
CLK_EXP = Pin, 10, -, B, -;
|
||||||
|
DSACK_0_ = Pin, 80, -, H, -;
|
||||||
|
E = Pin, 66, -, G, -;
|
||||||
|
FPU_CS = Pin, 78, -, H, -;
|
||||||
|
IPL_030_0_ = Pin, 8, -, B, -;
|
||||||
|
IPL_030_1_ = Pin, 7, -, B, -;
|
||||||
|
IPL_030_2_ = Pin, 9, -, B, -;
|
||||||
|
LDS_000 = Pin, 31, -, D, -;
|
||||||
|
UDS_000 = Pin, 32, -, D, -;
|
||||||
|
VMA = Pin, 35, -, D, -;
|
||||||
|
AS_000 = Pin, 33, -, D, -;
|
||||||
|
DSACK_1_ = Pin, 81, -, H, -;
|
||||||
|
DTACK = Pin, 30, -, D, -;
|
||||||
|
RESET = Pin, 3, -, B, -;
|
||||||
|
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
|
||||||
|
AMIGA_BUS_ENABLE = Pin, 34, -, D, -;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = Pin, 20, -, C, -;
|
||||||
|
CIIN = Pin, 47, -, E, -;
|
||||||
|
A_20_ = Pin, 93, -, A, -;
|
||||||
|
A_21_ = Pin, 94, -, A, -;
|
||||||
|
A_22_ = Pin, 85, -, H, -;
|
||||||
|
A_23_ = Pin, 84, -, H, -;
|
||||||
|
A_24_ = Pin, 19, -, C, -;
|
||||||
|
A_25_ = Pin, 18, -, C, -;
|
||||||
|
A_26_ = Pin, 17, -, C, -;
|
||||||
|
A_27_ = Pin, 16, -, C, -;
|
||||||
|
A_28_ = Pin, 15, -, C, -;
|
||||||
|
A_29_ = Pin, 6, -, B, -;
|
||||||
|
A_30_ = Pin, 5, -, B, -;
|
||||||
|
A_31_ = Pin, 4, -, B, -;
|
||||||
|
DS_030 = Pin, 98, -, A, -;
|
||||||
|
AVEC_EXP = Pin, 22, -, C, -;
|
||||||
|
BERR = Pin, 41, -, E, -;
|
||||||
|
|
||||||
|
[Group Assignments]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Resource Reservations]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Fitter Report Format]
|
||||||
|
|
||||||
|
[Power]
|
||||||
|
|
||||||
|
[Source Constraint Option]
|
||||||
|
|
||||||
|
[Fast Bypass]
|
||||||
|
|
||||||
|
[OSM Bypass]
|
||||||
|
|
||||||
|
[Input Registers]
|
||||||
|
|
||||||
|
[Netlist/Delay Format]
|
||||||
|
NetList = VHDL;
|
||||||
|
|
||||||
|
[IO Types]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Pullup]
|
||||||
|
Default = UP;
|
||||||
|
|
||||||
|
[Slewrate]
|
||||||
|
|
||||||
|
[Region]
|
||||||
|
|
||||||
|
[Timing Constraints]
|
||||||
|
|
||||||
|
[HSI Attributes]
|
||||||
|
|
||||||
|
[Input Delay]
|
||||||
|
|
||||||
|
[opt global constraints list]
|
||||||
|
|
||||||
|
[Explorer User Settings]
|
||||||
|
|
||||||
|
[Pin attributes list]
|
||||||
|
|
||||||
|
[global constraints list]
|
||||||
|
|
||||||
|
[Global Constraints Process Update]
|
||||||
|
|
||||||
|
[pin lock limitation]
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENTS LIST]
|
||||||
|
|
||||||
|
[RESOURCE RESERVATIONS LIST]
|
||||||
|
|
||||||
|
[individual constraints list]
|
||||||
|
|
||||||
|
[Attributes list setting]
|
||||||
|
|
||||||
|
[Timing Analyzer]
|
||||||
|
|
||||||
|
[PLL Assignments]
|
||||||
|
|
||||||
|
[Dual Function Macrocell]
|
||||||
|
|
||||||
|
[Explorer Results]
|
||||||
|
|
||||||
|
[VHDL synplify constraints]
|
||||||
|
|
||||||
|
[VHDL spectrum constraints]
|
||||||
|
|
||||||
|
[verilog synplify constraints]
|
||||||
|
|
||||||
|
[verilog spectrum constraints]
|
||||||
|
|
||||||
|
[VHDL synplify constraints list]
|
||||||
|
|
||||||
|
[VHDL spectrum constraints list]
|
||||||
|
|
||||||
|
[verilog synplify constraints list]
|
||||||
|
|
||||||
|
[verilog spectrum constraints list]
|
||||||
|
|
||||||
|
[Constraint Version]
|
||||||
|
version = 1.0;
|
||||||
|
|
||||||
|
[ORP ASSIGNMENTS]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Node attribute]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[SYMBOL/MODULE attribute]
|
||||||
|
layer = OFF;
|
|
@ -0,0 +1,183 @@
|
||||||
|
|
||||||
|
[Device]
|
||||||
|
Family = M4A5;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
Status = Production;
|
||||||
|
EN_PinGLB = Yes;
|
||||||
|
EN_PinMacrocell = Yes;
|
||||||
|
|
||||||
|
[Revision]
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
DATE = 05/15/2014;
|
||||||
|
TIME = 12:30:11;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
Synthesis = Synplify;
|
||||||
|
|
||||||
|
[Ignore Assignments]
|
||||||
|
|
||||||
|
[Clear Assignments]
|
||||||
|
|
||||||
|
[Backannotate Assignments]
|
||||||
|
|
||||||
|
[Global Constraints]
|
||||||
|
Spread_placement = Yes;
|
||||||
|
Zero_hold_time = Yes;
|
||||||
|
|
||||||
|
[Location Assignments]
|
||||||
|
layer = OFF;
|
||||||
|
AS_030 = Pin, 82, -, H, -;
|
||||||
|
A_0_ = Pin, 69, -, G, -;
|
||||||
|
A_16_ = Pin, 96, -, A, -;
|
||||||
|
A_17_ = Pin, 59, -, F, -;
|
||||||
|
A_18_ = Pin, 95, -, A, -;
|
||||||
|
A_19_ = Pin, 97, -, A, -;
|
||||||
|
BGACK_000 = Pin, 28, -, D, -;
|
||||||
|
BG_030 = Pin, 21, -, C, -;
|
||||||
|
CLK_000 = Pin, 11, -, -, -;
|
||||||
|
CLK_030 = Pin, 64, -, -, -;
|
||||||
|
CLK_OSZI = Pin, 61, -, -, -;
|
||||||
|
CPU_SPACE = Pin, 14, -, -, -;
|
||||||
|
FC_0_ = Pin, 57, -, F, -;
|
||||||
|
FC_1_ = Pin, 58, -, F, -;
|
||||||
|
IPL_0_ = Pin, 67, -, G, -;
|
||||||
|
IPL_1_ = Pin, 56, -, F, -;
|
||||||
|
IPL_2_ = Pin, 68, -, G, -;
|
||||||
|
RST = Pin, 86, -, -, -;
|
||||||
|
RW = Pin, 71, -, G, -;
|
||||||
|
SIZE_1_ = Pin, 79, -, H, -;
|
||||||
|
SIZE_0_ = Pin, 70, -, G, -;
|
||||||
|
VPA = Pin, 36, -, -, -;
|
||||||
|
AVEC = Pin, 92, -, A, -;
|
||||||
|
BGACK_030 = Pin, 83, -, H, -;
|
||||||
|
BG_000 = Pin, 29, -, D, -;
|
||||||
|
CLK_DIV_OUT = Pin, 65, -, G, -;
|
||||||
|
CLK_EXP = Pin, 10, -, B, -;
|
||||||
|
DSACK_0_ = Pin, 80, -, H, -;
|
||||||
|
E = Pin, 66, -, G, -;
|
||||||
|
FPU_CS = Pin, 78, -, H, -;
|
||||||
|
IPL_030_0_ = Pin, 8, -, B, -;
|
||||||
|
IPL_030_1_ = Pin, 7, -, B, -;
|
||||||
|
IPL_030_2_ = Pin, 9, -, B, -;
|
||||||
|
LDS_000 = Pin, 31, -, D, -;
|
||||||
|
UDS_000 = Pin, 32, -, D, -;
|
||||||
|
VMA = Pin, 35, -, D, -;
|
||||||
|
AS_000 = Pin, 33, -, D, -;
|
||||||
|
DSACK_1_ = Pin, 81, -, H, -;
|
||||||
|
DTACK = Pin, 30, -, D, -;
|
||||||
|
RESET = Pin, 3, -, B, -;
|
||||||
|
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
|
||||||
|
AMIGA_BUS_ENABLE = Pin, 34, -, D, -;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = Pin, 20, -, C, -;
|
||||||
|
CIIN = Pin, 47, -, E, -;
|
||||||
|
A_20_ = Pin, 93, -, A, -;
|
||||||
|
A_21_ = Pin, 94, -, A, -;
|
||||||
|
A_22_ = Pin, 85, -, H, -;
|
||||||
|
A_23_ = Pin, 84, -, H, -;
|
||||||
|
A_24_ = Pin, 19, -, C, -;
|
||||||
|
A_25_ = Pin, 18, -, C, -;
|
||||||
|
A_26_ = Pin, 17, -, C, -;
|
||||||
|
A_27_ = Pin, 16, -, C, -;
|
||||||
|
A_28_ = Pin, 15, -, C, -;
|
||||||
|
A_29_ = Pin, 6, -, B, -;
|
||||||
|
A_30_ = Pin, 5, -, B, -;
|
||||||
|
A_31_ = Pin, 4, -, B, -;
|
||||||
|
DS_030 = Pin, 98, -, A, -;
|
||||||
|
AVEC_EXP = Pin, 22, -, C, -;
|
||||||
|
BERR = Pin, 41, -, E, -;
|
||||||
|
|
||||||
|
[Group Assignments]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Resource Reservations]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Fitter Report Format]
|
||||||
|
|
||||||
|
[Power]
|
||||||
|
|
||||||
|
[Source Constraint Option]
|
||||||
|
|
||||||
|
[Fast Bypass]
|
||||||
|
|
||||||
|
[OSM Bypass]
|
||||||
|
|
||||||
|
[Input Registers]
|
||||||
|
|
||||||
|
[Netlist/Delay Format]
|
||||||
|
NetList = VHDL;
|
||||||
|
|
||||||
|
[IO Types]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Pullup]
|
||||||
|
Default = UP;
|
||||||
|
|
||||||
|
[Slewrate]
|
||||||
|
|
||||||
|
[Region]
|
||||||
|
|
||||||
|
[Timing Constraints]
|
||||||
|
|
||||||
|
[HSI Attributes]
|
||||||
|
|
||||||
|
[Input Delay]
|
||||||
|
|
||||||
|
[opt global constraints list]
|
||||||
|
|
||||||
|
[Explorer User Settings]
|
||||||
|
|
||||||
|
[Pin attributes list]
|
||||||
|
|
||||||
|
[global constraints list]
|
||||||
|
|
||||||
|
[Global Constraints Process Update]
|
||||||
|
|
||||||
|
[pin lock limitation]
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENTS LIST]
|
||||||
|
|
||||||
|
[RESOURCE RESERVATIONS LIST]
|
||||||
|
|
||||||
|
[individual constraints list]
|
||||||
|
|
||||||
|
[Attributes list setting]
|
||||||
|
|
||||||
|
[Timing Analyzer]
|
||||||
|
|
||||||
|
[PLL Assignments]
|
||||||
|
|
||||||
|
[Dual Function Macrocell]
|
||||||
|
|
||||||
|
[Explorer Results]
|
||||||
|
|
||||||
|
[VHDL synplify constraints]
|
||||||
|
|
||||||
|
[VHDL spectrum constraints]
|
||||||
|
|
||||||
|
[verilog synplify constraints]
|
||||||
|
|
||||||
|
[verilog spectrum constraints]
|
||||||
|
|
||||||
|
[VHDL synplify constraints list]
|
||||||
|
|
||||||
|
[VHDL spectrum constraints list]
|
||||||
|
|
||||||
|
[verilog synplify constraints list]
|
||||||
|
|
||||||
|
[verilog spectrum constraints list]
|
||||||
|
|
||||||
|
[Constraint Version]
|
||||||
|
version = 1.0;
|
||||||
|
|
||||||
|
[ORP ASSIGNMENTS]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[Node attribute]
|
||||||
|
layer = OFF;
|
||||||
|
|
||||||
|
[SYMBOL/MODULE attribute]
|
||||||
|
layer = OFF;
|
|
@ -0,0 +1,11 @@
|
||||||
|
JDF B
|
||||||
|
// Created by Version 1.7
|
||||||
|
PROJECT 68030_TK
|
||||||
|
DESIGN 68030_tk Normal
|
||||||
|
DEVKIT M4A5-128/64-10VC
|
||||||
|
ENTRY Pure VHDL
|
||||||
|
MODULE 68030-68000-bus.vhd
|
||||||
|
MODSTYLE BUS68030 Normal
|
||||||
|
SYNTHESIS_TOOL Synplify
|
||||||
|
SIMULATOR_TOOL ActiveHDL
|
||||||
|
TOPMODULE BUS68030
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,5 @@
|
||||||
|
[Tcl]
|
||||||
|
Start = Yes;
|
||||||
|
Process = YES;
|
||||||
|
Append = YES;
|
||||||
|
TclFilename = 68030_TK.tcl;
|
|
@ -0,0 +1 @@
|
||||||
|
-collapse all -pterms 16 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,842 @@
|
||||||
|
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
#$ DATE Thu May 15 19:20:52 2014
|
||||||
|
#$ MODULE 68030_tk
|
||||||
|
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ IPL_030_2_ A_24_ A_23_ \
|
||||||
|
# IPL_2_ A_22_ A_21_ DSACK_1_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 \
|
||||||
|
# UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
|
||||||
|
# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK A_0_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E \
|
||||||
|
# IPL_1_ VPA IPL_0_ VMA DSACK_0_ RST FC_0_ RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
|
||||||
|
# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_
|
||||||
|
#$ NODES 43 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_FPU_CS_INTreg \
|
||||||
|
# cpu_est_3_reg inst_VMA_INTreg cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC \
|
||||||
|
# inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD \
|
||||||
|
# inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ BG_000DFFSHreg \
|
||||||
|
# SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg inst_RISING_CLK_AMIGA \
|
||||||
|
# DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ \
|
||||||
|
# CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ IPL_030DFFSH_0_reg SM_AMIGA_2_ \
|
||||||
|
# IPL_030DFFSH_1_reg SM_AMIGA_1_ SM_AMIGA_0_ IPL_030DFFSH_2_reg SM_AMIGA_D_0_ \
|
||||||
|
# SM_AMIGA_D_1_ SM_AMIGA_D_2_ RESETDFFreg un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.model bus68030
|
||||||
|
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
|
||||||
|
CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
|
||||||
|
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
|
||||||
|
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
|
||||||
|
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \
|
||||||
|
IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
|
||||||
|
inst_CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \
|
||||||
|
inst_VMA_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \
|
||||||
|
inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \
|
||||||
|
inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
|
||||||
|
inst_CLK_OUT_PRE.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \
|
||||||
|
SM_AMIGA_6_.BLIF BG_000DFFSHreg.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \
|
||||||
|
inst_LDS_000_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF DSACK_INT_1_.BLIF \
|
||||||
|
inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \
|
||||||
|
CLK_000_CNT_0_.BLIF CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF \
|
||||||
|
CLK_000_CNT_3_.BLIF IPL_030DFFSH_0_reg.BLIF SM_AMIGA_2_.BLIF \
|
||||||
|
IPL_030DFFSH_1_reg.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
|
||||||
|
IPL_030DFFSH_2_reg.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF \
|
||||||
|
SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \
|
||||||
|
DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
|
||||||
|
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
|
||||||
|
FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
|
||||||
|
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \
|
||||||
|
SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \
|
||||||
|
SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \
|
||||||
|
SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.D cpu_est_0_.C \
|
||||||
|
cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C \
|
||||||
|
SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C \
|
||||||
|
SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D \
|
||||||
|
CLK_000_CNT_0_.C CLK_000_CNT_1_.D CLK_000_CNT_1_.C CLK_000_CNT_2_.D \
|
||||||
|
CLK_000_CNT_2_.C CLK_000_CNT_3_.D CLK_000_CNT_3_.C SM_AMIGA_D_0_.D \
|
||||||
|
SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D \
|
||||||
|
SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \
|
||||||
|
IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \
|
||||||
|
IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \
|
||||||
|
IPL_030DFFSH_2_reg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
|
||||||
|
inst_AS_030_000_SYNC.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \
|
||||||
|
BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_INTreg.D \
|
||||||
|
inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \
|
||||||
|
inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \
|
||||||
|
inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C DSACK_INT_1_.C \
|
||||||
|
DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \
|
||||||
|
inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \
|
||||||
|
inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \
|
||||||
|
inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \
|
||||||
|
inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_CNT_0_.D CLK_CNT_0_.C \
|
||||||
|
inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C inst_VPA_D.D inst_VPA_D.C \
|
||||||
|
inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \
|
||||||
|
inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \
|
||||||
|
inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 \
|
||||||
|
DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \
|
||||||
|
AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 cpu_est_3_reg.D.X1 \
|
||||||
|
cpu_est_3_reg.D.X2 DSACK_INT_1_.D.X1 DSACK_INT_1_.D.X2
|
||||||
|
.names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
|
||||||
|
01- 1
|
||||||
|
0-1 1
|
||||||
|
-00 0
|
||||||
|
1-- 0
|
||||||
|
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
|
||||||
|
--11- 1
|
||||||
|
11--1 1
|
||||||
|
--1-1 1
|
||||||
|
-00-- 0
|
||||||
|
0-0-- 0
|
||||||
|
---00 0
|
||||||
|
--0-0 0
|
||||||
|
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
|
||||||
|
-001- 1
|
||||||
|
0-01- 1
|
||||||
|
--0-1 1
|
||||||
|
11--0 0
|
||||||
|
--1-- 0
|
||||||
|
---00 0
|
||||||
|
.names CLK_000.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_DTACK_SYNC.BLIF \
|
||||||
|
inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF \
|
||||||
|
SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_1_.D
|
||||||
|
-----1--1- 1
|
||||||
|
---1---001 1
|
||||||
|
---1--0-01 1
|
||||||
|
---11---01 1
|
||||||
|
--01----01 1
|
||||||
|
-0-1----01 1
|
||||||
|
1-------01 1
|
||||||
|
011-0-110- 0
|
||||||
|
0--0----0- 0
|
||||||
|
-----0--1- 0
|
||||||
|
--------00 0
|
||||||
|
.names CLK_000.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \
|
||||||
|
inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF \
|
||||||
|
cpu_est_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
|
||||||
|
011--0-111- 1
|
||||||
|
0---0----1- 1
|
||||||
|
------0---1 1
|
||||||
|
---0------1 1
|
||||||
|
---11-1-0-- 0
|
||||||
|
---11-10--- 0
|
||||||
|
---1111---- 0
|
||||||
|
--011-1---- 0
|
||||||
|
-0-11-1---- 0
|
||||||
|
---1--1--0- 0
|
||||||
|
1--1--1---- 0
|
||||||
|
----1---0-0 0
|
||||||
|
----1--0--0 0
|
||||||
|
----11----0 0
|
||||||
|
--0-1-----0 0
|
||||||
|
-0--1-----0 0
|
||||||
|
---------00 0
|
||||||
|
1---------0 0
|
||||||
|
.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_1_.D
|
||||||
|
0-10-0 1
|
||||||
|
00101- 1
|
||||||
|
1-100- 1
|
||||||
|
-1--0- 1
|
||||||
|
11---1 1
|
||||||
|
-1-1-- 1
|
||||||
|
-10--- 1
|
||||||
|
011011 0
|
||||||
|
1-1010 0
|
||||||
|
00--01 0
|
||||||
|
10--1- 0
|
||||||
|
-0-1-- 0
|
||||||
|
-00--- 0
|
||||||
|
.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_2_.D
|
||||||
|
-0100- 1
|
||||||
|
1-101- 1
|
||||||
|
-1---1 1
|
||||||
|
---1-1 1
|
||||||
|
--0--1 1
|
||||||
|
0---10 0
|
||||||
|
00101- 0
|
||||||
|
-1--00 0
|
||||||
|
---1-0 0
|
||||||
|
--0--0 0
|
||||||
|
.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \
|
||||||
|
SM_AMIGA_0_.BLIF SM_AMIGA_7_.D
|
||||||
|
-11- 1
|
||||||
|
11-1 1
|
||||||
|
0-0- 0
|
||||||
|
--00 0
|
||||||
|
-0-- 0
|
||||||
|
.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF \
|
||||||
|
SM_AMIGA_7_.BLIF SM_AMIGA_6_.D
|
||||||
|
-01- 1
|
||||||
|
1-1- 1
|
||||||
|
-0-1 1
|
||||||
|
01-- 0
|
||||||
|
-10- 0
|
||||||
|
--00 0
|
||||||
|
.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF \
|
||||||
|
SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
|
||||||
|
011- 1
|
||||||
|
-1-1 1
|
||||||
|
-0-- 0
|
||||||
|
--00 0
|
||||||
|
1--0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF CLK_000_CNT_0_.D
|
||||||
|
10- 1
|
||||||
|
01- 1
|
||||||
|
--0 1
|
||||||
|
001 0
|
||||||
|
111 0
|
||||||
|
.names RST.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF \
|
||||||
|
SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_0_.D
|
||||||
|
1---1- 1
|
||||||
|
1--1-- 1
|
||||||
|
1-1--- 1
|
||||||
|
11---- 1
|
||||||
|
0----1 1
|
||||||
|
10000- 0
|
||||||
|
0----0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_1_.BLIF \
|
||||||
|
SM_AMIGA_0_.BLIF SM_AMIGA_D_1_.BLIF SM_AMIGA_D_1_.D
|
||||||
|
1---1- 1
|
||||||
|
1--1-- 1
|
||||||
|
1-1--- 1
|
||||||
|
11---- 1
|
||||||
|
0----1 1
|
||||||
|
10000- 0
|
||||||
|
0----0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF \
|
||||||
|
SM_AMIGA_0_.BLIF SM_AMIGA_D_2_.BLIF SM_AMIGA_D_2_.D
|
||||||
|
1---1- 1
|
||||||
|
1--1-- 1
|
||||||
|
1-1--- 1
|
||||||
|
11---- 1
|
||||||
|
0----1 1
|
||||||
|
10000- 0
|
||||||
|
0----0 0
|
||||||
|
.names IPL_0_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_0_reg.BLIF \
|
||||||
|
IPL_030DFFSH_0_reg.D
|
||||||
|
11- 1
|
||||||
|
-01 1
|
||||||
|
01- 0
|
||||||
|
-00 0
|
||||||
|
.names IPL_1_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_1_reg.BLIF \
|
||||||
|
IPL_030DFFSH_1_reg.D
|
||||||
|
11- 1
|
||||||
|
-01 1
|
||||||
|
01- 0
|
||||||
|
-00 0
|
||||||
|
.names IPL_2_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_2_reg.BLIF \
|
||||||
|
IPL_030DFFSH_2_reg.D
|
||||||
|
11- 1
|
||||||
|
-01 1
|
||||||
|
01- 0
|
||||||
|
-00 0
|
||||||
|
.names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
|
||||||
|
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \
|
||||||
|
inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D
|
||||||
|
1--1100101- 1
|
||||||
|
----0-----1 1
|
||||||
|
--1-1------ 1
|
||||||
|
-1--------- 1
|
||||||
|
-00-1----0- 0
|
||||||
|
-00-1---1-- 0
|
||||||
|
-00-1--0--- 0
|
||||||
|
-00-1-1---- 0
|
||||||
|
-00-11----- 0
|
||||||
|
-0001------ 0
|
||||||
|
000-1------ 0
|
||||||
|
-0--0-----0 0
|
||||||
|
.names AS_030.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF \
|
||||||
|
inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF \
|
||||||
|
SM_AMIGA_3_.BLIF inst_VPA_SYNC.D
|
||||||
|
----1--0- 1
|
||||||
|
----1-0-- 1
|
||||||
|
----10--- 1
|
||||||
|
---11---- 1
|
||||||
|
--1-1---- 1
|
||||||
|
-1--1---- 1
|
||||||
|
----1---0 1
|
||||||
|
1------0- 1
|
||||||
|
1-----0-- 1
|
||||||
|
1----0--- 1
|
||||||
|
1--1----- 1
|
||||||
|
1-1------ 1
|
||||||
|
11------- 1
|
||||||
|
1-------0 1
|
||||||
|
-000-1111 0
|
||||||
|
0---0---- 0
|
||||||
|
.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \
|
||||||
|
BG_000DFFSHreg.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D
|
||||||
|
---1-1- 1
|
||||||
|
---00-0 1
|
||||||
|
-1-0--- 1
|
||||||
|
0--0--- 1
|
||||||
|
--1---- 1
|
||||||
|
10001-- 0
|
||||||
|
1000--1 0
|
||||||
|
--01-0- 0
|
||||||
|
.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||||
|
inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D
|
||||||
|
-1-0- 1
|
||||||
|
-11-- 1
|
||||||
|
-1--0 1
|
||||||
|
1--0- 1
|
||||||
|
1-1-- 1
|
||||||
|
1---0 1
|
||||||
|
--011 0
|
||||||
|
00--- 0
|
||||||
|
.names inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF inst_VPA_SYNC.BLIF \
|
||||||
|
inst_CLK_000_D.BLIF inst_VMA_INTreg.D
|
||||||
|
1-1- 1
|
||||||
|
1--1 1
|
||||||
|
-1-1 1
|
||||||
|
00-- 0
|
||||||
|
--00 0
|
||||||
|
0--0 0
|
||||||
|
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF \
|
||||||
|
inst_BGACK_030_INTreg.D
|
||||||
|
11- 1
|
||||||
|
1-1 1
|
||||||
|
-00 0
|
||||||
|
0-- 0
|
||||||
|
.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||||
|
inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \
|
||||||
|
SM_AMIGA_5_.BLIF inst_UDS_000_INTreg.D
|
||||||
|
1-0-----0- 1
|
||||||
|
--0----10- 1
|
||||||
|
-011011--- 1
|
||||||
|
-001-10-10 1
|
||||||
|
-00111--10 1
|
||||||
|
--0-0-11-- 1
|
||||||
|
1-0-0-1--- 1
|
||||||
|
-011-----1 1
|
||||||
|
--1---01-0 1
|
||||||
|
--1-1--1-0 1
|
||||||
|
1-1---0--0 1
|
||||||
|
1-1-1----0 1
|
||||||
|
-1-----1-- 1
|
||||||
|
11-------- 1
|
||||||
|
--0----1-1 1
|
||||||
|
1-0------1 1
|
||||||
|
-----0-1-0 1
|
||||||
|
1----0---0 1
|
||||||
|
0-0----00- 0
|
||||||
|
-010011--- 0
|
||||||
|
-000-10-10 0
|
||||||
|
-00011--10 0
|
||||||
|
0-0-0-10-- 0
|
||||||
|
-010-----1 0
|
||||||
|
0-1---00-0 0
|
||||||
|
0-1-1--0-0 0
|
||||||
|
01-----0-- 0
|
||||||
|
0-0----0-1 0
|
||||||
|
0----0-0-0 0
|
||||||
|
.names SIZE_1_.BLIF AS_030.BLIF SIZE_0_.BLIF A_0_.BLIF \
|
||||||
|
inst_LDS_000_INTreg.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \
|
||||||
|
inst_LDS_000_INTreg.D
|
||||||
|
0-10-1 1
|
||||||
|
----10 1
|
||||||
|
-1---0 1
|
||||||
|
-0--00 0
|
||||||
|
---1-1 0
|
||||||
|
--0--1 0
|
||||||
|
1----1 0
|
||||||
|
.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D
|
||||||
|
-1--0- 1
|
||||||
|
-1-0-- 1
|
||||||
|
-10--- 1
|
||||||
|
-1---1 1
|
||||||
|
1---0- 1
|
||||||
|
1--0-- 1
|
||||||
|
1-0--- 1
|
||||||
|
1----1 1
|
||||||
|
--1110 0
|
||||||
|
00---- 0
|
||||||
|
.names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
|
||||||
|
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \
|
||||||
|
inst_FPU_CS_INTreg.D
|
||||||
|
---0-----1 1
|
||||||
|
---1----0- 1
|
||||||
|
---1---1-- 1
|
||||||
|
---1--0--- 1
|
||||||
|
---1-1---- 1
|
||||||
|
---11----- 1
|
||||||
|
--01------ 1
|
||||||
|
0--1------ 1
|
||||||
|
-1-------- 1
|
||||||
|
101100101- 0
|
||||||
|
-0-0-----0 0
|
||||||
|
.names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D
|
||||||
|
1- 1
|
||||||
|
-1 1
|
||||||
|
00 0
|
||||||
|
.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names DS_030.BLIF RW.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF \
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
01011-- 1
|
||||||
|
00-1010 1
|
||||||
|
0011-10 1
|
||||||
|
01----1 1
|
||||||
|
-0---0- 0
|
||||||
|
-00-1-- 0
|
||||||
|
-1--0-0 0
|
||||||
|
-11---0 0
|
||||||
|
1------ 0
|
||||||
|
-0----1 0
|
||||||
|
---0--0 0
|
||||||
|
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_AS_000_INTreg.BLIF AS_000
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_UDS_000_INTreg.BLIF UDS_000
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_LDS_000_INTreg.BLIF LDS_000
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names BERR
|
||||||
|
0
|
||||||
|
.names BG_000DFFSHreg.BLIF BG_000
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_FPU_CS_INTreg.BLIF FPU_CS
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names AVEC
|
||||||
|
1
|
||||||
|
.names AVEC_EXP
|
||||||
|
0
|
||||||
|
.names cpu_est_3_reg.BLIF E
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_VMA_INTreg.BLIF VMA
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RESETDFFreg.BLIF RESET
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names AMIGA_BUS_ENABLE
|
||||||
|
0
|
||||||
|
.names RW.BLIF AMIGA_BUS_DATA_DIR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names AMIGA_BUS_ENABLE_LOW
|
||||||
|
1
|
||||||
|
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
|
||||||
|
1111 1
|
||||||
|
--0- 0
|
||||||
|
-0-- 0
|
||||||
|
0--- 0
|
||||||
|
---0 0
|
||||||
|
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_4_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_3_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_2_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_1_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_0_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_0_.D
|
||||||
|
100 1
|
||||||
|
-11 1
|
||||||
|
0-1 1
|
||||||
|
101 0
|
||||||
|
-10 0
|
||||||
|
0-0 0
|
||||||
|
.names CLK_OSZI.BLIF cpu_est_0_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF cpu_est_1_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF cpu_est_2_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF cpu_est_3_reg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_7_.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_6_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF SM_AMIGA_5_.AR
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF CLK_000_CNT_0_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \
|
||||||
|
CLK_000_CNT_1_.BLIF CLK_000_CNT_1_.D
|
||||||
|
0010 1
|
||||||
|
1110 1
|
||||||
|
0001 1
|
||||||
|
1101 1
|
||||||
|
10-- 0
|
||||||
|
01-- 0
|
||||||
|
--00 0
|
||||||
|
--11 0
|
||||||
|
.names CLK_OSZI.BLIF CLK_000_CNT_1_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \
|
||||||
|
CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_2_.D
|
||||||
|
00110 1
|
||||||
|
11110 1
|
||||||
|
00-01 1
|
||||||
|
11-01 1
|
||||||
|
000-1 1
|
||||||
|
110-1 1
|
||||||
|
--111 0
|
||||||
|
10--- 0
|
||||||
|
01--- 0
|
||||||
|
---00 0
|
||||||
|
--0-0 0
|
||||||
|
.names CLK_OSZI.BLIF CLK_000_CNT_2_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \
|
||||||
|
CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D
|
||||||
|
001110 1
|
||||||
|
111110 1
|
||||||
|
00--01 1
|
||||||
|
11--01 1
|
||||||
|
00-0-1 1
|
||||||
|
11-0-1 1
|
||||||
|
000--1 1
|
||||||
|
110--1 1
|
||||||
|
--1111 0
|
||||||
|
10---- 0
|
||||||
|
01---- 0
|
||||||
|
----00 0
|
||||||
|
---0-0 0
|
||||||
|
--0--0 0
|
||||||
|
.names CLK_OSZI.BLIF CLK_000_CNT_3_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_D_0_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_D_1_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF SM_AMIGA_D_2_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF IPL_030DFFSH_0_reg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF IPL_030DFFSH_1_reg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF IPL_030DFFSH_2_reg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_AS_030_000_SYNC.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_VPA_SYNC.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_VPA_SYNC.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF BG_000DFFSHreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_AS_000_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_AS_000_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_VMA_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_BGACK_030_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names inst_CLK_OUT_PRE.BLIF CLK_CNT_0_.BLIF inst_CLK_OUT_PRE.D
|
||||||
|
10 1
|
||||||
|
01 1
|
||||||
|
00 0
|
||||||
|
11 0
|
||||||
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF DSACK_INT_1_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF DSACK_INT_1_.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_UDS_000_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_LDS_000_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_LDS_000_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_DTACK_SYNC.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_DTACK_SYNC.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_FPU_CS_INTreg.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_DTACK_DMA.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF inst_DTACK_DMA.AP
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CLK_OSZI.BLIF CLK_CNT_0_.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF inst_RISING_CLK_AMIGA.D
|
||||||
|
10 1
|
||||||
|
0- 0
|
||||||
|
-1 0
|
||||||
|
.names CLK_OSZI.BLIF inst_RISING_CLK_AMIGA.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names VPA.BLIF inst_VPA_D.D
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF inst_VPA_D.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_000.BLIF inst_CLK_000_D.D
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF inst_CLK_000_D.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names RST.BLIF RESETDFFreg.D
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF RESETDFFreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF inst_CLK_000_DD.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_INTreg.D
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names CLK_OSZI.BLIF inst_CLK_OUT_INTreg.C
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names DSACK_INT_1_.BLIF DSACK_1_
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_DTACK_DMA.BLIF DTACK
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names DSACK_0_
|
||||||
|
1
|
||||||
|
.names CPU_SPACE.BLIF DSACK_1_.OE
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names inst_BGACK_030_INTreg.BLIF DTACK.OE
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
|
||||||
|
1 1
|
||||||
|
0 0
|
||||||
|
.names inst_FPU_CS_INTreg.BLIF BERR.OE
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names CPU_SPACE.BLIF DSACK_0_.OE
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
|
||||||
|
0 1
|
||||||
|
1 0
|
||||||
|
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
|
||||||
|
A_25_.BLIF A_24_.BLIF CIIN.OE
|
||||||
|
00000000 1
|
||||||
|
------1- 0
|
||||||
|
-----1-- 0
|
||||||
|
----1--- 0
|
||||||
|
---1---- 0
|
||||||
|
--1----- 0
|
||||||
|
-1------ 0
|
||||||
|
1------- 0
|
||||||
|
-------1 0
|
||||||
|
.names SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF \
|
||||||
|
SM_AMIGA_D_2_.BLIF CLK_EXP.X1
|
||||||
|
1111 1
|
||||||
|
0--- 0
|
||||||
|
-0-- 0
|
||||||
|
--0- 0
|
||||||
|
---0 0
|
||||||
|
.names SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \
|
||||||
|
SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \
|
||||||
|
SM_AMIGA_D_1_.BLIF SM_AMIGA_D_2_.BLIF CLK_EXP.X2
|
||||||
|
00--0--1-- 1
|
||||||
|
-0-0-0--1- 1
|
||||||
|
--0-00---1 1
|
||||||
|
---1----0- 1
|
||||||
|
--1------0 1
|
||||||
|
1------0-- 1
|
||||||
|
-----1--0- 1
|
||||||
|
-----1---0 1
|
||||||
|
----1--0-- 1
|
||||||
|
----1----0 1
|
||||||
|
-1-----0-- 1
|
||||||
|
-1------0- 1
|
||||||
|
------1--- 1
|
||||||
|
-11---0111 0
|
||||||
|
-1--1-0111 0
|
||||||
|
---11-0111 0
|
||||||
|
1----10111 0
|
||||||
|
-1---10111 0
|
||||||
|
----110111 0
|
||||||
|
1-11--0111 0
|
||||||
|
00--010011 0
|
||||||
|
-0-0100101 0
|
||||||
|
-10-000110 0
|
||||||
|
00110-0011 0
|
||||||
|
1010-00101 0
|
||||||
|
1-01000110 0
|
||||||
|
0010000001 0
|
||||||
|
0001000010 0
|
||||||
|
1000000100 0
|
||||||
|
0000000000 0
|
||||||
|
.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF cpu_est_3_reg.D.X1
|
||||||
|
11 1
|
||||||
|
0- 0
|
||||||
|
-0 0
|
||||||
|
.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
|
||||||
|
inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
|
||||||
|
10---- 1
|
||||||
|
-01000 1
|
||||||
|
011010 1
|
||||||
|
1-1011 1
|
||||||
|
0-0--- 0
|
||||||
|
-10--- 0
|
||||||
|
0--1-- 0
|
||||||
|
-1-1-- 0
|
||||||
|
-1--0- 0
|
||||||
|
0----1 0
|
||||||
|
00--1- 0
|
||||||
|
11---0 0
|
||||||
|
.names AS_030.BLIF DSACK_INT_1_.BLIF DSACK_INT_1_.D.X1
|
||||||
|
00 1
|
||||||
|
1- 0
|
||||||
|
-1 0
|
||||||
|
.names AS_030.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \
|
||||||
|
inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF DSACK_INT_1_.BLIF \
|
||||||
|
CLK_000_CNT_0_.BLIF CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF \
|
||||||
|
CLK_000_CNT_3_.BLIF SM_AMIGA_0_.BLIF DSACK_INT_1_.D.X2
|
||||||
|
0-----0----- 1
|
||||||
|
-1---------- 1
|
||||||
|
----1------- 1
|
||||||
|
-----0------ 1
|
||||||
|
-----------0 1
|
||||||
|
--11-------- 1
|
||||||
|
-------0000- 1
|
||||||
|
100-01-1---1 0
|
||||||
|
10-001-1---1 0
|
||||||
|
-00-0111---1 0
|
||||||
|
-0-00111---1 0
|
||||||
|
100-01--1--1 0
|
||||||
|
10-001--1--1 0
|
||||||
|
-00-011-1--1 0
|
||||||
|
-0-0011-1--1 0
|
||||||
|
100-01---1-1 0
|
||||||
|
10-001---1-1 0
|
||||||
|
-00-011--1-1 0
|
||||||
|
-0-0011--1-1 0
|
||||||
|
100-01----11 0
|
||||||
|
10-001----11 0
|
||||||
|
-00-011---11 0
|
||||||
|
-0-0011---11 0
|
||||||
|
.end
|
|
@ -0,0 +1,14 @@
|
||||||
|
// Signal Name Cross Reference File
|
||||||
|
// ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
|
||||||
|
// Design '68030_tk' created Thu May 15 19:20:52 2014
|
||||||
|
|
||||||
|
|
||||||
|
// LEGEND: '>' Functional Block Port Separator
|
||||||
|
// '/' Hierarchy Path Separator
|
||||||
|
// '@' Automatically Generated Node
|
||||||
|
|
||||||
|
|
||||||
|
// Hierarchical Name Short Name
|
||||||
|
|
||||||
|
// *** Shortened names not required for this design. ***
|
|
@ -0,0 +1 @@
|
||||||
|
-dev mach4a_DT_NCE -clust 5
|
|
@ -0,0 +1,494 @@
|
||||||
|
ispLEVER Classic 1.7.00.05.28.13 Linked Equations File
|
||||||
|
Copyright(C), 1992-2013, Lattice Semiconductor Corp.
|
||||||
|
All Rights Reserved.
|
||||||
|
|
||||||
|
Design bus68030 created Thu May 15 19:20:52 2014
|
||||||
|
|
||||||
|
|
||||||
|
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||||
|
--------- ------ ------- ---- -----------------
|
||||||
|
0 0 1 Pin BERR
|
||||||
|
1 1 1 Pin BERR.OE
|
||||||
|
13 10 1 PinX1 CLK_EXP.X1
|
||||||
|
1 4 1 PinX2 CLK_EXP.X2
|
||||||
|
1 0 1 Pin AVEC
|
||||||
|
0 0 1 Pin AVEC_EXP
|
||||||
|
1 1 1 Pin AVEC_EXP.OE
|
||||||
|
1 0 1 Pin DSACK_0_
|
||||||
|
1 1 1 Pin DSACK_0_.OE
|
||||||
|
0 0 1 Pin AMIGA_BUS_ENABLE
|
||||||
|
1 1 1 Pin AMIGA_BUS_DATA_DIR
|
||||||
|
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
|
||||||
|
1 4 1 Pin CIIN
|
||||||
|
1 8 1 Pin CIIN.OE
|
||||||
|
2 3 1 Pin IPL_030_2_.D
|
||||||
|
1 1 1 Pin IPL_030_2_.AP
|
||||||
|
1 1 1 Pin IPL_030_2_.C
|
||||||
|
1 1 1 Pin DSACK_1_.OE
|
||||||
|
9 12 1 Pin DSACK_1_.D-
|
||||||
|
1 1 1 Pin DSACK_1_.AP
|
||||||
|
1 1 1 Pin DSACK_1_.C
|
||||||
|
1 1 1 Pin AS_000.OE
|
||||||
|
2 5 1 Pin AS_000.D-
|
||||||
|
1 1 1 Pin AS_000.AP
|
||||||
|
1 1 1 Pin AS_000.C
|
||||||
|
1 1 1 Pin UDS_000.OE
|
||||||
|
11 10 1 Pin UDS_000.D-
|
||||||
|
1 1 1 Pin UDS_000.AP
|
||||||
|
1 1 1 Pin UDS_000.C
|
||||||
|
1 1 1 Pin LDS_000.OE
|
||||||
|
3 6 1 Pin LDS_000.D
|
||||||
|
1 1 1 Pin LDS_000.AP
|
||||||
|
1 1 1 Pin LDS_000.C
|
||||||
|
3 7 1 Pin BG_000.D-
|
||||||
|
1 1 1 Pin BG_000.AP
|
||||||
|
1 1 1 Pin BG_000.C
|
||||||
|
2 3 1 Pin BGACK_030.D
|
||||||
|
1 1 1 Pin BGACK_030.AP
|
||||||
|
1 1 1 Pin BGACK_030.C
|
||||||
|
1 1 1 Pin CLK_DIV_OUT.D
|
||||||
|
1 1 1 Pin CLK_DIV_OUT.C
|
||||||
|
2 10 1 Pin FPU_CS.D-
|
||||||
|
1 1 1 Pin FPU_CS.AP
|
||||||
|
1 1 1 Pin FPU_CS.C
|
||||||
|
1 1 1 Pin DTACK.OE
|
||||||
|
1 2 1 Pin DTACK.D-
|
||||||
|
1 1 1 Pin DTACK.AP
|
||||||
|
1 1 1 Pin DTACK.C
|
||||||
|
2 3 1 Pin IPL_030_1_.D
|
||||||
|
1 1 1 Pin IPL_030_1_.AP
|
||||||
|
1 1 1 Pin IPL_030_1_.C
|
||||||
|
2 3 1 Pin IPL_030_0_.D
|
||||||
|
1 1 1 Pin IPL_030_0_.AP
|
||||||
|
1 1 1 Pin IPL_030_0_.C
|
||||||
|
3 6 1 Pin E.T
|
||||||
|
1 1 1 Pin E.C
|
||||||
|
3 4 1 Pin VMA.D
|
||||||
|
1 1 1 Pin VMA.AP
|
||||||
|
1 1 1 Pin VMA.C
|
||||||
|
1 1 1 Pin RESET.D
|
||||||
|
1 1 1 Pin RESET.C
|
||||||
|
4 6 1 Node cpu_est_1_.T
|
||||||
|
1 1 1 Node cpu_est_1_.C
|
||||||
|
4 11 1 Node inst_AS_030_000_SYNC.D
|
||||||
|
1 1 1 Node inst_AS_030_000_SYNC.AP
|
||||||
|
1 1 1 Node inst_AS_030_000_SYNC.C
|
||||||
|
2 6 1 Node inst_DTACK_SYNC.D-
|
||||||
|
1 1 1 Node inst_DTACK_SYNC.AP
|
||||||
|
1 1 1 Node inst_DTACK_SYNC.C
|
||||||
|
1 1 1 Node inst_VPA_D.D
|
||||||
|
1 1 1 Node inst_VPA_D.C
|
||||||
|
2 9 1 Node inst_VPA_SYNC.D-
|
||||||
|
1 1 1 Node inst_VPA_SYNC.AP
|
||||||
|
1 1 1 Node inst_VPA_SYNC.C
|
||||||
|
1 1 1 Node inst_CLK_000_D.D
|
||||||
|
1 1 1 Node inst_CLK_000_D.C
|
||||||
|
1 1 1 Node inst_CLK_000_DD.D
|
||||||
|
1 1 1 Node inst_CLK_000_DD.C
|
||||||
|
2 2 1 Node inst_CLK_OUT_PRE.D
|
||||||
|
1 1 1 Node inst_CLK_OUT_PRE.C
|
||||||
|
3 3 1 Node cpu_est_0_.D
|
||||||
|
1 1 1 Node cpu_est_0_.C
|
||||||
|
3 6 1 NodeX1 cpu_est_2_.D.X1
|
||||||
|
1 1 1 NodeX2 cpu_est_2_.D.X2
|
||||||
|
1 1 1 Node cpu_est_2_.C
|
||||||
|
1 1 1 Node CLK_CNT_0_.D
|
||||||
|
1 1 1 Node CLK_CNT_0_.C
|
||||||
|
1 1 1 Node SM_AMIGA_6_.AR
|
||||||
|
3 4 1 Node SM_AMIGA_6_.D
|
||||||
|
1 1 1 Node SM_AMIGA_6_.C
|
||||||
|
2 4 1 Node SM_AMIGA_7_.D
|
||||||
|
1 1 1 Node SM_AMIGA_7_.AP
|
||||||
|
1 1 1 Node SM_AMIGA_7_.C
|
||||||
|
1 2 1 Node inst_RISING_CLK_AMIGA.D
|
||||||
|
1 1 1 Node inst_RISING_CLK_AMIGA.C
|
||||||
|
1 1 1 Node SM_AMIGA_4_.AR
|
||||||
|
2 3 1 Node SM_AMIGA_4_.D
|
||||||
|
1 1 1 Node SM_AMIGA_4_.C
|
||||||
|
1 1 1 Node SM_AMIGA_3_.AR
|
||||||
|
3 5 1 Node SM_AMIGA_3_.D
|
||||||
|
1 1 1 Node SM_AMIGA_3_.C
|
||||||
|
1 1 1 Node SM_AMIGA_5_.AR
|
||||||
|
2 4 1 Node SM_AMIGA_5_.D
|
||||||
|
1 1 1 Node SM_AMIGA_5_.C
|
||||||
|
2 3 1 Node CLK_000_CNT_0_.D-
|
||||||
|
1 1 1 Node CLK_000_CNT_0_.C
|
||||||
|
4 4 1 Node CLK_000_CNT_1_.D
|
||||||
|
1 1 1 Node CLK_000_CNT_1_.C
|
||||||
|
5 5 1 Node CLK_000_CNT_2_.D-
|
||||||
|
1 1 1 Node CLK_000_CNT_2_.C
|
||||||
|
4 6 1 Node CLK_000_CNT_3_.T
|
||||||
|
1 1 1 Node CLK_000_CNT_3_.C
|
||||||
|
1 1 1 Node SM_AMIGA_2_.AR
|
||||||
|
3 5 1 Node SM_AMIGA_2_.D
|
||||||
|
1 1 1 Node SM_AMIGA_2_.C
|
||||||
|
1 1 1 Node SM_AMIGA_1_.AR
|
||||||
|
4 10 1 Node SM_AMIGA_1_.D-
|
||||||
|
1 1 1 Node SM_AMIGA_1_.C
|
||||||
|
1 1 1 Node SM_AMIGA_0_.AR
|
||||||
|
4 11 1 Node SM_AMIGA_0_.D
|
||||||
|
1 1 1 Node SM_AMIGA_0_.C
|
||||||
|
2 6 1 Node SM_AMIGA_D_0_.D-
|
||||||
|
1 1 1 Node SM_AMIGA_D_0_.C
|
||||||
|
2 6 1 Node SM_AMIGA_D_1_.D-
|
||||||
|
1 1 1 Node SM_AMIGA_D_1_.C
|
||||||
|
2 6 1 Node SM_AMIGA_D_2_.D-
|
||||||
|
1 1 1 Node SM_AMIGA_D_2_.C
|
||||||
|
4 7 1 Node un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
=========
|
||||||
|
214 P-Term Total: 214
|
||||||
|
Total Pins: 59
|
||||||
|
Total Nodes: 28
|
||||||
|
Average P-Term/Output: 2
|
||||||
|
|
||||||
|
|
||||||
|
Equations:
|
||||||
|
|
||||||
|
BERR = (0);
|
||||||
|
|
||||||
|
BERR.OE = (!FPU_CS.Q);
|
||||||
|
|
||||||
|
CLK_EXP.X1 = (SM_AMIGA_0_.Q
|
||||||
|
# SM_AMIGA_6_.Q & !SM_AMIGA_D_0_.Q
|
||||||
|
# SM_AMIGA_4_.Q & !SM_AMIGA_D_0_.Q
|
||||||
|
# SM_AMIGA_2_.Q & !SM_AMIGA_D_0_.Q
|
||||||
|
# SM_AMIGA_4_.Q & !SM_AMIGA_D_1_.Q
|
||||||
|
# SM_AMIGA_5_.Q & !SM_AMIGA_D_1_.Q
|
||||||
|
# SM_AMIGA_1_.Q & !SM_AMIGA_D_1_.Q
|
||||||
|
# SM_AMIGA_3_.Q & !SM_AMIGA_D_2_.Q
|
||||||
|
# SM_AMIGA_2_.Q & !SM_AMIGA_D_2_.Q
|
||||||
|
# SM_AMIGA_1_.Q & !SM_AMIGA_D_2_.Q
|
||||||
|
# !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q & SM_AMIGA_D_0_.Q
|
||||||
|
# !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_1_.Q
|
||||||
|
# !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_2_.Q);
|
||||||
|
|
||||||
|
CLK_EXP.X2 = (SM_AMIGA_0_.Q & SM_AMIGA_D_0_.Q & SM_AMIGA_D_1_.Q & SM_AMIGA_D_2_.Q);
|
||||||
|
|
||||||
|
AVEC = (1);
|
||||||
|
|
||||||
|
AVEC_EXP = (0);
|
||||||
|
|
||||||
|
AVEC_EXP.OE = (!FPU_CS.Q);
|
||||||
|
|
||||||
|
DSACK_0_ = (1);
|
||||||
|
|
||||||
|
DSACK_0_.OE = (!CPU_SPACE);
|
||||||
|
|
||||||
|
AMIGA_BUS_ENABLE = (0);
|
||||||
|
|
||||||
|
AMIGA_BUS_DATA_DIR = (!RW);
|
||||||
|
|
||||||
|
AMIGA_BUS_ENABLE_LOW = (1);
|
||||||
|
|
||||||
|
CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
|
||||||
|
|
||||||
|
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
|
||||||
|
|
||||||
|
IPL_030_2_.D = (IPL_2_ & inst_RISING_CLK_AMIGA.Q
|
||||||
|
# !inst_RISING_CLK_AMIGA.Q & IPL_030_2_.Q);
|
||||||
|
|
||||||
|
IPL_030_2_.AP = (!RST);
|
||||||
|
|
||||||
|
IPL_030_2_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
DSACK_1_.OE = (!CPU_SPACE);
|
||||||
|
|
||||||
|
!DSACK_1_.D = (!AS_030 & !DSACK_1_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q);
|
||||||
|
|
||||||
|
DSACK_1_.AP = (!RST);
|
||||||
|
|
||||||
|
DSACK_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
AS_000.OE = (BGACK_030.Q);
|
||||||
|
|
||||||
|
!AS_000.D = (!AS_030 & !AS_000.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q);
|
||||||
|
|
||||||
|
AS_000.AP = (!RST);
|
||||||
|
|
||||||
|
AS_000.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
UDS_000.OE = (BGACK_030.Q);
|
||||||
|
|
||||||
|
!UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q
|
||||||
|
# !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q
|
||||||
|
# !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q
|
||||||
|
# !AS_030 & !RW & !UDS_000.Q & SM_AMIGA_5_.Q
|
||||||
|
# !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q & !SM_AMIGA_5_.Q
|
||||||
|
# !AS_030 & !RW & !inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q & !UDS_000.Q
|
||||||
|
# !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q & !SM_AMIGA_5_.Q
|
||||||
|
# !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q & !SM_AMIGA_5_.Q
|
||||||
|
# !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q
|
||||||
|
# !DS_030 & !RW & !A_0_ & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q
|
||||||
|
# !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q);
|
||||||
|
|
||||||
|
UDS_000.AP = (!RST);
|
||||||
|
|
||||||
|
UDS_000.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
LDS_000.OE = (BGACK_030.Q);
|
||||||
|
|
||||||
|
LDS_000.D = (AS_030 & !un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
# LDS_000.Q & !un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
# !SIZE_1_ & SIZE_0_ & !A_0_ & un1_UDS_000_INT_0_sqmuxa_2_0);
|
||||||
|
|
||||||
|
LDS_000.AP = (!RST);
|
||||||
|
|
||||||
|
LDS_000.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q
|
||||||
|
# AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q
|
||||||
|
# AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q);
|
||||||
|
|
||||||
|
BG_000.AP = (!RST);
|
||||||
|
|
||||||
|
BG_000.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
BGACK_030.D = (BGACK_000 & BGACK_030.Q
|
||||||
|
# BGACK_000 & inst_RISING_CLK_AMIGA.Q);
|
||||||
|
|
||||||
|
BGACK_030.AP = (!RST);
|
||||||
|
|
||||||
|
BGACK_030.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q);
|
||||||
|
|
||||||
|
CLK_DIV_OUT.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!FPU_CS.D = (!AS_030 & !CLK_030 & !FPU_CS.Q
|
||||||
|
# FC_1_ & !AS_030 & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_);
|
||||||
|
|
||||||
|
FPU_CS.AP = (!RST);
|
||||||
|
|
||||||
|
FPU_CS.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
DTACK.OE = (!BGACK_030.Q);
|
||||||
|
|
||||||
|
!DTACK.D = (!AS_000.Q & !DSACK_1_.PIN);
|
||||||
|
|
||||||
|
DTACK.AP = (!RST);
|
||||||
|
|
||||||
|
DTACK.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q
|
||||||
|
# !inst_RISING_CLK_AMIGA.Q & IPL_030_1_.Q);
|
||||||
|
|
||||||
|
IPL_030_1_.AP = (!RST);
|
||||||
|
|
||||||
|
IPL_030_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q
|
||||||
|
# !inst_RISING_CLK_AMIGA.Q & IPL_030_0_.Q);
|
||||||
|
|
||||||
|
IPL_030_0_.AP = (!RST);
|
||||||
|
|
||||||
|
IPL_030_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
E.T = (E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q
|
||||||
|
# !E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q
|
||||||
|
# !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q);
|
||||||
|
|
||||||
|
E.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
VMA.D = (VMA.Q & inst_VPA_SYNC.Q
|
||||||
|
# VMA.Q & inst_CLK_000_D.Q
|
||||||
|
# AS_000.Q & inst_CLK_000_D.Q);
|
||||||
|
|
||||||
|
VMA.AP = (!RST);
|
||||||
|
|
||||||
|
VMA.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
RESET.D = (RST);
|
||||||
|
|
||||||
|
RESET.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
cpu_est_1_.T = (E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q
|
||||||
|
# !E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q
|
||||||
|
# !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
|
||||||
|
# E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q);
|
||||||
|
|
||||||
|
cpu_est_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_AS_030_000_SYNC.D = (AS_030
|
||||||
|
# CPU_SPACE & CLK_030
|
||||||
|
# !CLK_030 & inst_AS_030_000_SYNC.Q
|
||||||
|
# FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_);
|
||||||
|
|
||||||
|
inst_AS_030_000_SYNC.AP = (!RST);
|
||||||
|
|
||||||
|
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q
|
||||||
|
# inst_VPA_D.Q & inst_CLK_000_D.Q & SM_AMIGA_3_.Q & !DTACK.PIN);
|
||||||
|
|
||||||
|
inst_DTACK_SYNC.AP = (!RST);
|
||||||
|
|
||||||
|
inst_DTACK_SYNC.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_VPA_D.D = (VPA);
|
||||||
|
|
||||||
|
inst_VPA_D.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q
|
||||||
|
# !E.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
|
||||||
|
|
||||||
|
inst_VPA_SYNC.AP = (!RST);
|
||||||
|
|
||||||
|
inst_VPA_SYNC.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_CLK_000_D.D = (CLK_000);
|
||||||
|
|
||||||
|
inst_CLK_000_D.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_CLK_000_DD.D = (inst_CLK_000_D.Q);
|
||||||
|
|
||||||
|
inst_CLK_000_DD.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q
|
||||||
|
# inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q);
|
||||||
|
|
||||||
|
inst_CLK_OUT_PRE.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
cpu_est_0_.D = (!inst_CLK_000_D.Q & cpu_est_0_.Q
|
||||||
|
# inst_CLK_000_DD.Q & cpu_est_0_.Q
|
||||||
|
# inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q);
|
||||||
|
|
||||||
|
cpu_est_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
cpu_est_2_.D.X1 = (E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q
|
||||||
|
# !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q
|
||||||
|
# !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q);
|
||||||
|
|
||||||
|
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
|
||||||
|
|
||||||
|
cpu_est_2_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
CLK_CNT_0_.D = (!CLK_CNT_0_.Q);
|
||||||
|
|
||||||
|
CLK_CNT_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_6_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_6_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q
|
||||||
|
# !inst_CLK_000_D.Q & SM_AMIGA_6_.Q
|
||||||
|
# !inst_CLK_000_D.Q & SM_AMIGA_7_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_6_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_7_.D = (inst_CLK_000_D.Q & SM_AMIGA_7_.Q
|
||||||
|
# AS_000.Q & inst_CLK_000_D.Q & SM_AMIGA_0_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_7_.AP = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_7_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
inst_RISING_CLK_AMIGA.D = (CLK_000 & !inst_CLK_000_D.Q);
|
||||||
|
|
||||||
|
inst_RISING_CLK_AMIGA.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_4_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_4_.D = (!inst_CLK_000_D.Q & SM_AMIGA_4_.Q
|
||||||
|
# !inst_CLK_000_D.Q & SM_AMIGA_5_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_4_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_3_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_3_.D = (inst_CLK_000_D.Q & SM_AMIGA_4_.Q
|
||||||
|
# inst_CLK_000_D.Q & SM_AMIGA_3_.Q
|
||||||
|
# inst_DTACK_SYNC.Q & inst_VPA_SYNC.Q & SM_AMIGA_3_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_3_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_5_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_5_.D = (inst_CLK_000_D.Q & SM_AMIGA_5_.Q
|
||||||
|
# !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_5_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!CLK_000_CNT_0_.D = (CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q
|
||||||
|
# !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q);
|
||||||
|
|
||||||
|
CLK_000_CNT_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
CLK_000_CNT_1_.D = (CLK_000 & inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q
|
||||||
|
# !CLK_000 & !inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q
|
||||||
|
# CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q
|
||||||
|
# !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q);
|
||||||
|
|
||||||
|
CLK_000_CNT_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!CLK_000_CNT_2_.D = (!CLK_000 & inst_CLK_000_D.Q
|
||||||
|
# CLK_000 & !inst_CLK_000_D.Q
|
||||||
|
# !CLK_000_CNT_0_.Q & !CLK_000_CNT_2_.Q
|
||||||
|
# !CLK_000_CNT_1_.Q & !CLK_000_CNT_2_.Q
|
||||||
|
# CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q);
|
||||||
|
|
||||||
|
CLK_000_CNT_2_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
CLK_000_CNT_3_.T = (!CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_3_.Q
|
||||||
|
# CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_3_.Q
|
||||||
|
# CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q
|
||||||
|
# !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q);
|
||||||
|
|
||||||
|
CLK_000_CNT_3_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_2_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q
|
||||||
|
# !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q
|
||||||
|
# !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_2_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_1_.AR = (!RST);
|
||||||
|
|
||||||
|
!SM_AMIGA_1_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q
|
||||||
|
# !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q
|
||||||
|
# !CLK_000 & !inst_DTACK_SYNC.Q & !SM_AMIGA_2_.Q
|
||||||
|
# !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & !SM_AMIGA_2_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
SM_AMIGA_0_.AR = (!RST);
|
||||||
|
|
||||||
|
SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q
|
||||||
|
# !inst_CLK_000_D.Q & SM_AMIGA_0_.Q
|
||||||
|
# !CLK_000 & !inst_DTACK_SYNC.Q & SM_AMIGA_1_.Q
|
||||||
|
# !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_1_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!SM_AMIGA_D_0_.D = (!RST & !SM_AMIGA_D_0_.Q
|
||||||
|
# RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_0_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_D_0_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!SM_AMIGA_D_1_.D = (!RST & !SM_AMIGA_D_1_.Q
|
||||||
|
# RST & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_D_1_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
!SM_AMIGA_D_2_.D = (!RST & !SM_AMIGA_D_2_.Q
|
||||||
|
# RST & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
|
||||||
|
|
||||||
|
SM_AMIGA_D_2_.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0 = (!DS_030 & RW & SM_AMIGA_5_.Q
|
||||||
|
# !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q
|
||||||
|
# !DS_030 & !RW & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q
|
||||||
|
# !DS_030 & !RW & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q);
|
||||||
|
|
||||||
|
|
||||||
|
Reverse-Polarity Equations:
|
||||||
|
|
|
@ -0,0 +1,345 @@
|
||||||
|
#PLAFILE 68030_tk.tt4
|
||||||
|
#DATE 05/15/2014
|
||||||
|
#DESIGN <no design name>
|
||||||
|
#DEVICE mach447a
|
||||||
|
|
||||||
|
DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT
|
||||||
|
DATA LOCATION AMIGA_BUS_ENABLE:D_9_34 // OUT
|
||||||
|
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_12_20 // OUT
|
||||||
|
DATA LOCATION AS_000:D_5_33 // IO {RN_AS_000}
|
||||||
|
DATA LOCATION AS_030:H_*_82 // INP
|
||||||
|
DATA LOCATION AVEC:A_4_92 // OUT
|
||||||
|
DATA LOCATION AVEC_EXP:C_0_22 // OUT
|
||||||
|
DATA LOCATION A_0_:G_*_69 // INP
|
||||||
|
DATA LOCATION A_16_:A_*_96 // INP
|
||||||
|
DATA LOCATION A_17_:F_*_59 // INP
|
||||||
|
DATA LOCATION A_18_:A_*_95 // INP
|
||||||
|
DATA LOCATION A_19_:A_*_97 // INP
|
||||||
|
DATA LOCATION A_20_:A_*_93 // INP
|
||||||
|
DATA LOCATION A_21_:A_*_94 // INP
|
||||||
|
DATA LOCATION A_22_:H_*_85 // INP
|
||||||
|
DATA LOCATION A_23_:H_*_84 // INP
|
||||||
|
DATA LOCATION A_24_:C_*_19 // INP
|
||||||
|
DATA LOCATION A_25_:C_*_18 // INP
|
||||||
|
DATA LOCATION A_26_:C_*_17 // INP
|
||||||
|
DATA LOCATION A_27_:C_*_16 // INP
|
||||||
|
DATA LOCATION A_28_:C_*_15 // INP
|
||||||
|
DATA LOCATION A_29_:B_*_6 // INP
|
||||||
|
DATA LOCATION A_30_:B_*_5 // INP
|
||||||
|
DATA LOCATION A_31_:B_*_4 // INP
|
||||||
|
DATA LOCATION BERR:E_4_41 // OUT
|
||||||
|
DATA LOCATION BGACK_000:D_*_28 // INP
|
||||||
|
DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
|
||||||
|
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
|
||||||
|
DATA LOCATION BG_030:C_*_21 // INP
|
||||||
|
DATA LOCATION CIIN:E_12_47 // OUT
|
||||||
|
DATA LOCATION CLK_000:*_*_11 // INP
|
||||||
|
DATA LOCATION CLK_000_CNT_0_:H_5 // NOD
|
||||||
|
DATA LOCATION CLK_000_CNT_1_:G_5 // NOD
|
||||||
|
DATA LOCATION CLK_000_CNT_2_:H_13 // NOD
|
||||||
|
DATA LOCATION CLK_000_CNT_3_:H_2 // NOD
|
||||||
|
DATA LOCATION CLK_030:*_*_64 // INP
|
||||||
|
DATA LOCATION CLK_CNT_0_:G_15 // NOD
|
||||||
|
DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT
|
||||||
|
DATA LOCATION CLK_EXP:B_0_10 // OUT
|
||||||
|
DATA LOCATION CLK_OSZI:*_*_61 // Cin
|
||||||
|
DATA LOCATION CPU_SPACE:*_*_14 // INP
|
||||||
|
DATA LOCATION DSACK_0_:H_12_80 // OUT
|
||||||
|
DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_}
|
||||||
|
DATA LOCATION DS_030:A_*_98 // INP
|
||||||
|
DATA LOCATION DTACK:D_0_30 // IO
|
||||||
|
DATA LOCATION E:G_4_66 // IO {RN_E}
|
||||||
|
DATA LOCATION FC_0_:F_*_57 // INP
|
||||||
|
DATA LOCATION FC_1_:F_*_58 // INP
|
||||||
|
DATA LOCATION FPU_CS:H_0_78 // IO {RN_FPU_CS}
|
||||||
|
DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_}
|
||||||
|
DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_}
|
||||||
|
DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
|
||||||
|
DATA LOCATION IPL_0_:G_*_67 // INP
|
||||||
|
DATA LOCATION IPL_1_:F_*_56 // INP
|
||||||
|
DATA LOCATION IPL_2_:G_*_68 // INP
|
||||||
|
DATA LOCATION LDS_000:D_12_31 // IO {RN_LDS_000}
|
||||||
|
DATA LOCATION RESET:B_5_3 // OUT
|
||||||
|
DATA LOCATION RN_AS_000:D_5 // NOD {AS_000}
|
||||||
|
DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
|
||||||
|
DATA LOCATION RN_BG_000:D_1 // NOD {BG_000}
|
||||||
|
DATA LOCATION RN_DSACK_1_:H_8 // NOD {DSACK_1_}
|
||||||
|
DATA LOCATION RN_E:G_4 // NOD {E}
|
||||||
|
DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS}
|
||||||
|
DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_}
|
||||||
|
DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_}
|
||||||
|
DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_}
|
||||||
|
DATA LOCATION RN_LDS_000:D_12 // NOD {LDS_000}
|
||||||
|
DATA LOCATION RN_UDS_000:D_8 // NOD {UDS_000}
|
||||||
|
DATA LOCATION RN_VMA:D_4 // NOD {VMA}
|
||||||
|
DATA LOCATION RST:*_*_86 // INP
|
||||||
|
DATA LOCATION RW:G_*_71 // INP
|
||||||
|
DATA LOCATION SIZE_0_:G_*_70 // INP
|
||||||
|
DATA LOCATION SIZE_1_:H_*_79 // INP
|
||||||
|
DATA LOCATION SM_AMIGA_0_:G_8 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_1_:G_1 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_2_:G_9 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_3_:G_13 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_4_:D_13 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_5_:D_6 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_6_:D_2 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_7_:G_6 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_D_0_:B_13 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_D_1_:B_9 // NOD
|
||||||
|
DATA LOCATION SM_AMIGA_D_2_:G_2 // NOD
|
||||||
|
DATA LOCATION UDS_000:D_8_32 // IO {RN_UDS_000}
|
||||||
|
DATA LOCATION VMA:D_4_35 // IO {RN_VMA}
|
||||||
|
DATA LOCATION VPA:*_*_36 // INP
|
||||||
|
DATA LOCATION cpu_est_0_:G_11 // NOD
|
||||||
|
DATA LOCATION cpu_est_1_:G_3 // NOD
|
||||||
|
DATA LOCATION cpu_est_2_:G_7 // NOD
|
||||||
|
DATA LOCATION inst_AS_030_000_SYNC:H_1 // NOD
|
||||||
|
DATA LOCATION inst_CLK_000_D:A_0 // NOD
|
||||||
|
DATA LOCATION inst_CLK_000_DD:D_14 // NOD
|
||||||
|
DATA LOCATION inst_CLK_OUT_PRE:G_10 // NOD
|
||||||
|
DATA LOCATION inst_DTACK_SYNC:G_14 // NOD
|
||||||
|
DATA LOCATION inst_RISING_CLK_AMIGA:H_9 // NOD
|
||||||
|
DATA LOCATION inst_VPA_D:B_6 // NOD
|
||||||
|
DATA LOCATION inst_VPA_SYNC:G_12 // NOD
|
||||||
|
DATA LOCATION un1_UDS_000_INT_0_sqmuxa_2_0:D_10 // NOD
|
||||||
|
DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT
|
||||||
|
DATA IO_DIR AMIGA_BUS_ENABLE:OUT
|
||||||
|
DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT
|
||||||
|
DATA IO_DIR AS_000:OUT
|
||||||
|
DATA IO_DIR AS_030:IN
|
||||||
|
DATA IO_DIR AVEC:OUT
|
||||||
|
DATA IO_DIR AVEC_EXP:OUT
|
||||||
|
DATA IO_DIR A_0_:IN
|
||||||
|
DATA IO_DIR A_16_:IN
|
||||||
|
DATA IO_DIR A_17_:IN
|
||||||
|
DATA IO_DIR A_18_:IN
|
||||||
|
DATA IO_DIR A_19_:IN
|
||||||
|
DATA IO_DIR A_20_:IN
|
||||||
|
DATA IO_DIR A_21_:IN
|
||||||
|
DATA IO_DIR A_22_:IN
|
||||||
|
DATA IO_DIR A_23_:IN
|
||||||
|
DATA IO_DIR A_24_:IN
|
||||||
|
DATA IO_DIR A_25_:IN
|
||||||
|
DATA IO_DIR A_26_:IN
|
||||||
|
DATA IO_DIR A_27_:IN
|
||||||
|
DATA IO_DIR A_28_:IN
|
||||||
|
DATA IO_DIR A_29_:IN
|
||||||
|
DATA IO_DIR A_30_:IN
|
||||||
|
DATA IO_DIR A_31_:IN
|
||||||
|
DATA IO_DIR BERR:OUT
|
||||||
|
DATA IO_DIR BGACK_000:IN
|
||||||
|
DATA IO_DIR BGACK_030:OUT
|
||||||
|
DATA IO_DIR BG_000:OUT
|
||||||
|
DATA IO_DIR BG_030:IN
|
||||||
|
DATA IO_DIR CIIN:OUT
|
||||||
|
DATA IO_DIR CLK_000:IN
|
||||||
|
DATA IO_DIR CLK_030:IN
|
||||||
|
DATA IO_DIR CLK_DIV_OUT:OUT
|
||||||
|
DATA IO_DIR CLK_EXP:OUT
|
||||||
|
DATA IO_DIR CLK_OSZI:IN
|
||||||
|
DATA IO_DIR CPU_SPACE:IN
|
||||||
|
DATA IO_DIR DSACK_0_:OUT
|
||||||
|
DATA IO_DIR DSACK_1_:BI
|
||||||
|
DATA IO_DIR DS_030:IN
|
||||||
|
DATA IO_DIR DTACK:BI
|
||||||
|
DATA IO_DIR E:OUT
|
||||||
|
DATA IO_DIR FC_0_:IN
|
||||||
|
DATA IO_DIR FC_1_:IN
|
||||||
|
DATA IO_DIR FPU_CS:OUT
|
||||||
|
DATA IO_DIR IPL_030_0_:OUT
|
||||||
|
DATA IO_DIR IPL_030_1_:OUT
|
||||||
|
DATA IO_DIR IPL_030_2_:OUT
|
||||||
|
DATA IO_DIR IPL_0_:IN
|
||||||
|
DATA IO_DIR IPL_1_:IN
|
||||||
|
DATA IO_DIR IPL_2_:IN
|
||||||
|
DATA IO_DIR LDS_000:OUT
|
||||||
|
DATA IO_DIR RESET:OUT
|
||||||
|
DATA IO_DIR RST:IN
|
||||||
|
DATA IO_DIR RW:IN
|
||||||
|
DATA IO_DIR SIZE_0_:IN
|
||||||
|
DATA IO_DIR SIZE_1_:IN
|
||||||
|
DATA IO_DIR UDS_000:OUT
|
||||||
|
DATA IO_DIR VMA:OUT
|
||||||
|
DATA IO_DIR VPA:IN
|
||||||
|
DATA GLB_CLOCK CLK_OSZI
|
||||||
|
DATA PW_LEVEL A_30_:0
|
||||||
|
DATA SLEW A_30_:0
|
||||||
|
DATA PW_LEVEL A_29_:0
|
||||||
|
DATA SLEW A_29_:0
|
||||||
|
DATA PW_LEVEL SIZE_1_:0
|
||||||
|
DATA SLEW SIZE_1_:0
|
||||||
|
DATA PW_LEVEL A_28_:0
|
||||||
|
DATA SLEW A_28_:0
|
||||||
|
DATA PW_LEVEL A_27_:0
|
||||||
|
DATA SLEW A_27_:0
|
||||||
|
DATA PW_LEVEL A_31_:0
|
||||||
|
DATA SLEW A_31_:0
|
||||||
|
DATA PW_LEVEL A_26_:0
|
||||||
|
DATA SLEW A_26_:0
|
||||||
|
DATA PW_LEVEL A_25_:0
|
||||||
|
DATA SLEW A_25_:0
|
||||||
|
DATA PW_LEVEL A_24_:0
|
||||||
|
DATA SLEW A_24_:0
|
||||||
|
DATA PW_LEVEL A_23_:0
|
||||||
|
DATA SLEW A_23_:0
|
||||||
|
DATA PW_LEVEL IPL_2_:0
|
||||||
|
DATA SLEW IPL_2_:0
|
||||||
|
DATA PW_LEVEL A_22_:0
|
||||||
|
DATA SLEW A_22_:0
|
||||||
|
DATA PW_LEVEL A_21_:0
|
||||||
|
DATA SLEW A_21_:0
|
||||||
|
DATA PW_LEVEL A_20_:0
|
||||||
|
DATA SLEW A_20_:0
|
||||||
|
DATA PW_LEVEL A_19_:0
|
||||||
|
DATA SLEW A_19_:0
|
||||||
|
DATA PW_LEVEL FC_1_:0
|
||||||
|
DATA SLEW FC_1_:0
|
||||||
|
DATA PW_LEVEL A_18_:0
|
||||||
|
DATA SLEW A_18_:0
|
||||||
|
DATA PW_LEVEL AS_030:0
|
||||||
|
DATA SLEW AS_030:0
|
||||||
|
DATA PW_LEVEL A_17_:0
|
||||||
|
DATA SLEW A_17_:0
|
||||||
|
DATA PW_LEVEL A_16_:0
|
||||||
|
DATA SLEW A_16_:0
|
||||||
|
DATA PW_LEVEL DS_030:0
|
||||||
|
DATA SLEW DS_030:0
|
||||||
|
DATA SLEW CPU_SPACE:0
|
||||||
|
DATA PW_LEVEL BERR:0
|
||||||
|
DATA SLEW BERR:0
|
||||||
|
DATA PW_LEVEL BG_030:0
|
||||||
|
DATA SLEW BG_030:0
|
||||||
|
DATA PW_LEVEL BGACK_000:0
|
||||||
|
DATA SLEW BGACK_000:0
|
||||||
|
DATA SLEW CLK_030:0
|
||||||
|
DATA SLEW CLK_000:0
|
||||||
|
DATA SLEW CLK_OSZI:0
|
||||||
|
DATA PW_LEVEL CLK_EXP:0
|
||||||
|
DATA SLEW CLK_EXP:0
|
||||||
|
DATA PW_LEVEL A_0_:0
|
||||||
|
DATA SLEW A_0_:0
|
||||||
|
DATA PW_LEVEL AVEC:0
|
||||||
|
DATA SLEW AVEC:0
|
||||||
|
DATA PW_LEVEL AVEC_EXP:0
|
||||||
|
DATA SLEW AVEC_EXP:0
|
||||||
|
DATA PW_LEVEL IPL_1_:0
|
||||||
|
DATA SLEW IPL_1_:0
|
||||||
|
DATA SLEW VPA:0
|
||||||
|
DATA PW_LEVEL IPL_0_:0
|
||||||
|
DATA SLEW IPL_0_:0
|
||||||
|
DATA PW_LEVEL DSACK_0_:0
|
||||||
|
DATA SLEW DSACK_0_:0
|
||||||
|
DATA SLEW RST:0
|
||||||
|
DATA PW_LEVEL FC_0_:0
|
||||||
|
DATA SLEW FC_0_:0
|
||||||
|
DATA PW_LEVEL RW:0
|
||||||
|
DATA SLEW RW:0
|
||||||
|
DATA PW_LEVEL AMIGA_BUS_ENABLE:0
|
||||||
|
DATA SLEW AMIGA_BUS_ENABLE:0
|
||||||
|
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0
|
||||||
|
DATA SLEW AMIGA_BUS_DATA_DIR:0
|
||||||
|
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0
|
||||||
|
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
|
||||||
|
DATA PW_LEVEL CIIN:0
|
||||||
|
DATA SLEW CIIN:0
|
||||||
|
DATA PW_LEVEL SIZE_0_:0
|
||||||
|
DATA SLEW SIZE_0_:0
|
||||||
|
DATA PW_LEVEL IPL_030_2_:0
|
||||||
|
DATA SLEW IPL_030_2_:0
|
||||||
|
DATA PW_LEVEL DSACK_1_:0
|
||||||
|
DATA SLEW DSACK_1_:0
|
||||||
|
DATA PW_LEVEL AS_000:0
|
||||||
|
DATA SLEW AS_000:0
|
||||||
|
DATA PW_LEVEL UDS_000:0
|
||||||
|
DATA SLEW UDS_000:0
|
||||||
|
DATA PW_LEVEL LDS_000:0
|
||||||
|
DATA SLEW LDS_000:0
|
||||||
|
DATA PW_LEVEL BG_000:0
|
||||||
|
DATA SLEW BG_000:0
|
||||||
|
DATA PW_LEVEL BGACK_030:0
|
||||||
|
DATA SLEW BGACK_030:0
|
||||||
|
DATA PW_LEVEL CLK_DIV_OUT:0
|
||||||
|
DATA SLEW CLK_DIV_OUT:0
|
||||||
|
DATA PW_LEVEL FPU_CS:0
|
||||||
|
DATA SLEW FPU_CS:0
|
||||||
|
DATA PW_LEVEL DTACK:0
|
||||||
|
DATA SLEW DTACK:0
|
||||||
|
DATA PW_LEVEL IPL_030_1_:0
|
||||||
|
DATA SLEW IPL_030_1_:0
|
||||||
|
DATA PW_LEVEL IPL_030_0_:0
|
||||||
|
DATA SLEW IPL_030_0_:0
|
||||||
|
DATA PW_LEVEL E:0
|
||||||
|
DATA SLEW E:0
|
||||||
|
DATA PW_LEVEL VMA:0
|
||||||
|
DATA SLEW VMA:0
|
||||||
|
DATA PW_LEVEL RESET:0
|
||||||
|
DATA SLEW RESET:0
|
||||||
|
DATA PW_LEVEL cpu_est_1_:0
|
||||||
|
DATA SLEW cpu_est_1_:0
|
||||||
|
DATA PW_LEVEL inst_AS_030_000_SYNC:0
|
||||||
|
DATA SLEW inst_AS_030_000_SYNC:0
|
||||||
|
DATA PW_LEVEL inst_DTACK_SYNC:0
|
||||||
|
DATA SLEW inst_DTACK_SYNC:0
|
||||||
|
DATA PW_LEVEL inst_VPA_D:0
|
||||||
|
DATA SLEW inst_VPA_D:0
|
||||||
|
DATA PW_LEVEL inst_VPA_SYNC:0
|
||||||
|
DATA SLEW inst_VPA_SYNC:0
|
||||||
|
DATA PW_LEVEL inst_CLK_000_D:0
|
||||||
|
DATA SLEW inst_CLK_000_D:0
|
||||||
|
DATA PW_LEVEL inst_CLK_000_DD:0
|
||||||
|
DATA SLEW inst_CLK_000_DD:0
|
||||||
|
DATA PW_LEVEL inst_CLK_OUT_PRE:0
|
||||||
|
DATA SLEW inst_CLK_OUT_PRE:0
|
||||||
|
DATA PW_LEVEL cpu_est_0_:0
|
||||||
|
DATA SLEW cpu_est_0_:0
|
||||||
|
DATA PW_LEVEL cpu_est_2_:0
|
||||||
|
DATA SLEW cpu_est_2_:0
|
||||||
|
DATA PW_LEVEL CLK_CNT_0_:0
|
||||||
|
DATA SLEW CLK_CNT_0_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_6_:0
|
||||||
|
DATA SLEW SM_AMIGA_6_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_7_:0
|
||||||
|
DATA SLEW SM_AMIGA_7_:0
|
||||||
|
DATA PW_LEVEL inst_RISING_CLK_AMIGA:0
|
||||||
|
DATA SLEW inst_RISING_CLK_AMIGA:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_4_:0
|
||||||
|
DATA SLEW SM_AMIGA_4_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_3_:0
|
||||||
|
DATA SLEW SM_AMIGA_3_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_5_:0
|
||||||
|
DATA SLEW SM_AMIGA_5_:0
|
||||||
|
DATA PW_LEVEL CLK_000_CNT_0_:0
|
||||||
|
DATA SLEW CLK_000_CNT_0_:0
|
||||||
|
DATA PW_LEVEL CLK_000_CNT_1_:0
|
||||||
|
DATA SLEW CLK_000_CNT_1_:0
|
||||||
|
DATA PW_LEVEL CLK_000_CNT_2_:0
|
||||||
|
DATA SLEW CLK_000_CNT_2_:0
|
||||||
|
DATA PW_LEVEL CLK_000_CNT_3_:0
|
||||||
|
DATA SLEW CLK_000_CNT_3_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_2_:0
|
||||||
|
DATA SLEW SM_AMIGA_2_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_1_:0
|
||||||
|
DATA SLEW SM_AMIGA_1_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_0_:0
|
||||||
|
DATA SLEW SM_AMIGA_0_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_D_0_:0
|
||||||
|
DATA SLEW SM_AMIGA_D_0_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_D_1_:0
|
||||||
|
DATA SLEW SM_AMIGA_D_1_:0
|
||||||
|
DATA PW_LEVEL SM_AMIGA_D_2_:0
|
||||||
|
DATA SLEW SM_AMIGA_D_2_:0
|
||||||
|
DATA PW_LEVEL un1_UDS_000_INT_0_sqmuxa_2_0:0
|
||||||
|
DATA SLEW un1_UDS_000_INT_0_sqmuxa_2_0:0
|
||||||
|
DATA PW_LEVEL RN_IPL_030_2_:0
|
||||||
|
DATA PW_LEVEL RN_DSACK_1_:0
|
||||||
|
DATA PW_LEVEL RN_AS_000:0
|
||||||
|
DATA PW_LEVEL RN_UDS_000:0
|
||||||
|
DATA PW_LEVEL RN_LDS_000:0
|
||||||
|
DATA PW_LEVEL RN_BG_000:0
|
||||||
|
DATA PW_LEVEL RN_BGACK_030:0
|
||||||
|
DATA PW_LEVEL RN_FPU_CS:0
|
||||||
|
DATA PW_LEVEL RN_IPL_030_1_:0
|
||||||
|
DATA PW_LEVEL RN_IPL_030_0_:0
|
||||||
|
DATA PW_LEVEL RN_E:0
|
||||||
|
DATA PW_LEVEL RN_VMA:0
|
||||||
|
END
|
|
@ -0,0 +1,16 @@
|
||||||
|
|
||||||
|
GROUP MACH_SEG_A inst_CLK_000_D AVEC
|
||||||
|
GROUP MACH_SEG_B SM_AMIGA_D_1_ SM_AMIGA_D_0_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_
|
||||||
|
RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ inst_VPA_D RESET CLK_EXP
|
||||||
|
GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW
|
||||||
|
GROUP MACH_SEG_D UDS_000 RN_UDS_000 LDS_000 RN_LDS_000 BG_000 RN_BG_000
|
||||||
|
AS_000 RN_AS_000 VMA RN_VMA SM_AMIGA_6_ SM_AMIGA_5_ SM_AMIGA_4_ DTACK
|
||||||
|
inst_CLK_000_DD un1_UDS_000_INT_0_sqmuxa_2_0 AMIGA_BUS_ENABLE
|
||||||
|
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR
|
||||||
|
GROUP MACH_SEG_G SM_AMIGA_0_ SM_AMIGA_1_ inst_VPA_SYNC inst_DTACK_SYNC
|
||||||
|
SM_AMIGA_D_2_ E RN_E cpu_est_1_ cpu_est_2_ SM_AMIGA_2_ SM_AMIGA_3_
|
||||||
|
SM_AMIGA_7_ CLK_000_CNT_1_ cpu_est_0_ inst_CLK_OUT_PRE CLK_CNT_0_
|
||||||
|
CLK_DIV_OUT
|
||||||
|
GROUP MACH_SEG_H DSACK_1_ RN_DSACK_1_ inst_AS_030_000_SYNC FPU_CS RN_FPU_CS
|
||||||
|
CLK_000_CNT_3_ CLK_000_CNT_2_ BGACK_030 RN_BGACK_030 CLK_000_CNT_0_
|
||||||
|
inst_RISING_CLK_AMIGA DSACK_0_
|
|
@ -0,0 +1,2 @@
|
||||||
|
No pin assignment or valid property.
|
||||||
|
No source constraints were imported.
|
|
@ -0,0 +1 @@
|
||||||
|
<LATTICE_ENCRYPTED_BLIF>3467346{D`00n
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1 @@
|
||||||
|
. BUS68030 68030-68000-bus.vhd c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd
|
|
@ -0,0 +1 @@
|
||||||
|
-ck Min -ce On -ar On -ap On -oe On -split 16 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5
|
|
@ -0,0 +1,210 @@
|
||||||
|
[DEVICE]
|
||||||
|
Family = M4A5;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
EN_Segment = No;
|
||||||
|
Pin_MC_1to1 = No;
|
||||||
|
EN_PinReserve_IO = Yes;
|
||||||
|
EN_PinReserve_BIDIR = Yes;
|
||||||
|
Voltage = 5.0;
|
||||||
|
|
||||||
|
[REVISION]
|
||||||
|
RCS = "$Revision: 1.2 $";
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
SDS_File = m4a5.sds;
|
||||||
|
Design = 68030_tk.tt4;
|
||||||
|
DATE = 5/15/14;
|
||||||
|
TIME = 19:20:57;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
Type = TT2;
|
||||||
|
Pre_Fit_Time = 1;
|
||||||
|
|
||||||
|
[IGNORE ASSIGNMENTS]
|
||||||
|
Pin_Assignments = No;
|
||||||
|
Pin_Keep_Block = No;
|
||||||
|
Pin_Keep_Segment = No;
|
||||||
|
Group_Assignments = No;
|
||||||
|
Macrocell_Assignments = No;
|
||||||
|
Macrocell_Keep_Block = No;
|
||||||
|
Macrocell_Keep_Segment = No;
|
||||||
|
Pin_Reservation = No;
|
||||||
|
Block_Reservation = No;
|
||||||
|
Segment_Reservation = No;
|
||||||
|
Timing_Constraints = No;
|
||||||
|
|
||||||
|
[CLEAR ASSIGNMENTS]
|
||||||
|
Pin_Assignments = No;
|
||||||
|
Pin_Keep_Block = No;
|
||||||
|
Pin_Keep_Segment = No;
|
||||||
|
Group_Assignments = No;
|
||||||
|
Macrocell_Assignments = No;
|
||||||
|
Macrocell_Keep_Block = No;
|
||||||
|
Macrocell_Keep_Segment = No;
|
||||||
|
Pin_Reservation = No;
|
||||||
|
Block_Reservation = No;
|
||||||
|
Segment_Reservation = No;
|
||||||
|
Timing_Constraints = No;
|
||||||
|
|
||||||
|
[BACKANNOTATE ASSIGNMENTS]
|
||||||
|
Pin_Block = No;
|
||||||
|
Pin_Macrocell_Block = No;
|
||||||
|
Routing = No;
|
||||||
|
|
||||||
|
[GLOBAL CONSTRAINTS]
|
||||||
|
Max_PTerm_Split = 16;
|
||||||
|
Max_PTerm_Collapse = 16;
|
||||||
|
Max_Pin_Percent = 100;
|
||||||
|
Max_Macrocell_Percent = 100;
|
||||||
|
Max_GLB_Input_Percent = 100;
|
||||||
|
Max_Seg_In_Percent = 100;
|
||||||
|
Logic_Reduction = Yes;
|
||||||
|
XOR_Synthesis = Yes;
|
||||||
|
DT_Synthesis = Yes;
|
||||||
|
Node_Collapse = Yes;
|
||||||
|
Run_Time = 0;
|
||||||
|
Set_Reset_Dont_Care = No;
|
||||||
|
Clock_Optimize = No;
|
||||||
|
In_Reg_Optimize = Yes;
|
||||||
|
Balanced_Partitioning = Yes;
|
||||||
|
Device_max_fanin = 33;
|
||||||
|
Device_max_pterms = 20;
|
||||||
|
Usercode = 0;
|
||||||
|
Usercode_Format = Hex;
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENTS]
|
||||||
|
Layer = OFF;
|
||||||
|
A_30_ = pin,5,-,B,-;
|
||||||
|
A_29_ = pin,6,-,B,-;
|
||||||
|
SIZE_1_ = pin,79,-,H,-;
|
||||||
|
A_28_ = pin,15,-,C,-;
|
||||||
|
A_27_ = pin,16,-,C,-;
|
||||||
|
A_31_ = pin,4,-,B,-;
|
||||||
|
A_26_ = pin,17,-,C,-;
|
||||||
|
A_25_ = pin,18,-,C,-;
|
||||||
|
A_24_ = pin,19,-,C,-;
|
||||||
|
A_23_ = pin,84,-,H,-;
|
||||||
|
IPL_2_ = pin,68,-,G,-;
|
||||||
|
A_22_ = pin,85,-,H,-;
|
||||||
|
A_21_ = pin,94,-,A,-;
|
||||||
|
A_20_ = pin,93,-,A,-;
|
||||||
|
A_19_ = pin,97,-,A,-;
|
||||||
|
FC_1_ = pin,58,-,F,-;
|
||||||
|
A_18_ = pin,95,-,A,-;
|
||||||
|
AS_030 = pin,82,-,H,-;
|
||||||
|
A_17_ = pin,59,-,F,-;
|
||||||
|
A_16_ = pin,96,-,A,-;
|
||||||
|
DS_030 = pin,98,-,A,-;
|
||||||
|
CPU_SPACE = pin,14,-,-,-;
|
||||||
|
BERR = pin,41,-,E,-;
|
||||||
|
BG_030 = pin,21,-,C,-;
|
||||||
|
BGACK_000 = pin,28,-,D,-;
|
||||||
|
CLK_030 = pin,64,-,-,-;
|
||||||
|
CLK_000 = pin,11,-,-,-;
|
||||||
|
CLK_OSZI = pin,61,-,-,-;
|
||||||
|
CLK_EXP = pin,10,-,B,-;
|
||||||
|
A_0_ = pin,69,-,G,-;
|
||||||
|
AVEC = pin,92,-,A,-;
|
||||||
|
AVEC_EXP = pin,22,-,C,-;
|
||||||
|
IPL_1_ = pin,56,-,F,-;
|
||||||
|
VPA = pin,36,-,-,-;
|
||||||
|
IPL_0_ = pin,67,-,G,-;
|
||||||
|
DSACK_0_ = pin,80,-,H,-;
|
||||||
|
RST = pin,86,-,-,-;
|
||||||
|
FC_0_ = pin,57,-,F,-;
|
||||||
|
RW = pin,71,-,G,-;
|
||||||
|
AMIGA_BUS_ENABLE = pin,34,-,D,-;
|
||||||
|
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||||
|
CIIN = pin,47,-,E,-;
|
||||||
|
SIZE_0_ = pin,70,-,G,-;
|
||||||
|
IPL_030_2_ = pin,9,-,B,-;
|
||||||
|
DSACK_1_ = pin,81,-,H,-;
|
||||||
|
AS_000 = pin,33,-,D,-;
|
||||||
|
UDS_000 = pin,32,-,D,-;
|
||||||
|
LDS_000 = pin,31,-,D,-;
|
||||||
|
BG_000 = pin,29,-,D,-;
|
||||||
|
BGACK_030 = pin,83,-,H,-;
|
||||||
|
CLK_DIV_OUT = pin,65,-,G,-;
|
||||||
|
FPU_CS = pin,78,-,H,-;
|
||||||
|
DTACK = pin,30,-,D,-;
|
||||||
|
IPL_030_1_ = pin,7,-,B,-;
|
||||||
|
IPL_030_0_ = pin,8,-,B,-;
|
||||||
|
E = pin,66,-,G,-;
|
||||||
|
VMA = pin,35,-,D,-;
|
||||||
|
RESET = pin,3,-,B,-;
|
||||||
|
cpu_est_1_ = node,-,-,G,3;
|
||||||
|
inst_AS_030_000_SYNC = node,-,-,H,1;
|
||||||
|
inst_DTACK_SYNC = node,-,-,G,14;
|
||||||
|
inst_VPA_D = node,-,-,B,6;
|
||||||
|
inst_VPA_SYNC = node,-,-,G,12;
|
||||||
|
inst_CLK_000_D = node,-,-,A,0;
|
||||||
|
inst_CLK_000_DD = node,-,-,D,14;
|
||||||
|
inst_CLK_OUT_PRE = node,-,-,G,10;
|
||||||
|
cpu_est_0_ = node,-,-,G,11;
|
||||||
|
cpu_est_2_ = node,-,-,G,7;
|
||||||
|
CLK_CNT_0_ = node,-,-,G,15;
|
||||||
|
SM_AMIGA_6_ = node,-,-,D,2;
|
||||||
|
SM_AMIGA_7_ = node,-,-,G,6;
|
||||||
|
inst_RISING_CLK_AMIGA = node,-,-,H,9;
|
||||||
|
SM_AMIGA_4_ = node,-,-,D,13;
|
||||||
|
SM_AMIGA_3_ = node,-,-,G,13;
|
||||||
|
SM_AMIGA_5_ = node,-,-,D,6;
|
||||||
|
CLK_000_CNT_0_ = node,-,-,H,5;
|
||||||
|
CLK_000_CNT_1_ = node,-,-,G,5;
|
||||||
|
CLK_000_CNT_2_ = node,-,-,H,13;
|
||||||
|
CLK_000_CNT_3_ = node,-,-,H,2;
|
||||||
|
SM_AMIGA_2_ = node,-,-,G,9;
|
||||||
|
SM_AMIGA_1_ = node,-,-,G,1;
|
||||||
|
SM_AMIGA_0_ = node,-,-,G,8;
|
||||||
|
SM_AMIGA_D_0_ = node,-,-,B,13;
|
||||||
|
SM_AMIGA_D_1_ = node,-,-,B,9;
|
||||||
|
SM_AMIGA_D_2_ = node,-,-,G,2;
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0 = node,-,-,D,10;
|
||||||
|
|
||||||
|
[GROUP ASSIGNMENTS]
|
||||||
|
Layer = OFF;
|
||||||
|
|
||||||
|
[RESOURCE RESERVATIONS]
|
||||||
|
Layer = OFF;
|
||||||
|
|
||||||
|
[SLEWRATE]
|
||||||
|
Default = FAST;
|
||||||
|
|
||||||
|
[PULLUP]
|
||||||
|
Default = Up;
|
||||||
|
|
||||||
|
[NETLIST/DELAY FORMAT]
|
||||||
|
Delay_File = SDF;
|
||||||
|
Netlist = VHDL;
|
||||||
|
|
||||||
|
[OSM BYPASS]
|
||||||
|
|
||||||
|
[FITTER REPORT FORMAT]
|
||||||
|
Fitter_Options = Yes;
|
||||||
|
Pinout_Diagram = No;
|
||||||
|
Pinout_Listing = Yes;
|
||||||
|
Detailed_Block_Segment_Summary = Yes;
|
||||||
|
Input_Signal_List = Yes;
|
||||||
|
Output_Signal_List = Yes;
|
||||||
|
Bidir_Signal_List = Yes;
|
||||||
|
Node_Signal_List = Yes;
|
||||||
|
Signal_Fanout_List = Yes;
|
||||||
|
Block_Segment_Fanin_List = Yes;
|
||||||
|
Postfit_Eqn = Yes;
|
||||||
|
Prefit_Eqn = Yes;
|
||||||
|
Page_Break = Yes;
|
||||||
|
|
||||||
|
[POWER]
|
||||||
|
Powerlevel = Low,High;
|
||||||
|
Default = High;
|
||||||
|
Type = GLB;
|
||||||
|
|
||||||
|
[SOURCE CONSTRAINT OPTION]
|
||||||
|
|
||||||
|
[TIMING ANALYZER]
|
||||||
|
Last_source=;
|
||||||
|
Last_source_type=Fmax;
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,115 @@
|
||||||
|
|--------------------------------------------|
|
||||||
|
|- ispLEVER Fitter Report File -|
|
||||||
|
|- Version 1.7.00.05.28.13 -|
|
||||||
|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|
||||||
|
|--------------------------------------------|
|
||||||
|
|
||||||
|
|
||||||
|
; Source file 68030_tk.tt4
|
||||||
|
; FITTER-generated Placements.
|
||||||
|
; DEVICE mach447a
|
||||||
|
; DATE Thu May 15 19:20:57 2014
|
||||||
|
|
||||||
|
|
||||||
|
Pin 5 A_30_
|
||||||
|
Pin 6 A_29_
|
||||||
|
Pin 79 SIZE_1_
|
||||||
|
Pin 15 A_28_
|
||||||
|
Pin 16 A_27_
|
||||||
|
Pin 4 A_31_
|
||||||
|
Pin 17 A_26_
|
||||||
|
Pin 18 A_25_
|
||||||
|
Pin 19 A_24_
|
||||||
|
Pin 84 A_23_
|
||||||
|
Pin 68 IPL_2_
|
||||||
|
Pin 85 A_22_
|
||||||
|
Pin 94 A_21_
|
||||||
|
Pin 93 A_20_
|
||||||
|
Pin 97 A_19_
|
||||||
|
Pin 58 FC_1_
|
||||||
|
Pin 95 A_18_
|
||||||
|
Pin 82 AS_030
|
||||||
|
Pin 59 A_17_
|
||||||
|
Pin 96 A_16_
|
||||||
|
Pin 98 DS_030
|
||||||
|
Pin 14 CPU_SPACE
|
||||||
|
Pin 41 BERR Comb ; S6=1 S9=1 Pair 203
|
||||||
|
Pin 21 BG_030
|
||||||
|
Pin 28 BGACK_000
|
||||||
|
Pin 64 CLK_030
|
||||||
|
Pin 11 CLK_000
|
||||||
|
Pin 61 CLK_OSZI
|
||||||
|
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 125
|
||||||
|
Pin 69 A_0_
|
||||||
|
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||||
|
Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149
|
||||||
|
Pin 56 IPL_1_
|
||||||
|
Pin 36 VPA
|
||||||
|
Pin 67 IPL_0_
|
||||||
|
Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287
|
||||||
|
Pin 86 RST
|
||||||
|
Pin 57 FC_0_
|
||||||
|
Pin 71 RW
|
||||||
|
Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 187
|
||||||
|
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197
|
||||||
|
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167
|
||||||
|
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||||
|
Pin 70 SIZE_0_
|
||||||
|
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
|
||||||
|
Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 281
|
||||||
|
Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181
|
||||||
|
Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 185
|
||||||
|
Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 191
|
||||||
|
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||||
|
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||||
|
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245
|
||||||
|
Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269
|
||||||
|
Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173
|
||||||
|
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143
|
||||||
|
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
|
||||||
|
Pin 66 E Reg ; S6=1 S9=1 Pair 251
|
||||||
|
Pin 35 VMA Reg ; S6=1 S9=1 Pair 179
|
||||||
|
Pin 3 RESET Reg ; S6=1 S9=0 Pair 133
|
||||||
|
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
|
||||||
|
Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1
|
||||||
|
Node 181 RN_AS_000 Reg ; S6=1 S9=1
|
||||||
|
Node 185 RN_UDS_000 Reg ; S6=1 S9=1
|
||||||
|
Node 191 RN_LDS_000 Reg ; S6=1 S9=1
|
||||||
|
Node 175 RN_BG_000 Reg ; S6=1 S9=1
|
||||||
|
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||||
|
Node 269 RN_FPU_CS Reg ; S6=1 S9=1
|
||||||
|
Node 173 RN_DTACK Reg ; S6=1 S9=1
|
||||||
|
Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1
|
||||||
|
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
|
||||||
|
Node 251 RN_E Reg ; S6=1 S9=1
|
||||||
|
Node 179 RN_VMA Reg ; S6=1 S9=1
|
||||||
|
Node 250 cpu_est_1_ Reg ; S6=1 S9=1
|
||||||
|
Node 271 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||||
|
Node 266 inst_DTACK_SYNC Reg ; S6=0 S9=0
|
||||||
|
Node 134 inst_VPA_D Reg ; S6=1 S9=0
|
||||||
|
Node 263 inst_VPA_SYNC Reg ; S6=0 S9=0
|
||||||
|
Node 101 inst_CLK_000_D Reg ; S6=1 S9=1
|
||||||
|
Node 194 inst_CLK_000_DD Reg ; S6=1 S9=0
|
||||||
|
Node 260 inst_CLK_OUT_PRE Reg ; S6=1 S9=1
|
||||||
|
Node 262 cpu_est_0_ Reg ; S6=1 S9=1
|
||||||
|
Node 256 cpu_est_2_ Reg ; S6=1 S9=1
|
||||||
|
Node 268 CLK_CNT_0_ Reg ; S6=1 S9=1
|
||||||
|
Node 176 SM_AMIGA_6_ Reg ; S6=0 S9=1
|
||||||
|
Node 254 SM_AMIGA_7_ Reg ; S6=0 S9=0
|
||||||
|
Node 283 inst_RISING_CLK_AMIGA Reg ; S6=1 S9=0
|
||||||
|
Node 193 SM_AMIGA_4_ Reg ; S6=0 S9=1
|
||||||
|
Node 265 SM_AMIGA_3_ Reg ; S6=1 S9=0
|
||||||
|
Node 182 SM_AMIGA_5_ Reg ; S6=0 S9=1
|
||||||
|
Node 277 CLK_000_CNT_0_ Reg ; S6=1 S9=0
|
||||||
|
Node 253 CLK_000_CNT_1_ Reg ; S6=1 S9=1
|
||||||
|
Node 289 CLK_000_CNT_2_ Reg ; S6=1 S9=0
|
||||||
|
Node 272 CLK_000_CNT_3_ Reg ; S6=1 S9=0
|
||||||
|
Node 259 SM_AMIGA_2_ Reg ; S6=1 S9=0
|
||||||
|
Node 247 SM_AMIGA_1_ Reg ; S6=1 S9=0
|
||||||
|
Node 257 SM_AMIGA_0_ Reg ; S6=1 S9=0
|
||||||
|
Node 145 SM_AMIGA_D_0_ Reg ; S6=1 S9=0
|
||||||
|
Node 139 SM_AMIGA_D_1_ Reg ; S6=1 S9=0
|
||||||
|
Node 248 SM_AMIGA_D_2_ Reg ; S6=1 S9=1
|
||||||
|
Node 188 un1_UDS_000_INT_0_sqmuxa_2_0 Comb ; S6=1 S9=1
|
||||||
|
; Unused Pins & Nodes
|
||||||
|
; -> None Found.
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,3 @@
|
||||||
|
<SYNPROJ_Revision_Control>
|
||||||
|
<RevisionControl_Info/>
|
||||||
|
</SYNPROJ_Revision_Control>
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,2 @@
|
||||||
|
Part Number: M4A5-128/64-10VC
|
||||||
|
Need not generate svf file according to the constraints, exit
|
|
@ -0,0 +1,90 @@
|
||||||
|
|
||||||
|
|
||||||
|
Design Name = 68030_tk.tt4
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
|
||||||
|
*******************
|
||||||
|
* TIMING ANALYSIS *
|
||||||
|
*******************
|
||||||
|
|
||||||
|
Timing Analysis KEY:
|
||||||
|
One unit of delay time is equivalent to one pass
|
||||||
|
through the Central Switch Matrix.
|
||||||
|
.. Delay ( in this column ) not applicable to the indicated signal.
|
||||||
|
TSU, Set-Up Time ( 0 for input-paired signals ),
|
||||||
|
represents the number of switch matrix passes between
|
||||||
|
an input pin and a register setup before clock.
|
||||||
|
TSU is reported on the register.
|
||||||
|
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
|
||||||
|
represents the number of switch matrix passes between
|
||||||
|
a clocked register and an output pin.
|
||||||
|
TCO is reported on the register.
|
||||||
|
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
|
||||||
|
represents the number of switch matrix passes between
|
||||||
|
an input pin and an output pin.
|
||||||
|
TPD is reported on the output pin.
|
||||||
|
TCR, Clocked Output-to-Register Time,
|
||||||
|
represents the number of switch matrix passes between
|
||||||
|
a clocked register and the register it drives ( before clock ).
|
||||||
|
TCR is reported on the driving register.
|
||||||
|
|
||||||
|
TSU TCO TPD TCR
|
||||||
|
#passes #passes #passes #passes
|
||||||
|
SIGNAL NAME min max min max min max min max
|
||||||
|
LDS_000 1 2 0 0 .. .. 1 1
|
||||||
|
RN_LDS_000 1 2 0 0 .. .. 1 1
|
||||||
|
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
|
||||||
|
inst_CLK_000_D 1 1 .. .. .. .. 1 2
|
||||||
|
SM_AMIGA_6_ .. .. 1 1 .. .. 1 2
|
||||||
|
SM_AMIGA_4_ .. .. 1 1 .. .. 1 2
|
||||||
|
SM_AMIGA_5_ .. .. 1 1 .. .. 1 2
|
||||||
|
AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
|
||||||
|
CIIN .. .. .. .. 1 1 .. ..
|
||||||
|
IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||||
|
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||||
|
DSACK_1_ 1 1 0 0 .. .. 1 1
|
||||||
|
RN_DSACK_1_ 1 1 0 0 .. .. 1 1
|
||||||
|
AS_000 1 1 0 0 .. .. 1 1
|
||||||
|
RN_AS_000 1 1 0 0 .. .. 1 1
|
||||||
|
UDS_000 1 1 0 0 .. .. 1 1
|
||||||
|
RN_UDS_000 1 1 0 0 .. .. 1 1
|
||||||
|
BG_000 1 1 0 0 .. .. 1 1
|
||||||
|
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||||
|
BGACK_030 1 1 0 0 .. .. 1 1
|
||||||
|
RN_BGACK_030 1 1 0 0 .. .. 1 1
|
||||||
|
FPU_CS 1 1 0 0 .. .. 1 1
|
||||||
|
RN_FPU_CS 1 1 0 0 .. .. 1 1
|
||||||
|
DTACK 1 1 0 0 .. .. .. ..
|
||||||
|
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||||
|
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||||
|
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||||
|
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||||
|
E .. .. 0 0 .. .. 1 1
|
||||||
|
RN_E .. .. 0 0 .. .. 1 1
|
||||||
|
VMA .. .. 0 0 .. .. 1 1
|
||||||
|
RN_VMA .. .. 0 0 .. .. 1 1
|
||||||
|
RESET 1 1 0 0 .. .. .. ..
|
||||||
|
cpu_est_1_ .. .. .. .. .. .. 1 1
|
||||||
|
inst_DTACK_SYNC 1 1 .. .. .. .. 1 1
|
||||||
|
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||||
|
inst_VPA_SYNC 1 1 .. .. .. .. 1 1
|
||||||
|
inst_CLK_000_DD .. .. .. .. .. .. 1 1
|
||||||
|
inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
|
||||||
|
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||||
|
cpu_est_2_ .. .. .. .. .. .. 1 1
|
||||||
|
CLK_CNT_0_ .. .. .. .. .. .. 1 1
|
||||||
|
SM_AMIGA_7_ .. .. .. .. .. .. 1 1
|
||||||
|
inst_RISING_CLK_AMIGA 1 1 .. .. .. .. 1 1
|
||||||
|
SM_AMIGA_3_ .. .. 1 1 .. .. 1 1
|
||||||
|
CLK_000_CNT_0_ 1 1 .. .. .. .. 1 1
|
||||||
|
CLK_000_CNT_1_ 1 1 .. .. .. .. 1 1
|
||||||
|
CLK_000_CNT_2_ 1 1 .. .. .. .. 1 1
|
||||||
|
CLK_000_CNT_3_ 1 1 .. .. .. .. 1 1
|
||||||
|
SM_AMIGA_2_ .. .. 1 1 .. .. 1 1
|
||||||
|
SM_AMIGA_1_ 1 1 1 1 .. .. 1 1
|
||||||
|
SM_AMIGA_0_ 1 1 1 1 .. .. 1 1
|
||||||
|
SM_AMIGA_D_0_ 1 1 1 1 .. .. .. ..
|
||||||
|
SM_AMIGA_D_1_ 1 1 1 1 .. .. .. ..
|
||||||
|
SM_AMIGA_D_2_ 1 1 1 1 .. .. .. ..
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0 .. .. .. .. 1 1 .. ..
|
|
@ -0,0 +1,387 @@
|
||||||
|
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
#$ DATE Thu May 15 19:20:52 2014
|
||||||
|
#$ MODULE 68030_tk
|
||||||
|
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET
|
||||||
|
#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.type fr
|
||||||
|
.i 77
|
||||||
|
.o 127
|
||||||
|
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN DTACK.PIN
|
||||||
|
.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.C CLK_000_CNT_1_.C CLK_000_CNT_2_.C CLK_000_CNT_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP AS_000.C AS_000.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP CLK_CNT_0_.C inst_RISING_CLK_AMIGA.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D E.T VMA.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D BG_000.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D CLK_000_CNT_0_.D CLK_000_CNT_1_.D CLK_000_CNT_2_.D CLK_000_CNT_3_.T IPL_030_0_.D SM_AMIGA_2_.D IPL_030_1_.D SM_AMIGA_1_.D SM_AMIGA_0_.D IPL_030_2_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D
|
||||||
|
.p 375
|
||||||
|
----------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----11----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---0-----1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1--0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------1----------------------------------------------------------------- ~~~~~~~1~1~1~1~1~11111~1~1~11111111~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
|
||||||
|
-------------0--------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~~~~~1~1~1~~~~~~~~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0-------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-0--------------0000000------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------1111-------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---1----11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------1--------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0-------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------11----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------10--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------1-----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-------------------------------------1-1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------11-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
|
||||||
|
--------------------------------------1------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1---0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0---1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1--1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-------10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-1-----10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1----0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10-00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||||
|
-----------------------------------------1---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
|
||||||
|
-----0--------1--------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------1---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0-----------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----1------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0--------------------------0---------1--1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--1-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
|
||||||
|
--------1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------1-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
|
||||||
|
---------------------------------1----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
|
||||||
|
-----------------------------------------1---------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1-1------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-----------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0---------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~
|
||||||
|
---------------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1---------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
|
||||||
|
------------------------------------------1-1--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------0--0-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
--------------------------------------------00-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
----1------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1--------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1----------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
|
||||||
|
-----0--------1---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------1----------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1--------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------1-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------1--------------------------1------------1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------1------------------------------------0--1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0--------------------------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------1---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0------------------------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------1-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------1----------------------------------1----------------01------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0----------------01------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------110------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------110------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----1--------------------------------------------------------0000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------1---0000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0--------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
|
||||||
|
-------------1----------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~
|
||||||
|
---------------------------------------------1--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
--------------------------------------------------------0----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
|
||||||
|
-------------1------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~
|
||||||
|
----------0-------------------------------0-------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------0--------------------------1-1----0---11------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------1-------------------------------------------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
-------------------------------------0----1-----------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------0--1-----------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1-1---------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1-----0-----------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1------0----------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~
|
||||||
|
----------------------------------------0----------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------------------------------------1----1-----------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-----------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----1----------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------1-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0-------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
|
||||||
|
-------------0---------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||||
|
---------------------------------------------------0------0-------0----1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0----------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
|
||||||
|
----------------------------------------------------------0-0-------0---1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1-------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------1-----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------------1---0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0-----------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
|
||||||
|
-----------------------------------------------------------0------0-0----1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------1-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------------------1-------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------------1----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
0--------------1---------------0------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------1------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
|
||||||
|
----1-----------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1---------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---00-0--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0-01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------0----------------------------------------------------------------- ~~~~~~~0~0~0~0~0~00000~0~0~00000000~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~~~~~0~0~0~~~~~~~~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||||
|
--------------1-------------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------0----------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------0---------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------0--------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------0-------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---10---11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0--------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-----------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------0-0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0-------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-------------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~0~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~
|
||||||
|
----------1-----------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-----------------------------------------0---1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0--1-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------01-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
----------------------------------------1-1-11------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~0~~~~~~0~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~
|
||||||
|
--------------------------------------0------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1--------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1-1--1--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1----------11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0----------01--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-----------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-1---------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1-1--1---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0----------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1--------00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-00-0-----------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------0---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-----0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------0-1------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-00-0-------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----01------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0--------------------------0---------1--0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--0-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||||
|
--------------------------------0-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||||
|
---------------------------------0----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||||
|
-----------------------------------0--------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0---------------------------------------0---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0---0-1--11---------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------0----------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0---------------------------------------0-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
--------------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
--------------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------1--------------------------1------------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----------------------------------------0--------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------1------------------------------------0--0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------0---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------0-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------0-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------11-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------0-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
----------0-------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
------------------------------------------1-1---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||||
|
----------0--------------------------1-1----0---11----------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
-----------------------------------------------------------0------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||||
|
--------------------------------------------------------0----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||||
|
----------------------------------------1----1----------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------------------------------0-0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
-----------------------------------------00--0-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-------------------------------------0----1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------0--1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1-1------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1-----0--------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1------0-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-----------------------------------------------------0---------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------0------0-------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
|
||||||
|
--------------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-------------1--------------------------------------------0-0-------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||||
|
-------------1---------------------------------------------0------0-00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||||
|
--------------------------------------------------------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||||
|
-----------------------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0---------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
|
||||||
|
------------------------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0----------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||||
|
----------------------------------------------------------11---------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------11--------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1-------1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------1-----1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1----------------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1---------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1-10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------011-----0--0-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------0-------0-10-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1------010-------00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------0-0-----1-00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------010-----0-00-001--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0-----------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||||
|
----------------------------------------------------------10------0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------01-----0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------001-----0-00-010--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1------000-----0-00-100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------000-----0-00-000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
1-------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------0----------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------1------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0--------------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------0----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------1-1-------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
.end
|
|
@ -0,0 +1,387 @@
|
||||||
|
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
#$ DATE Thu May 15 19:20:52 2014
|
||||||
|
#$ MODULE 68030_tk
|
||||||
|
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET
|
||||||
|
#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.type fr
|
||||||
|
.i 77
|
||||||
|
.o 127
|
||||||
|
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN DTACK.PIN
|
||||||
|
.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.C CLK_000_CNT_1_.C CLK_000_CNT_2_.C CLK_000_CNT_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP AS_000.C AS_000.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP CLK_CNT_0_.C inst_RISING_CLK_AMIGA.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D E.T VMA.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D BG_000.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D CLK_000_CNT_0_.D CLK_000_CNT_1_.D CLK_000_CNT_2_.D CLK_000_CNT_3_.T IPL_030_0_.D SM_AMIGA_2_.D IPL_030_1_.D SM_AMIGA_1_.D SM_AMIGA_0_.D IPL_030_2_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D
|
||||||
|
.p 375
|
||||||
|
----------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----11----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---0-----1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1--0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------1----------------------------------------------------------------- ~~~~~~~1~1~1~1~1~11111~1~1~11111111~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
|
||||||
|
-------------0--------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~~~~~1~1~1~~~~~~~~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0-------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-0--------------0000000------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------1111-------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---1----11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------1--------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0-------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------11----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------10--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------1-----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-------------------------------------1-1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------11-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
|
||||||
|
--------------------------------------1------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1---0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0---1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1--1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-------10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-1-----10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1--------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1----0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10-00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||||
|
-----------------------------------------1---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
|
||||||
|
-----0--------1--------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------1---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1----------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------1------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------0-----------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----1------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0--------------------------0---------1--1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--1-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
|
||||||
|
--------1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------1-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
|
||||||
|
---------------------------------1----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
|
||||||
|
-----------------------------------------1---------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1-1------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-----------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0---------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~
|
||||||
|
---------------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1---------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
|
||||||
|
------------------------------------------1-1--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------0--0-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
--------------------------------------------00-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
----1------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------1--------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1----------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
|
||||||
|
-----0--------1---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------1----------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1--------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------1-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1----------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------1--------------------------1------------1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------1------------------------------------0--1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0--------------------------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------1---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0------------------------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------1-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------1----------------------------------1----------------01------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0----------------01------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------110------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------110------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
|
||||||
|
----1--------------------------------------------------------0000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------1---0000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0--------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
|
||||||
|
-------------1----------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~
|
||||||
|
---------------------------------------------1--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
|
||||||
|
--------------------------------------------------------0----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
|
||||||
|
-------------1------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~
|
||||||
|
----------0-------------------------------0-------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------0--------------------------1-1----0---11------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------1-------------------------------------------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
-------------------------------------0----1-----------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------0--1-----------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1-1---------------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1-----0-----------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
------------------------------------------1------0----------------0-1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
|
||||||
|
---------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~
|
||||||
|
----------------------------------------0----------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----------------------------------------1----1-----------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-----------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
|
||||||
|
----1----------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------1-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0-------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
|
||||||
|
-------------0---------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||||
|
---------------------------------------------------0------0-------0----1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0----------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
|
||||||
|
----------------------------------------------------------0-0-------0---1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1-------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------1-----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------------1---0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0-----------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
|
||||||
|
-----------------------------------------------------------0------0-0----1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------1-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------------------1-------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------------1----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
0--------------1---------------0------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1---------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------1------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
|
||||||
|
----1-----------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------1---------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---00-0--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0-01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------0----------------------------------------------------------------- ~~~~~~~0~0~0~0~0~00000~0~0~00000000~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1--------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~~~~~0~0~0~~~~~~~~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||||
|
--------------1-------------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------0----------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------0---------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------0--------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------0-------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---10---11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-0--1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0--------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-----------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------0-0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----0-------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0-------------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~0~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~
|
||||||
|
----------1-----------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-----------------------------------------0---1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0--1-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------01-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
----------------------------------------1-1-11------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~0~~~~~~0~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~
|
||||||
|
--------------------------------------0------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0-----10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1--------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1-1--1--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1----------11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0----------01--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------1-----------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-1---------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------1-1--1---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------------0---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------1--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0----------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------1--------00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------1--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------------0--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-00-0-----------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------0---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------1-----0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------0-1------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----1-00-0-------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----01------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0--------------------------0---------1--0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
--0-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||||
|
--------------------------------0-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||||
|
---------------------------------0----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||||
|
-----------------------------------0--------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
--------------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0---------------------------------------0---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------0-0---0-1--11---------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
|
||||||
|
--------------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------1----------------0----------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------0---------------------------------------0-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
--------------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
|
||||||
|
--------------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------1--------------------------1------------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0----------------------------------------0--------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0---------1------------------------------------0--0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------0---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-----0--------0----------------0-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------0-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------11-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
----------1----------------------------------1-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------0----------------------------------0-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------0-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
--------------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||||
|
----------0----------------------------------1------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
----------1----------------------------------0------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||||
|
--------------------------------------------------------0--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||||
|
---------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
----------0-------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
------------------------------------------1-1---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||||
|
----------0--------------------------1-1----0---11----------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
-----------------------------------------------------------0------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||||
|
--------------------------------------------------------0----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||||
|
----------------------------------------1----1----------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------------------------------0-0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||||
|
-----------------------------------------00--0-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------00--0-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
-----------------------------------------0--00-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------1----------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-------------------------------------0----1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
---------------------------------------0--1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1-1------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1-----0--------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
------------------------------------------1------0-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-----------------------------------------------------0---------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------1-------------------------------------0------0-------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
|
||||||
|
--------------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||||
|
-------------1--------------------------------------------0-0-------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||||
|
-------------1---------------------------------------------0------0-00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||||
|
--------------------------------------------------------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||||
|
-----------------------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0---------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
|
||||||
|
------------------------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0----------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||||
|
----------------------------------------------------------11---------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------11--------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1-------1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------1-----1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1----------------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------1---------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
------------------------------------------------------------------1-10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------011-----0--0-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------0-------0-10-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1------010-------00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------------------------0-0-----1-00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------010-----0-00-001--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------0-----------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||||
|
----------------------------------------------------------10------0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1-------01-----0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------001-----0-00-010--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------1------000-----0-00-100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------------------------------------------0------000-----0-00-000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
1-------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
---------------0----------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------1------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----0--------------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
|
||||||
|
----------------------------------------0----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
|
||||||
|
-------------------------------------------1-1-------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
.end
|
|
@ -0,0 +1,199 @@
|
||||||
|
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
#$ DATE Thu May 15 19:20:52 2014
|
||||||
|
#$ MODULE BUS68030
|
||||||
|
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_
|
||||||
|
A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR
|
||||||
|
BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA
|
||||||
|
IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR
|
||||||
|
AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000
|
||||||
|
BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET
|
||||||
|
#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D
|
||||||
|
inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_
|
||||||
|
cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_
|
||||||
|
SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_
|
||||||
|
CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_
|
||||||
|
SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.type f
|
||||||
|
.i 77
|
||||||
|
.o 128
|
||||||
|
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030
|
||||||
|
CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
|
||||||
|
A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
|
||||||
|
BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q
|
||||||
|
inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q
|
||||||
|
inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q
|
||||||
|
SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q
|
||||||
|
DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q
|
||||||
|
CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q
|
||||||
|
IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q
|
||||||
|
SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN
|
||||||
|
DTACK.PIN
|
||||||
|
.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_
|
||||||
|
DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN
|
||||||
|
CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C
|
||||||
|
DSACK_1_.AP DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D%
|
||||||
|
UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE
|
||||||
|
BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_DIV_OUT.D
|
||||||
|
CLK_DIV_OUT.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE
|
||||||
|
IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP
|
||||||
|
E.T E.C VMA.D VMA.C VMA.AP RESET.D RESET.C cpu_est_1_.T cpu_est_1_.C
|
||||||
|
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP
|
||||||
|
inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D
|
||||||
|
inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D
|
||||||
|
inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D
|
||||||
|
inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
|
||||||
|
cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
|
||||||
|
SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP
|
||||||
|
inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_4_.D SM_AMIGA_4_.C
|
||||||
|
SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D
|
||||||
|
SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D% CLK_000_CNT_0_.C CLK_000_CNT_1_.D
|
||||||
|
CLK_000_CNT_1_.C CLK_000_CNT_2_.D% CLK_000_CNT_2_.C CLK_000_CNT_3_.T
|
||||||
|
CLK_000_CNT_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D%
|
||||||
|
SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR
|
||||||
|
SM_AMIGA_D_0_.D% SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D% SM_AMIGA_D_1_.C
|
||||||
|
SM_AMIGA_D_2_.D% SM_AMIGA_D_2_.C un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||||
|
.p 142
|
||||||
|
----------------------------------------------------------------------------- 00001001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------0---------------------------------------- 01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------------------------1------- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------0------0-------0----1----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------1-------------------0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------1------------0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------------1----0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------0-0-------0---1---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------1-------------0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------1-----------0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------------------1---0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------------------0------0-0----1--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------------------1-------------0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------------1------0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------------------1----0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------------------------1-111--- 00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------0---------------------------------------------------------------------- 00000000100000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------0-------------------------------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------1111-------------------------------------------------- 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-0--------------0000000------------------------------------------------------ 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--1-----------------------------------------------------1-------------------- 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0-------------1------ 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------1----------------------------------------------------------------- 00000000000000010010001000100010001001001010010001001001010010101001001010010101010010101001001010010010010101010100100100101010
|
||||||
|
-------------0--------------------------------------------------------------- 00000000000000001001000100010001000100100001001000100100001000000100100001000000000000000100100001001001000000000010010010000000
|
||||||
|
----0----------------------------------------------------0------------------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1-------------1-------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1-------------1-------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1--------------1------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1--------------1------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1---------------1-----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1---------------1-----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1----------------1----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1----------------1----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0-----------------------------------0------------------------------------ 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0---1-----1------------------------- 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||||
|
-----------------------------------1----------------------------------------- 00000000000000000000000010001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------1----------------0---------0---1-----1------------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----01------------------------------------------------0---------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0--------------------------0---------1--0---------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0---------------------------------------0---0------------------ 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------1----------------0----------------------------1---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0---------------------------------------0-----1---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------1--------------------------1------------0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0----------------------------------------0--------0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------1------------------------------------0--0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------0----------------0---------1---1------------1-0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------0----------------0-------------1-----0------1-0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
0--------------1---------------0------------------------------------------1-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1---------------------------------------------------------------------0-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------------------1------------------0-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1-00-0-----------------------------------------1------------------------- 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------0-1------------------------------------------0------------------------ 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1-00-0-------------------------------------------1----------------------- 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------1--------------------------1----------------------------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------1-----------------------------------------------1-------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------1----------------------------- 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---10---11-----------------0010---1------------------------------------------ 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0----0--------------------------0---------------------------------------- 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------0----------------------------------0- 00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------0----------------------------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------1-----------------------1-------------------- 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0----------1--------- 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------1----------------------1-------------------- 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0--------1----------- 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-1-----10-11--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-1-----10-10--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10-00--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------1-----1-------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------1------1------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------1----1------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-0-----10-0---------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-------10-11--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10--0--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-1-----10-10--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1------------------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------1--1------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---1----11-----------------0010---1------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------0-------------------------------1----------------------------------- 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0-------------------------------------0---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------1-1-------------1----------------0 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------1---------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------------------------------------0-------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0---0-1--11---------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||||
|
----------1------------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------0--1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------1--0-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0--1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------1-1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------10-0---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-------10-10--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------0-----10-00--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10-11--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------------1--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------0-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------1---------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0-----1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0-------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------1-------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
|
||||||
|
----------------------------------------1----1-----------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
|
||||||
|
----------1----------------------------------0------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000010000000000000000000
|
||||||
|
---------------------------------------------0------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||||
|
---------------------------------------------0--------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||||
|
---------------------------------------------1------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
------------------------------------------1-1--------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
---------------------------------------------1-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
---------------------------------------------1--------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||||
|
----------1----------------------------------1---------------1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
|
||||||
|
----------0----------------------------------0---------------1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
|
||||||
|
----------1----------------------------------1---------------01-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------0---------------01-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------1----------------------------------1---------------10-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------0---------------10-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
-------------------------------------------------------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
-------------------------------------------------------------0-0------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
--------------------------------------------------------------00------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
----------1----------------------------------1---------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------0----------------------------------0---------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------0----------------------------------1------------------1------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------1----------------------------------0------------------1------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
------------------------------------------0--0-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||||
|
--------------------------------------------00-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||||
|
---------------------------------------------0--------------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000
|
||||||
|
----------0-------------------------------0-----------------------0---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
----------0--------------------------1-1----0---11----------------0---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
------------------------------------------------------------------0-0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
----------0-------------------------------0-------------------------1-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
----------0--------------------------1-1----0---11------------------1-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
----------------------------------------0----------------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
---------------------------------------------0-----------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
-------------1-------------------------------------0------0-------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||||
|
-------------0---------------------------------------------------------0----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||||
|
-------------1--------------------------------------------0-0-------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||||
|
-------------0----------------------------------------------------------0---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||||
|
-------------1---------------------------------------------0------0-00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||||
|
-------------0-----------------------------------------------------------0--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||||
|
-----0--------1--------------------------0---1-----1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------1---------------------------------------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------0--------------------------1---1------------1-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------0------------------------------1-----0------1-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
.end
|
|
@ -0,0 +1,199 @@
|
||||||
|
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
#$ DATE Thu May 15 19:20:52 2014
|
||||||
|
#$ MODULE BUS68030
|
||||||
|
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_
|
||||||
|
A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR
|
||||||
|
BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA
|
||||||
|
IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR
|
||||||
|
AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000
|
||||||
|
BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET
|
||||||
|
#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D
|
||||||
|
inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_
|
||||||
|
cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_
|
||||||
|
SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_
|
||||||
|
CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_
|
||||||
|
SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.type f
|
||||||
|
.i 77
|
||||||
|
.o 128
|
||||||
|
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030
|
||||||
|
CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
|
||||||
|
A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
|
||||||
|
BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q
|
||||||
|
inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q
|
||||||
|
inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q
|
||||||
|
SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q
|
||||||
|
DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q
|
||||||
|
CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q
|
||||||
|
IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q
|
||||||
|
SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN
|
||||||
|
DTACK.PIN
|
||||||
|
.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_
|
||||||
|
DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN
|
||||||
|
CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C
|
||||||
|
DSACK_1_.AP DSACK_1_.OE AS_000.D- AS_000.C AS_000.AP AS_000.OE UDS_000.D-
|
||||||
|
UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE
|
||||||
|
BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_DIV_OUT.D
|
||||||
|
CLK_DIV_OUT.C FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE
|
||||||
|
IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP
|
||||||
|
E.T E.C VMA.D VMA.C VMA.AP RESET.D RESET.C cpu_est_1_.T cpu_est_1_.C
|
||||||
|
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP
|
||||||
|
inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D
|
||||||
|
inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D
|
||||||
|
inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D
|
||||||
|
inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
|
||||||
|
cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
|
||||||
|
SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP
|
||||||
|
inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_4_.D SM_AMIGA_4_.C
|
||||||
|
SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D
|
||||||
|
SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D- CLK_000_CNT_0_.C CLK_000_CNT_1_.D
|
||||||
|
CLK_000_CNT_1_.C CLK_000_CNT_2_.D- CLK_000_CNT_2_.C CLK_000_CNT_3_.T
|
||||||
|
CLK_000_CNT_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D-
|
||||||
|
SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR
|
||||||
|
SM_AMIGA_D_0_.D- SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D- SM_AMIGA_D_1_.C
|
||||||
|
SM_AMIGA_D_2_.D- SM_AMIGA_D_2_.C un1_UDS_000_INT_0_sqmuxa_2_0
|
||||||
|
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||||
|
.p 142
|
||||||
|
----------------------------------------------------------------------------- 00001001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------0---------------------------------------- 01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------------------------1------- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------0------0-------0----1----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------1-------------------0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------1------------0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------------1----0----- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------0-0-------0---1---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------------------1-------------0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------1-----------0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------------------1---0---- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------------------0------0-0----1--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------------------1-------------0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------------------------------------------------------------1------0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------------------1----0--- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------------------------------1-111--- 00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------0---------------------------------------------------------------------- 00000000100000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------0-------------------------------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------1111-------------------------------------------------- 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-0--------------0000000------------------------------------------------------ 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--1-----------------------------------------------------1-------------------- 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0-------------1------ 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------1----------------------------------------------------------------- 00000000000000010010001000100010001001001010010001001001010010101001001010010101010010101001001010010010010101010100100100101010
|
||||||
|
-------------0--------------------------------------------------------------- 00000000000000001001000100010001000100100001001000100100001000000100100001000000000000000100100001001001000000000010010010000000
|
||||||
|
----0----------------------------------------------------0------------------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1-------------1-------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1-------------1-------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1--------------1------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1--------------1------1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1---------------1-----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1---------------1-----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------00--0-1----------------1----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0--00-1----------------1----1------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0-----------------------------------0------------------------------------ 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------0---1-----1------------------------- 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||||
|
-----------------------------------1----------------------------------------- 00000000000000000000000010001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------1----------------0---------0---1-----1------------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----01------------------------------------------------0---------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0--------------------------0---------1--0---------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0---------------------------------------0---0------------------ 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------1----------------0----------------------------1---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------0---------------------------------------0-----1---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------1--------------------------1------------0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0----------------------------------------0--------0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------1------------------------------------0--0-----0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------0----------------0---------1---1------------1-0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----0--------0----------------0-------------1-----0------1-0---------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
0--------------1---------------0------------------------------------------1-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1---------------------------------------------------------------------0-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------------------1------------------0-- 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1-00-0-----------------------------------------1------------------------- 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------0-1------------------------------------------0------------------------ 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1-00-0-------------------------------------------1----------------------- 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------1--------------------------1----------------------------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------1-----------------------------------------------1-------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------1----------------------------- 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---10---11-----------------0010---1------------------------------------------ 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0----0--------------------------0---------------------------------------- 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------0----------------------------------0- 00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------0----------------------------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------1-----------------------1-------------------- 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0----------1--------- 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------1----------------------1-------------------- 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------------0--------1----------- 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-1-----10-11--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-1-----10-10--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10-00--------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------1-----1-------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------1------1------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------1----1------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-0-----10-0---------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-------10-11--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10--0--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-1-----10-10--------------------------- 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----1------------------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------1--1------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---1----11-----------------0010---1------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
---------0-------------------------------1----------------------------------- 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0-------------------------------------0---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------1-1-------------1----------------0 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||||
|
------------1---------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||||
|
----0---------------------------------------0-------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0---0-1--11---------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||||
|
----------1------------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------0--1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------------1--0-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0--1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
----------------------------------------------1-1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------10-0---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------1-------10-10--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
---------------------------------------0-----10-00--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------0-0-----10-11--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||||
|
-------------------------------------------------1--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
|
||||||
|
--------------------------------------------------0-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
|
||||||
|
-----------------------------------------1---------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0-----1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------0-------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||||
|
---------------------------------------------1-------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
|
||||||
|
----------------------------------------1----1-----------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
|
||||||
|
----------1----------------------------------0------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000010000000000000000000
|
||||||
|
---------------------------------------------0------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||||
|
---------------------------------------------0--------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||||
|
---------------------------------------------1------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
------------------------------------------1-1--------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
---------------------------------------------1-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
|
||||||
|
---------------------------------------------1--------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||||
|
----------1----------------------------------1---------------1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
|
||||||
|
----------0----------------------------------0---------------1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
|
||||||
|
----------1----------------------------------1---------------01-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------0---------------01-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------1----------------------------------1---------------10-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------0---------------10-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
|
||||||
|
----------0----------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
-------------------------------------------------------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
-------------------------------------------------------------0-0------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
--------------------------------------------------------------00------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
|
||||||
|
----------1----------------------------------1---------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------0----------------------------------0---------------111------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------0----------------------------------1------------------1------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
----------1----------------------------------0------------------1------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
|
||||||
|
------------------------------------------0--0-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||||
|
--------------------------------------------00-------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||||
|
---------------------------------------------0--------------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000
|
||||||
|
----------0-------------------------------0-----------------------0---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
----------0--------------------------1-1----0---11----------------0---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
------------------------------------------------------------------0-0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||||
|
----------0-------------------------------0-------------------------1-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
----------0--------------------------1-1----0---11------------------1-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
----------------------------------------0----------------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
---------------------------------------------0-----------------------1------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||||
|
-------------1-------------------------------------0------0-------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||||
|
-------------0---------------------------------------------------------0----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||||
|
-------------1--------------------------------------------0-0-------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||||
|
-------------0----------------------------------------------------------0---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||||
|
-------------1---------------------------------------------0------0-00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||||
|
-------------0-----------------------------------------------------------0--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||||
|
-----0--------1--------------------------0---1-----1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------1---------------------------------------------1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------0--------------------------1---1------------1-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
-----0--------0------------------------------1-----0------1-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||||
|
.end
|
|
@ -0,0 +1,198 @@
|
||||||
|
[DEVICE]
|
||||||
|
|
||||||
|
Family = M4A5;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
EN_Segment = NO;
|
||||||
|
Pin_MC_1to1 = NO;
|
||||||
|
Voltage = 5.0;
|
||||||
|
|
||||||
|
[REVISION]
|
||||||
|
|
||||||
|
RCS = "$Revision: 1.2 $";
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
SDS_file = m4a5.sds;
|
||||||
|
Design = 68030_tk.tt4;
|
||||||
|
Rev = 0.01;
|
||||||
|
DATE = 5/15/14;
|
||||||
|
TIME = 19:20:57;
|
||||||
|
Type = TT2;
|
||||||
|
Pre_Fit_Time = 1;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
|
||||||
|
[IGNORE ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignments = NO;
|
||||||
|
Pin_Keep_Block = NO;
|
||||||
|
Pin_Keep_Segment = NO;
|
||||||
|
Group_Assignments = NO;
|
||||||
|
Macrocell_Assignments = NO;
|
||||||
|
Macrocell_Keep_Block = NO;
|
||||||
|
Macrocell_Keep_Segment = NO;
|
||||||
|
Pin_Reservation = NO;
|
||||||
|
Timing_Constraints = NO;
|
||||||
|
Block_Reservation = NO;
|
||||||
|
Segment_Reservation = NO;
|
||||||
|
Ignore_Source_Location = NO;
|
||||||
|
Ignore_Source_Optimization = NO;
|
||||||
|
Ignore_Source_Timing = NO;
|
||||||
|
|
||||||
|
[CLEAR ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignments = NO;
|
||||||
|
Pin_Keep_Block = NO;
|
||||||
|
Pin_Keep_Segment = NO;
|
||||||
|
Group_Assignments = NO;
|
||||||
|
Macrocell_Assignments = NO;
|
||||||
|
Macrocell_Keep_Block = NO;
|
||||||
|
Macrocell_Keep_Segment = NO;
|
||||||
|
Pin_Reservation = NO;
|
||||||
|
Timing_Constraints = NO;
|
||||||
|
Block_Reservation = NO;
|
||||||
|
Segment_Reservation = NO;
|
||||||
|
Ignore_Source_Location = NO;
|
||||||
|
Ignore_Source_Optimization = NO;
|
||||||
|
Ignore_Source_Timing = NO;
|
||||||
|
|
||||||
|
[BACKANNOTATE NETLIST]
|
||||||
|
|
||||||
|
Netlist = VHDL;
|
||||||
|
Delay_File = SDF;
|
||||||
|
Generic_VCC = ;
|
||||||
|
Generic_GND = ;
|
||||||
|
|
||||||
|
[BACKANNOTATE ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignment = NO;
|
||||||
|
Pin_Block = NO;
|
||||||
|
Pin_Macrocell_Block = NO;
|
||||||
|
Routing = NO;
|
||||||
|
|
||||||
|
[GLOBAL PROJECT OPTIMIZATION]
|
||||||
|
|
||||||
|
Balanced_Partitioning = YES;
|
||||||
|
Spread_Placement = YES;
|
||||||
|
Max_Pin_Percent = 100;
|
||||||
|
Max_Macrocell_Percent = 100;
|
||||||
|
Max_Inter_Seg_Percent = 100;
|
||||||
|
Max_Seg_In_Percent = 100;
|
||||||
|
Max_Blk_In_Percent = 100;
|
||||||
|
|
||||||
|
[FITTER REPORT FORMAT]
|
||||||
|
|
||||||
|
Fitter_Options = YES;
|
||||||
|
Pinout_Diagram = NO;
|
||||||
|
Pinout_Listing = YES;
|
||||||
|
Detailed_Block_Segment_Summary = YES;
|
||||||
|
Input_Signal_List = YES;
|
||||||
|
Output_Signal_List = YES;
|
||||||
|
Bidir_Signal_List = YES;
|
||||||
|
Node_Signal_List = YES;
|
||||||
|
Signal_Fanout_List = YES;
|
||||||
|
Block_Segment_Fanin_List = YES;
|
||||||
|
Prefit_Eqn = YES;
|
||||||
|
Postfit_Eqn = YES;
|
||||||
|
Page_Break = YES;
|
||||||
|
|
||||||
|
[OPTIMIZATION OPTIONS]
|
||||||
|
|
||||||
|
Logic_Reduction = YES;
|
||||||
|
Max_PTerm_Split = 16;
|
||||||
|
Max_PTerm_Collapse = 16;
|
||||||
|
XOR_Synthesis = YES;
|
||||||
|
Node_Collapse = Yes;
|
||||||
|
DT_Synthesis = Yes;
|
||||||
|
|
||||||
|
[FITTER GLOBAL OPTIONS]
|
||||||
|
|
||||||
|
Run_Time = 0;
|
||||||
|
Set_Reset_Dont_Care = NO;
|
||||||
|
In_Reg_Optimize = YES;
|
||||||
|
Clock_Optimize = NO;
|
||||||
|
Conf_Unused_IOs = OUT_LOW;
|
||||||
|
|
||||||
|
[POWER]
|
||||||
|
Powerlevel = Low, High;
|
||||||
|
Default = High;
|
||||||
|
Type = GLB;
|
||||||
|
|
||||||
|
[HARDWARE DEVICE OPTIONS]
|
||||||
|
Zero_Hold_Time = Yes;
|
||||||
|
Signature_Word = 0;
|
||||||
|
Pull_up = Yes;
|
||||||
|
Out_Slew_Rate = FAST, SLOW, 0;
|
||||||
|
Device_max_fanin = 33;
|
||||||
|
Device_max_pterms = 20;
|
||||||
|
Usercode_Format = Hex;
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENT]
|
||||||
|
|
||||||
|
Layer = OFF
|
||||||
|
DSACK_1_ = BIDIR,81,7,-;
|
||||||
|
DTACK = OUTPUT,30,3,-;
|
||||||
|
CLK_EXP = OUTPUT,10,1,-;
|
||||||
|
UDS_000 = OUTPUT,32,3,-;
|
||||||
|
E = OUTPUT,66,6,-;
|
||||||
|
VMA = OUTPUT,35,3,-;
|
||||||
|
LDS_000 = OUTPUT,31,3,-;
|
||||||
|
BG_000 = OUTPUT,29,3,-;
|
||||||
|
BGACK_030 = OUTPUT,83,7,-;
|
||||||
|
FPU_CS = OUTPUT,78,7,-;
|
||||||
|
AS_000 = OUTPUT,33,3,-;
|
||||||
|
IPL_030_2_ = OUTPUT,9,1,-;
|
||||||
|
IPL_030_0_ = OUTPUT,8,1,-;
|
||||||
|
IPL_030_1_ = OUTPUT,7,1,-;
|
||||||
|
AVEC = OUTPUT,92,0,-;
|
||||||
|
DSACK_0_ = OUTPUT,80,7,-;
|
||||||
|
CLK_DIV_OUT = OUTPUT,65,6,-;
|
||||||
|
AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
|
||||||
|
CIIN = OUTPUT,47,4,-;
|
||||||
|
BERR = OUTPUT,41,4,-;
|
||||||
|
AMIGA_BUS_ENABLE = OUTPUT,34,3,-;
|
||||||
|
AVEC_EXP = OUTPUT,22,2,-;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
|
||||||
|
RESET = OUTPUT,3,1,-;
|
||||||
|
SM_AMIGA_0_ = NODE,*,6,-;
|
||||||
|
RN_FPU_CS = NODE,-1,7,-;
|
||||||
|
SM_AMIGA_4_ = NODE,*,3,-;
|
||||||
|
inst_VPA_SYNC = NODE,*,6,-;
|
||||||
|
inst_CLK_000_D = NODE,*,0,-;
|
||||||
|
SM_AMIGA_1_ = NODE,*,6,-;
|
||||||
|
CLK_000_CNT_1_ = NODE,*,6,-;
|
||||||
|
inst_AS_030_000_SYNC = NODE,*,7,-;
|
||||||
|
SM_AMIGA_2_ = NODE,*,6,-;
|
||||||
|
SM_AMIGA_3_ = NODE,*,6,-;
|
||||||
|
SM_AMIGA_6_ = NODE,*,3,-;
|
||||||
|
RN_BGACK_030 = NODE,-1,7,-;
|
||||||
|
RN_AS_000 = NODE,-1,3,-;
|
||||||
|
SM_AMIGA_D_2_ = NODE,*,6,-;
|
||||||
|
CLK_000_CNT_0_ = NODE,*,7,-;
|
||||||
|
SM_AMIGA_5_ = NODE,*,3,-;
|
||||||
|
SM_AMIGA_7_ = NODE,*,6,-;
|
||||||
|
inst_CLK_OUT_PRE = NODE,*,6,-;
|
||||||
|
inst_DTACK_SYNC = NODE,*,6,-;
|
||||||
|
inst_RISING_CLK_AMIGA = NODE,*,7,-;
|
||||||
|
RN_UDS_000 = NODE,-1,3,-;
|
||||||
|
RN_DSACK_1_ = NODE,-1,7,-;
|
||||||
|
CLK_000_CNT_2_ = NODE,*,7,-;
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0 = NODE,*,3,-;
|
||||||
|
CLK_000_CNT_3_ = NODE,*,7,-;
|
||||||
|
cpu_est_1_ = NODE,*,6,-;
|
||||||
|
RN_VMA = NODE,-1,3,-;
|
||||||
|
RN_E = NODE,-1,6,-;
|
||||||
|
RN_BG_000 = NODE,-1,3,-;
|
||||||
|
RN_LDS_000 = NODE,-1,3,-;
|
||||||
|
cpu_est_2_ = NODE,*,6,-;
|
||||||
|
cpu_est_0_ = NODE,*,6,-;
|
||||||
|
RN_IPL_030_0_ = NODE,-1,1,-;
|
||||||
|
RN_IPL_030_1_ = NODE,-1,1,-;
|
||||||
|
RN_IPL_030_2_ = NODE,-1,1,-;
|
||||||
|
SM_AMIGA_D_1_ = NODE,*,1,-;
|
||||||
|
SM_AMIGA_D_0_ = NODE,*,1,-;
|
||||||
|
CLK_CNT_0_ = NODE,*,6,-;
|
||||||
|
inst_CLK_000_DD = NODE,*,3,-;
|
||||||
|
inst_VPA_D = NODE,*,1,-;
|
||||||
|
CLK_OSZI = INPUT,61,-,-;
|
|
@ -0,0 +1,220 @@
|
||||||
|
[DEVICE]
|
||||||
|
|
||||||
|
Family = M4A5;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
EN_Segment = NO;
|
||||||
|
Pin_MC_1to1 = NO;
|
||||||
|
Voltage = 5.0;
|
||||||
|
|
||||||
|
[REVISION]
|
||||||
|
|
||||||
|
RCS = "$Revision: 1.2 $";
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
SDS_file = m4a5.sds;
|
||||||
|
Design = 68030_tk.tt4;
|
||||||
|
Rev = 0.01;
|
||||||
|
DATE = 5/15/14;
|
||||||
|
TIME = 19:20:57;
|
||||||
|
Type = TT2;
|
||||||
|
Pre_Fit_Time = 1;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
|
||||||
|
[IGNORE ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignments = NO;
|
||||||
|
Pin_Keep_Block = NO;
|
||||||
|
Pin_Keep_Segment = NO;
|
||||||
|
Group_Assignments = NO;
|
||||||
|
Macrocell_Assignments = NO;
|
||||||
|
Macrocell_Keep_Block = NO;
|
||||||
|
Macrocell_Keep_Segment = NO;
|
||||||
|
Pin_Reservation = NO;
|
||||||
|
Timing_Constraints = NO;
|
||||||
|
Block_Reservation = NO;
|
||||||
|
Segment_Reservation = NO;
|
||||||
|
Ignore_Source_Location = NO;
|
||||||
|
Ignore_Source_Optimization = NO;
|
||||||
|
Ignore_Source_Timing = NO;
|
||||||
|
|
||||||
|
[CLEAR ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignments = NO;
|
||||||
|
Pin_Keep_Block = NO;
|
||||||
|
Pin_Keep_Segment = NO;
|
||||||
|
Group_Assignments = NO;
|
||||||
|
Macrocell_Assignments = NO;
|
||||||
|
Macrocell_Keep_Block = NO;
|
||||||
|
Macrocell_Keep_Segment = NO;
|
||||||
|
Pin_Reservation = NO;
|
||||||
|
Timing_Constraints = NO;
|
||||||
|
Block_Reservation = NO;
|
||||||
|
Segment_Reservation = NO;
|
||||||
|
Ignore_Source_Location = NO;
|
||||||
|
Ignore_Source_Optimization = NO;
|
||||||
|
Ignore_Source_Timing = NO;
|
||||||
|
|
||||||
|
[BACKANNOTATE NETLIST]
|
||||||
|
|
||||||
|
Netlist = VHDL;
|
||||||
|
Delay_File = SDF;
|
||||||
|
Generic_VCC = ;
|
||||||
|
Generic_GND = ;
|
||||||
|
|
||||||
|
[BACKANNOTATE ASSIGNMENTS]
|
||||||
|
|
||||||
|
Pin_Assignment = NO;
|
||||||
|
Pin_Block = NO;
|
||||||
|
Pin_Macrocell_Block = NO;
|
||||||
|
Routing = NO;
|
||||||
|
|
||||||
|
[GLOBAL PROJECT OPTIMIZATION]
|
||||||
|
|
||||||
|
Balanced_Partitioning = YES;
|
||||||
|
Spread_Placement = YES;
|
||||||
|
Max_Pin_Percent = 100;
|
||||||
|
Max_Macrocell_Percent = 100;
|
||||||
|
Max_Inter_Seg_Percent = 100;
|
||||||
|
Max_Seg_In_Percent = 100;
|
||||||
|
Max_Blk_In_Percent = 100;
|
||||||
|
|
||||||
|
[FITTER REPORT FORMAT]
|
||||||
|
|
||||||
|
Fitter_Options = YES;
|
||||||
|
Pinout_Diagram = NO;
|
||||||
|
Pinout_Listing = YES;
|
||||||
|
Detailed_Block_Segment_Summary = YES;
|
||||||
|
Input_Signal_List = YES;
|
||||||
|
Output_Signal_List = YES;
|
||||||
|
Bidir_Signal_List = YES;
|
||||||
|
Node_Signal_List = YES;
|
||||||
|
Signal_Fanout_List = YES;
|
||||||
|
Block_Segment_Fanin_List = YES;
|
||||||
|
Prefit_Eqn = YES;
|
||||||
|
Postfit_Eqn = YES;
|
||||||
|
Page_Break = YES;
|
||||||
|
|
||||||
|
[OPTIMIZATION OPTIONS]
|
||||||
|
|
||||||
|
Logic_Reduction = YES;
|
||||||
|
Max_PTerm_Split = 16;
|
||||||
|
Max_PTerm_Collapse = 16;
|
||||||
|
XOR_Synthesis = YES;
|
||||||
|
Node_Collapse = Yes;
|
||||||
|
DT_Synthesis = Yes;
|
||||||
|
|
||||||
|
[FITTER GLOBAL OPTIONS]
|
||||||
|
|
||||||
|
Run_Time = 0;
|
||||||
|
Set_Reset_Dont_Care = NO;
|
||||||
|
In_Reg_Optimize = YES;
|
||||||
|
Clock_Optimize = NO;
|
||||||
|
Conf_Unused_IOs = OUT_LOW;
|
||||||
|
|
||||||
|
[POWER]
|
||||||
|
Powerlevel = Low, High;
|
||||||
|
Default = High;
|
||||||
|
Type = GLB;
|
||||||
|
|
||||||
|
[HARDWARE DEVICE OPTIONS]
|
||||||
|
Zero_Hold_Time = Yes;
|
||||||
|
Signature_Word = 0;
|
||||||
|
Pull_up = Yes;
|
||||||
|
Out_Slew_Rate = FAST, SLOW, 0;
|
||||||
|
Device_max_fanin = 33;
|
||||||
|
Device_max_pterms = 20;
|
||||||
|
Usercode_Format = Hex;
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENT]
|
||||||
|
|
||||||
|
Layer = OFF;
|
||||||
|
A_30_ = INPUT,5, B,-;
|
||||||
|
A_29_ = INPUT,6, B,-;
|
||||||
|
SIZE_1_ = INPUT,79, H,-;
|
||||||
|
A_28_ = INPUT,15, C,-;
|
||||||
|
A_27_ = INPUT,16, C,-;
|
||||||
|
A_31_ = INPUT,4, B,-;
|
||||||
|
A_26_ = INPUT,17, C,-;
|
||||||
|
A_25_ = INPUT,18, C,-;
|
||||||
|
A_24_ = INPUT,19, C,-;
|
||||||
|
A_23_ = INPUT,84, H,-;
|
||||||
|
IPL_2_ = INPUT,68, G,-;
|
||||||
|
A_22_ = INPUT,85, H,-;
|
||||||
|
A_21_ = INPUT,94, A,-;
|
||||||
|
A_20_ = INPUT,93, A,-;
|
||||||
|
A_19_ = INPUT,97, A,-;
|
||||||
|
FC_1_ = INPUT,58, F,-;
|
||||||
|
A_18_ = INPUT,95, A,-;
|
||||||
|
AS_030 = INPUT,82, H,-;
|
||||||
|
A_17_ = INPUT,59, F,-;
|
||||||
|
A_16_ = INPUT,96, A,-;
|
||||||
|
DS_030 = INPUT,98, A,-;
|
||||||
|
CPU_SPACE = INPUT,14,-,-;
|
||||||
|
BERR = OUTPUT,41, E,-;
|
||||||
|
BG_030 = INPUT,21, C,-;
|
||||||
|
BGACK_000 = INPUT,28, D,-;
|
||||||
|
CLK_030 = INPUT,64,-,-;
|
||||||
|
CLK_000 = INPUT,11,-,-;
|
||||||
|
CLK_OSZI = INPUT,61,-,-;
|
||||||
|
CLK_EXP = OUTPUT,10, B,-;
|
||||||
|
A_0_ = INPUT,69, G,-;
|
||||||
|
AVEC = OUTPUT,92, A,-;
|
||||||
|
AVEC_EXP = OUTPUT,22, C,-;
|
||||||
|
IPL_1_ = INPUT,56, F,-;
|
||||||
|
VPA = INPUT,36,-,-;
|
||||||
|
IPL_0_ = INPUT,67, G,-;
|
||||||
|
DSACK_0_ = OUTPUT,80, H,-;
|
||||||
|
RST = INPUT,86,-,-;
|
||||||
|
FC_0_ = INPUT,57, F,-;
|
||||||
|
RW = INPUT,71, G,-;
|
||||||
|
AMIGA_BUS_ENABLE = OUTPUT,34, D,-;
|
||||||
|
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||||
|
CIIN = OUTPUT,47, E,-;
|
||||||
|
SIZE_0_ = INPUT,70, G,-;
|
||||||
|
IPL_030_2_ = OUTPUT,9, B,-;
|
||||||
|
DSACK_1_ = BIDIR,81, H,-;
|
||||||
|
AS_000 = OUTPUT,33, D,-;
|
||||||
|
UDS_000 = OUTPUT,32, D,-;
|
||||||
|
LDS_000 = OUTPUT,31, D,-;
|
||||||
|
BG_000 = OUTPUT,29, D,-;
|
||||||
|
BGACK_030 = OUTPUT,83, H,-;
|
||||||
|
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||||
|
FPU_CS = OUTPUT,78, H,-;
|
||||||
|
DTACK = BIDIR,30, D,-;
|
||||||
|
IPL_030_1_ = OUTPUT,7, B,-;
|
||||||
|
IPL_030_0_ = OUTPUT,8, B,-;
|
||||||
|
E = OUTPUT,66, G,-;
|
||||||
|
VMA = OUTPUT,35, D,-;
|
||||||
|
RESET = OUTPUT,3, B,-;
|
||||||
|
cpu_est_1_ = NODE,3, G,-;
|
||||||
|
inst_AS_030_000_SYNC = NODE,1, H,-;
|
||||||
|
inst_DTACK_SYNC = NODE,14, G,-;
|
||||||
|
inst_VPA_D = NODE,6, B,-;
|
||||||
|
inst_VPA_SYNC = NODE,12, G,-;
|
||||||
|
inst_CLK_000_D = NODE,0, A,-;
|
||||||
|
inst_CLK_000_DD = NODE,14, D,-;
|
||||||
|
inst_CLK_OUT_PRE = NODE,10, G,-;
|
||||||
|
cpu_est_0_ = NODE,11, G,-;
|
||||||
|
cpu_est_2_ = NODE,7, G,-;
|
||||||
|
CLK_CNT_0_ = NODE,15, G,-;
|
||||||
|
SM_AMIGA_6_ = NODE,2, D,-;
|
||||||
|
SM_AMIGA_7_ = NODE,6, G,-;
|
||||||
|
inst_RISING_CLK_AMIGA = NODE,9, H,-;
|
||||||
|
SM_AMIGA_4_ = NODE,13, D,-;
|
||||||
|
SM_AMIGA_3_ = NODE,13, G,-;
|
||||||
|
SM_AMIGA_5_ = NODE,6, D,-;
|
||||||
|
CLK_000_CNT_0_ = NODE,5, H,-;
|
||||||
|
CLK_000_CNT_1_ = NODE,5, G,-;
|
||||||
|
CLK_000_CNT_2_ = NODE,13, H,-;
|
||||||
|
CLK_000_CNT_3_ = NODE,2, H,-;
|
||||||
|
SM_AMIGA_2_ = NODE,9, G,-;
|
||||||
|
SM_AMIGA_1_ = NODE,1, G,-;
|
||||||
|
SM_AMIGA_0_ = NODE,8, G,-;
|
||||||
|
SM_AMIGA_D_0_ = NODE,13, B,-;
|
||||||
|
SM_AMIGA_D_1_ = NODE,9, B,-;
|
||||||
|
SM_AMIGA_D_2_ = NODE,2, G,-;
|
||||||
|
un1_UDS_000_INT_0_sqmuxa_2_0 = NODE,10, D,-;
|
|
@ -0,0 +1,216 @@
|
||||||
|
[DEVICE]
|
||||||
|
Family = M4A5;
|
||||||
|
PartType = M4A5-128/64;
|
||||||
|
Package = 100TQFP;
|
||||||
|
PartNumber = M4A5-128/64-10VC;
|
||||||
|
Speed = -10;
|
||||||
|
Operating_condition = COM;
|
||||||
|
EN_Segment = No;
|
||||||
|
Pin_MC_1to1 = No;
|
||||||
|
EN_PinReserve_IO = Yes;
|
||||||
|
EN_PinReserve_BIDIR = Yes;
|
||||||
|
Voltage = 5.0;
|
||||||
|
|
||||||
|
[REVISION]
|
||||||
|
RCS = "$Revision: 1.2 $";
|
||||||
|
Parent = m4a5.lci;
|
||||||
|
SDS_File = m4a5.sds;
|
||||||
|
DATE = 05/15/2014;
|
||||||
|
TIME = 12:30:11;
|
||||||
|
Source_Format = Pure_VHDL;
|
||||||
|
Type = TT2;
|
||||||
|
Pre_Fit_Time = 1;
|
||||||
|
|
||||||
|
[IGNORE ASSIGNMENTS]
|
||||||
|
Pin_Assignments = No;
|
||||||
|
Pin_Keep_Block = No;
|
||||||
|
Pin_Keep_Segment = No;
|
||||||
|
Group_Assignments = No;
|
||||||
|
Macrocell_Assignments = No;
|
||||||
|
Macrocell_Keep_Block = No;
|
||||||
|
Macrocell_Keep_Segment = No;
|
||||||
|
Pin_Reservation = No;
|
||||||
|
Block_Reservation = No;
|
||||||
|
Segment_Reservation = No;
|
||||||
|
Timing_Constraints = No;
|
||||||
|
|
||||||
|
[CLEAR ASSIGNMENTS]
|
||||||
|
Pin_Assignments = No;
|
||||||
|
Pin_Keep_Block = No;
|
||||||
|
Pin_Keep_Segment = No;
|
||||||
|
Group_Assignments = No;
|
||||||
|
Macrocell_Assignments = No;
|
||||||
|
Macrocell_Keep_Block = No;
|
||||||
|
Macrocell_Keep_Segment = No;
|
||||||
|
Pin_Reservation = No;
|
||||||
|
Block_Reservation = No;
|
||||||
|
Segment_Reservation = No;
|
||||||
|
Timing_Constraints = No;
|
||||||
|
|
||||||
|
[BACKANNOTATE ASSIGNMENTS]
|
||||||
|
Pin_Block = No;
|
||||||
|
Pin_Macrocell_Block = No;
|
||||||
|
Routing = No;
|
||||||
|
|
||||||
|
[GLOBAL PROJECT OPTIMIZATION]
|
||||||
|
Balanced_Partitioning = Yes;
|
||||||
|
Spread_Placement = Yes;
|
||||||
|
Max_Pin_Percent = 100;
|
||||||
|
Max_Macrocell_Percent = 100;
|
||||||
|
Max_Blk_In_Percent = 100;
|
||||||
|
|
||||||
|
[OPTIMIZATION OPTIONS]
|
||||||
|
Logic_Reduction = Yes;
|
||||||
|
Max_PTerm_Split = 16;
|
||||||
|
Max_PTerm_Collapse = 16;
|
||||||
|
XOR_Synthesis = Yes;
|
||||||
|
EN_XOR_Synthesis = Yes;
|
||||||
|
XOR_Gate = Yes;
|
||||||
|
Node_Collapse = Yes;
|
||||||
|
Keep_XOR = Yes;
|
||||||
|
DT_Synthesis = Yes;
|
||||||
|
Clock_PTerm = Min;
|
||||||
|
Reset_PTerm = On;
|
||||||
|
Preset_PTerm = On;
|
||||||
|
Clock_Enable_PTerm = On;
|
||||||
|
Output_Enable_PTerm = On;
|
||||||
|
EN_DT_Synthesis = Yes;
|
||||||
|
Cluster_PTerm = 5;
|
||||||
|
FF_inv = No;
|
||||||
|
EN_Use_CE = No;
|
||||||
|
Use_CE = No;
|
||||||
|
Use_Internal_COM_FB = Yes;
|
||||||
|
EN_use_Internal_COM_FB = Yes;
|
||||||
|
Set_Reset_Swap = No;
|
||||||
|
EN_Set_Reset_Swap = No;
|
||||||
|
Density = No;
|
||||||
|
DeMorgan = Yes;
|
||||||
|
T_FF = Yes;
|
||||||
|
Max_Symbols = 32;
|
||||||
|
|
||||||
|
[FITTER GLOBAL OPTIONS]
|
||||||
|
Run_Time = 0;
|
||||||
|
Set_Reset_Dont_Care = No;
|
||||||
|
EN_Set_Reset_Dont_Care = Yes;
|
||||||
|
In_Reg_Optimize = Yes;
|
||||||
|
EN_In_Reg_Optimize = No;
|
||||||
|
Clock_Optimize = No;
|
||||||
|
Global_Clock_As_Pterm = No;
|
||||||
|
Show_Iterations = No;
|
||||||
|
Routing_Attempts = 2;
|
||||||
|
Conf_Unused_IOs = Out_Low;
|
||||||
|
|
||||||
|
[HARDWARE DEVICE OPTIONS]
|
||||||
|
Zero_Hold_Time = Yes;
|
||||||
|
Signature_Word = 0;
|
||||||
|
Pull_up = Yes;
|
||||||
|
Out_Slew_Rate = FAST,SLOW,0;
|
||||||
|
Device_max_fanin = 33;
|
||||||
|
Device_max_pterms = 20;
|
||||||
|
Usercode_Format = Hex;
|
||||||
|
|
||||||
|
[PIN RESERVATIONS]
|
||||||
|
Layer = OFF;
|
||||||
|
|
||||||
|
[LOCATION ASSIGNMENT]
|
||||||
|
Layer = OFF;
|
||||||
|
AS_030 = input,82,H,-;
|
||||||
|
A_0_ = input,69,G,-;
|
||||||
|
A_16_ = input,96,A,-;
|
||||||
|
A_17_ = input,59,F,-;
|
||||||
|
A_18_ = input,95,A,-;
|
||||||
|
A_19_ = input,97,A,-;
|
||||||
|
BGACK_000 = input,28,D,-;
|
||||||
|
BG_030 = input,21,C,-;
|
||||||
|
CLK_000 = input,11,-,-;
|
||||||
|
CLK_030 = input,64,-,-;
|
||||||
|
CLK_OSZI = input,61,-,-;
|
||||||
|
CPU_SPACE = input,14,-,-;
|
||||||
|
FC_0_ = input,57,F,-;
|
||||||
|
FC_1_ = input,58,F,-;
|
||||||
|
IPL_0_ = input,67,G,-;
|
||||||
|
IPL_1_ = input,56,F,-;
|
||||||
|
IPL_2_ = input,68,G,-;
|
||||||
|
RST = input,86,-,-;
|
||||||
|
RW = input,71,G,-;
|
||||||
|
SIZE_1_ = input,79,H,-;
|
||||||
|
SIZE_0_ = input,70,G,-;
|
||||||
|
VPA = input,36,-,-;
|
||||||
|
AVEC = input,92,A,-;
|
||||||
|
BGACK_030 = input,83,H,-;
|
||||||
|
BG_000 = input,29,D,-;
|
||||||
|
CLK_DIV_OUT = input,65,G,-;
|
||||||
|
CLK_EXP = input,10,B,-;
|
||||||
|
DSACK_0_ = input,80,H,-;
|
||||||
|
E = input,66,G,-;
|
||||||
|
FPU_CS = input,78,H,-;
|
||||||
|
IPL_030_0_ = input,8,B,-;
|
||||||
|
IPL_030_1_ = input,7,B,-;
|
||||||
|
IPL_030_2_ = input,9,B,-;
|
||||||
|
LDS_000 = input,31,D,-;
|
||||||
|
UDS_000 = input,32,D,-;
|
||||||
|
VMA = input,35,D,-;
|
||||||
|
AS_000 = input,33,D,-;
|
||||||
|
DSACK_1_ = input,81,H,-;
|
||||||
|
DTACK = input,30,D,-;
|
||||||
|
RESET = input,3,B,-;
|
||||||
|
AMIGA_BUS_DATA_DIR = input,48,E,-;
|
||||||
|
AMIGA_BUS_ENABLE = input,34,D,-;
|
||||||
|
AMIGA_BUS_ENABLE_LOW = input,20,C,-;
|
||||||
|
CIIN = input,47,E,-;
|
||||||
|
A_20_ = input,93,A,-;
|
||||||
|
A_21_ = input,94,A,-;
|
||||||
|
A_22_ = input,85,H,-;
|
||||||
|
A_23_ = input,84,H,-;
|
||||||
|
A_24_ = input,19,C,-;
|
||||||
|
A_25_ = input,18,C,-;
|
||||||
|
A_26_ = input,17,C,-;
|
||||||
|
A_27_ = input,16,C,-;
|
||||||
|
A_28_ = input,15,C,-;
|
||||||
|
A_29_ = input,6,B,-;
|
||||||
|
A_30_ = input,5,B,-;
|
||||||
|
A_31_ = input,4,B,-;
|
||||||
|
DS_030 = input,98,A,-;
|
||||||
|
AVEC_EXP = input,22,C,-;
|
||||||
|
BERR = input,41,E,-;
|
||||||
|
|
||||||
|
[GROUP ASSIGNMENT]
|
||||||
|
Layer = OFF;
|
||||||
|
|
||||||
|
[SPACE RESERVATIONS]
|
||||||
|
Layer = OFF;
|
||||||
|
|
||||||
|
[BACKANNOTATE NETLIST]
|
||||||
|
Delay_File = SDF;
|
||||||
|
Netlist = VHDL;
|
||||||
|
VCC_GND = Cell;
|
||||||
|
|
||||||
|
[FITTER REPORT FORMAT]
|
||||||
|
Fitter_Options = Yes;
|
||||||
|
Pinout_Diagram = No;
|
||||||
|
Pinout_Listing = Yes;
|
||||||
|
Detailed_Block_Segment_Summary = Yes;
|
||||||
|
Input_Signal_List = Yes;
|
||||||
|
Output_Signal_List = Yes;
|
||||||
|
Bidir_Signal_List = Yes;
|
||||||
|
Node_Signal_List = Yes;
|
||||||
|
Signal_Fanout_List = Yes;
|
||||||
|
Block_Segment_Fanin_List = Yes;
|
||||||
|
Postfit_Eqn = Yes;
|
||||||
|
Page_Break = Yes;
|
||||||
|
|
||||||
|
[POWER]
|
||||||
|
Powerlevel = Low,High;
|
||||||
|
Default = High;
|
||||||
|
Type = GLB;
|
||||||
|
|
||||||
|
[SOURCE CONSTRAINT OPTION]
|
||||||
|
Import_source_constraint = Yes;
|
||||||
|
Disable_warning_message = No;
|
||||||
|
|
||||||
|
[TIMING ANALYZER]
|
||||||
|
Last_source=;
|
||||||
|
Last_source_type=Fmax;
|
||||||
|
|
||||||
|
[INPUT REGISTERS]
|
||||||
|
|
|
@ -0,0 +1,16 @@
|
||||||
|
Signal Name Cross Reference File
|
||||||
|
|
||||||
|
ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
|
||||||
|
Design '68030_tk' created Thu May 15 19:20:52 2014
|
||||||
|
|
||||||
|
|
||||||
|
LEGEND: '>' Functional Block Port Separator
|
||||||
|
'/' Hierarchy Path Separator
|
||||||
|
'@' Automatically Generated Node
|
||||||
|
|
||||||
|
|
||||||
|
Short Name Hierarchical Name
|
||||||
|
---------- -----------------
|
||||||
|
|
||||||
|
*** Shortened names not required for this design. ***
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,976 @@
|
||||||
|
EDIF2BLIF version IspLever 1.0 Linked Equations File
|
||||||
|
Copyright(C), 1992-2013, Lattice Semiconductor Corp.
|
||||||
|
All Rights Reserved.
|
||||||
|
|
||||||
|
Design bus68030 created Thu Apr 24 11:58:27 2014
|
||||||
|
|
||||||
|
|
||||||
|
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||||
|
--------- ------ ------- ---- -----------------
|
||||||
|
1/1 1 1 Pin IPL_030_2_
|
||||||
|
1/1 1 1 Pin DSACK_1_
|
||||||
|
1/1 1 1 Pin DSACK_1_.OE
|
||||||
|
1/1 1 1 Pin AS_000
|
||||||
|
1/1 1 1 Pin AS_000.OE
|
||||||
|
1/1 1 1 Pin UDS_000
|
||||||
|
1/1 1 1 Pin UDS_000.OE
|
||||||
|
1/1 1 1 Pin LDS_000
|
||||||
|
1/1 1 1 Pin LDS_000.OE
|
||||||
|
1/1 1 1 Pin BERR
|
||||||
|
1/1 1 1 Pin BERR.OE
|
||||||
|
1/1 1 1 Pin BG_000
|
||||||
|
1/1 1 1 Pin BGACK_030
|
||||||
|
1/1 1 1 Pin CLK_DIV_OUT
|
||||||
|
1/1 1 1 Pin CLK_EXP
|
||||||
|
1/1 1 1 Pin FPU_CS
|
||||||
|
1/1 1 1 Pin DTACK
|
||||||
|
1/1 1 1 Pin DTACK.OE
|
||||||
|
1/1 1 1 Pin AVEC
|
||||||
|
1/1 1 1 Pin E
|
||||||
|
1/1 1 1 Pin VMA
|
||||||
|
1/1 1 1 Pin IPL_030_1_
|
||||||
|
1/1 1 1 Pin IPL_030_0_
|
||||||
|
1/1 1 1 Pin DSACK_0_
|
||||||
|
1/1 1 1 Pin DSACK_0_.OE
|
||||||
|
1 2 1 Node N_41_1
|
||||||
|
1 2 1 Node N_40_1
|
||||||
|
1 1 1 Node vma_int_0_un3_n
|
||||||
|
1 2 1 Node vma_int_0_un1_n
|
||||||
|
1 2 1 Node vma_int_0_un0_n
|
||||||
|
1 1 1 Node uds_000_int_0_un3_n
|
||||||
|
1 2 1 Node uds_000_int_0_un1_n
|
||||||
|
1 2 1 Node uds_000_int_0_un0_n
|
||||||
|
1 1 1 Node cpu_est_3_reg.D
|
||||||
|
1/1 1 1 Node cpu_est_3_reg.C
|
||||||
|
1 1 1 Node lds_000_int_0_un3_n
|
||||||
|
2 2 1 Node inst_VMA_INTreg.D
|
||||||
|
1/1 1 1 Node inst_VMA_INTreg.C
|
||||||
|
1 2 1 Node lds_000_int_0_un1_n
|
||||||
|
1/1 1 1 Node cpu_est_0_.D
|
||||||
|
1/1 1 1 Node cpu_est_0_.C
|
||||||
|
1 2 1 Node lds_000_int_0_un0_n
|
||||||
|
1 1 1 Node cpu_est_1_.D
|
||||||
|
1/1 1 1 Node cpu_est_1_.C
|
||||||
|
1/1 1 1 Node a_23__n
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_D.D
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_D.AP
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_D.C
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_DD.D
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_DD.AP
|
||||||
|
1/1 1 1 Node inst_AS_000_INT_DD.C
|
||||||
|
1/1 1 1 Node a_22__n
|
||||||
|
1 2 1 Node inst_AS_030_AMIGA_ENABLE.D
|
||||||
|
1/1 1 1 Node inst_AS_030_AMIGA_ENABLE.AP
|
||||||
|
1/1 1 1 Node inst_AS_030_AMIGA_ENABLE.C
|
||||||
|
1 0 1 Node vcc_n_n
|
||||||
|
1/1 1 1 Node a_21__n
|
||||||
|
0 0 1 Node gnd_n_n
|
||||||
|
1 2 1 Node cpu_est_2_.D
|
||||||
|
1/1 1 1 Node cpu_est_2_.C
|
||||||
|
1/1 1 1 Node a_20__n
|
||||||
|
1/1 1 1 Node inst_AS_030_delay.D
|
||||||
|
1/1 1 1 Node inst_AS_030_delay.AP
|
||||||
|
1/1 1 1 Node inst_AS_030_delay.C
|
||||||
|
1 2 1 Node DSACK_INT_1_.D
|
||||||
|
1/1 1 1 Node DSACK_INT_1_.AP
|
||||||
|
1/1 1 1 Node DSACK_INT_1_.C
|
||||||
|
1/1 1 1 Node a_15__n
|
||||||
|
1 1 1 Node un1_as_000_int2
|
||||||
|
1/1 1 1 Node a_14__n
|
||||||
|
1 2 1 Node un22_fpu_cs_int
|
||||||
|
1 1 1 Node inst_AS_000_INT.D
|
||||||
|
1/1 1 1 Node inst_AS_000_INT.AP
|
||||||
|
1/1 1 1 Node inst_AS_000_INT.C
|
||||||
|
1/1 1 1 Node a_13__n
|
||||||
|
1 1 1 Node un1_as_000_int2_1
|
||||||
|
1/1 1 1 Node a_12__n
|
||||||
|
1 2 1 Node UDS_000_INT_1_sqmuxa
|
||||||
|
2 2 1 Node inst_LDS_000_INTreg.D
|
||||||
|
1/1 1 1 Node inst_LDS_000_INTreg.AP
|
||||||
|
1/1 1 1 Node inst_LDS_000_INTreg.C
|
||||||
|
1/1 1 1 Node a_11__n
|
||||||
|
2 2 1 Node inst_UDS_000_INTreg.D
|
||||||
|
1/1 1 1 Node inst_UDS_000_INTreg.AP
|
||||||
|
1/1 1 1 Node inst_UDS_000_INTreg.C
|
||||||
|
1 2 1 Node un1_dtack_int
|
||||||
|
1/1 1 1 Node a_10__n
|
||||||
|
1/1 1 1 Node a_9__n
|
||||||
|
1/1 1 1 Node a_8__n
|
||||||
|
1 1 1 Node un5_lds_logic
|
||||||
|
1/1 1 1 Node a_7__n
|
||||||
|
1 1 1 Node N_11
|
||||||
|
1 1 1 Node N_22
|
||||||
|
1/1 1 1 Node a_6__n
|
||||||
|
1 1 1 Node N_32
|
||||||
|
1 1 1 Node N_33
|
||||||
|
1/1 1 1 Node a_5__n
|
||||||
|
1 2 1 Node N_48
|
||||||
|
1 2 1 Node N_39
|
||||||
|
1/1 1 1 Node a_4__n
|
||||||
|
1 2 1 Node N_40
|
||||||
|
1 2 1 Node N_41
|
||||||
|
1/1 1 1 Node a_3__n
|
||||||
|
1 2 1 Node N_42
|
||||||
|
1 2 1 Node N_43
|
||||||
|
1/1 1 1 Node a_2__n
|
||||||
|
1 2 1 Node N_44
|
||||||
|
1 2 1 Node N_45
|
||||||
|
1/1 1 1 Node a_1__n
|
||||||
|
1 2 1 Node N_46
|
||||||
|
1 2 1 Node N_51
|
||||||
|
1/1 1 1 Node d_31__n
|
||||||
|
1 2 1 Node N_52
|
||||||
|
1 2 1 Node N_53
|
||||||
|
1/1 1 1 Node d_30__n
|
||||||
|
1 2 1 Node N_55
|
||||||
|
1 2 1 Node N_57
|
||||||
|
1/1 1 1 Node d_29__n
|
||||||
|
1 1 1 Node N_69
|
||||||
|
1 1 1 Node un22_fpu_cs_int_i
|
||||||
|
1/1 1 1 Node d_28__n
|
||||||
|
1 1 1 Node AS_000_i
|
||||||
|
1 1 1 Node VPA_i
|
||||||
|
1 1 1 Node cpu_est_i_0__n
|
||||||
|
1 1 1 Node AS_030_i
|
||||||
|
1 1 1 Node cpu_est_i_1__n
|
||||||
|
1 1 1 Node cpu_est_i_2__n
|
||||||
|
1 1 1 Node cpu_est_i_3__n
|
||||||
|
1 1 1 Node VMA_INT_i
|
||||||
|
1 1 1 Node AS_000_INT_DD_i
|
||||||
|
1 1 1 Node DTACK_i
|
||||||
|
1 1 1 Node dsack_i_1__n
|
||||||
|
1 1 1 Node RW_i
|
||||||
|
1 1 1 Node BGACK_000_i
|
||||||
|
1 1 1 Node a_i_18__n
|
||||||
|
1 1 1 Node a_i_19__n
|
||||||
|
1 1 1 Node a_i_16__n
|
||||||
|
1 1 1 Node a_i_30__n
|
||||||
|
1 1 1 Node a_i_31__n
|
||||||
|
1 1 1 Node a_i_28__n
|
||||||
|
1 1 1 Node a_i_29__n
|
||||||
|
1 1 1 Node a_i_26__n
|
||||||
|
1 1 1 Node a_i_27__n
|
||||||
|
1 1 1 Node a_i_24__n
|
||||||
|
1 1 1 Node a_i_25__n
|
||||||
|
1 1 1 Node CLK_030_i
|
||||||
|
1 1 1 Node RST_i
|
||||||
|
1 1 1 Node N_48_i
|
||||||
|
1 1 1 Node CLK_000_i
|
||||||
|
1 1 1 Node un1_dtack_int_i
|
||||||
|
1/1 1 1 Node AS_030_c
|
||||||
|
1/1 1 1 Node AS_000_c
|
||||||
|
1/1 1 1 Node size_c_0__n
|
||||||
|
1/1 1 1 Node size_c_1__n
|
||||||
|
1/1 1 1 Node a_c_0__n
|
||||||
|
1/1 1 1 Node a_c_16__n
|
||||||
|
1/1 1 1 Node a_c_17__n
|
||||||
|
1/1 1 1 Node a_c_18__n
|
||||||
|
1/1 1 1 Node a_c_19__n
|
||||||
|
1/1 1 1 Node a_c_24__n
|
||||||
|
1/1 1 1 Node a_c_25__n
|
||||||
|
1/1 1 1 Node a_c_26__n
|
||||||
|
1/1 1 1 Node a_c_27__n
|
||||||
|
1/1 1 1 Node a_c_28__n
|
||||||
|
1/1 1 1 Node a_c_29__n
|
||||||
|
1/1 1 1 Node a_c_30__n
|
||||||
|
1/1 1 1 Node a_c_31__n
|
||||||
|
1/1 1 1 Node CPU_SPACE_c
|
||||||
|
1 1 1 Node BG_000DFFSHreg.D
|
||||||
|
1/1 1 1 Node BG_000DFFSHreg.AP
|
||||||
|
1/1 1 1 Node BG_000DFFSHreg.C
|
||||||
|
1/1 1 1 Node BGACK_000_c
|
||||||
|
1/1 1 1 Node CLK_030_c
|
||||||
|
1/1 1 1 Node CLK_000_c
|
||||||
|
1 1 1 Node CLK_OUT_INTreg.D
|
||||||
|
1/1 1 1 Node CLK_OUT_INTreg.C
|
||||||
|
1/1 1 1 Node IPL_030DFF_0_reg.D
|
||||||
|
1/1 1 1 Node IPL_030DFF_0_reg.C
|
||||||
|
1/1 1 1 Node IPL_030DFF_1_reg.D
|
||||||
|
1/1 1 1 Node IPL_030DFF_1_reg.C
|
||||||
|
1/1 1 1 Node IPL_030DFF_2_reg.D
|
||||||
|
1/1 1 1 Node IPL_030DFF_2_reg.C
|
||||||
|
1/1 1 1 Node dsack_c_1__n
|
||||||
|
1/1 1 1 Node DTACK_c
|
||||||
|
1/1 1 1 Node VPA_c
|
||||||
|
1/1 1 1 Node RST_c
|
||||||
|
1/1 1 1 Node RW_c
|
||||||
|
1/1 1 1 Node fc_c_0__n
|
||||||
|
1/1 1 1 Node fc_c_1__n
|
||||||
|
1 2 1 Node N_70
|
||||||
|
1 2 1 Node cpu_est_11_0_1__n
|
||||||
|
1 1 1 Node N_46_i
|
||||||
|
1 1 1 Node N_55_i
|
||||||
|
1 1 1 Node N_44_i
|
||||||
|
1 1 1 Node N_45_i
|
||||||
|
1 2 1 Node N_33_i
|
||||||
|
1 2 1 Node N_32_i
|
||||||
|
1 2 1 Node N_22_i
|
||||||
|
1 1 1 Node N_51_i
|
||||||
|
1 1 1 Node N_52_i
|
||||||
|
1 1 1 Node N_53_i
|
||||||
|
1 2 1 Node cpu_est_11_0_3__n
|
||||||
|
1 1 1 Node N_42_i
|
||||||
|
1 1 1 Node N_43_i
|
||||||
|
1 1 1 Node N_40_i
|
||||||
|
1 1 1 Node N_41_i
|
||||||
|
1 1 1 Node N_39_i
|
||||||
|
1 1 1 Node N_57_i
|
||||||
|
1 2 1 Node N_11_0
|
||||||
|
1 2 1 Node bg_amiga_un1_as_030_0_n
|
||||||
|
1 2 1 Node N_47_i
|
||||||
|
1 2 1 Node un5_lds_logic_i
|
||||||
|
1 1 1 Node a_c_i_0__n
|
||||||
|
1 1 1 Node size_c_i_1__n
|
||||||
|
1 2 1 Node un1_as_000_int2_1_0
|
||||||
|
1 2 1 Node un1_as_000_int2_0
|
||||||
|
1 1 1 Node N_70_i
|
||||||
|
1 2 1 Node N_69_i
|
||||||
|
1 2 1 Node un22_fpu_cs_int_1
|
||||||
|
1 2 1 Node un22_fpu_cs_int_2
|
||||||
|
1 2 1 Node un22_fpu_cs_int_3
|
||||||
|
1 2 1 Node un22_fpu_cs_int_4
|
||||||
|
1 2 1 Node un22_fpu_cs_int_5
|
||||||
|
1 2 1 Node UDS_000_INT_1_sqmuxa_1
|
||||||
|
1 2 1 Node un5_lds_logic_i_1
|
||||||
|
1 2 1 Node cpu_est_11_0_1_1__n
|
||||||
|
1 2 1 Node cpu_est_11_0_2_1__n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_1_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_2_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_3_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_4_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_5_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_6_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_7_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_8_n
|
||||||
|
1 2 1 Node as_edge_un11_as_030_ne_9_n
|
||||||
|
1 2 1 Node N_39_1
|
||||||
|
1 2 1 Node N_39_2
|
||||||
|
1 2 1 Node N_39_3
|
||||||
|
1 2 1 Node cpu_est_11_0_1_3__n
|
||||||
|
1 2 1 Node N_15_i_1
|
||||||
|
1 2 1 Node N_53_1
|
||||||
|
1 2 1 Node N_43_1
|
||||||
|
1 2 1 Node N_42_1
|
||||||
|
=========
|
||||||
|
246/110 Best P-Term Total: 246
|
||||||
|
Total Pins: 74
|
||||||
|
Total Nodes: 192
|
||||||
|
Average P-Term/Output: 1
|
||||||
|
|
||||||
|
|
||||||
|
Equations:
|
||||||
|
|
||||||
|
IPL_030_2_ = (IPL_030DFF_2_reg);
|
||||||
|
|
||||||
|
DSACK_1_ = (DSACK_INT_1_);
|
||||||
|
|
||||||
|
DSACK_1_.OE = (CPU_SPACE_c);
|
||||||
|
|
||||||
|
AS_000 = (inst_AS_000_INT);
|
||||||
|
|
||||||
|
AS_000.OE = (N_69_i);
|
||||||
|
|
||||||
|
UDS_000 = (inst_UDS_000_INTreg);
|
||||||
|
|
||||||
|
UDS_000.OE = (N_69_i);
|
||||||
|
|
||||||
|
LDS_000 = (inst_LDS_000_INTreg);
|
||||||
|
|
||||||
|
LDS_000.OE = (N_69_i);
|
||||||
|
|
||||||
|
BERR = (gnd_n_n);
|
||||||
|
|
||||||
|
BERR.OE = (un22_fpu_cs_int);
|
||||||
|
|
||||||
|
BG_000 = (BG_000DFFSHreg);
|
||||||
|
|
||||||
|
BGACK_030 = (N_69_i);
|
||||||
|
|
||||||
|
CLK_DIV_OUT = (CLK_OUT_INTreg);
|
||||||
|
|
||||||
|
CLK_EXP = (CLK_OUT_INTreg);
|
||||||
|
|
||||||
|
FPU_CS = (un22_fpu_cs_int_i);
|
||||||
|
|
||||||
|
DTACK = (un1_dtack_int_i);
|
||||||
|
|
||||||
|
DTACK.OE = (N_69);
|
||||||
|
|
||||||
|
AVEC = (N_47_i);
|
||||||
|
|
||||||
|
E = (cpu_est_3_reg);
|
||||||
|
|
||||||
|
VMA = (inst_VMA_INTreg);
|
||||||
|
|
||||||
|
IPL_030_1_ = (IPL_030DFF_1_reg);
|
||||||
|
|
||||||
|
IPL_030_0_ = (IPL_030DFF_0_reg);
|
||||||
|
|
||||||
|
DSACK_0_ = (vcc_n_n);
|
||||||
|
|
||||||
|
DSACK_0_.OE = (CPU_SPACE_c);
|
||||||
|
|
||||||
|
N_41_1 = (cpu_est_1_ & cpu_est_i_0__n);
|
||||||
|
|
||||||
|
N_40_1 = (N_22 & cpu_est_0_);
|
||||||
|
|
||||||
|
vma_int_0_un3_n = (!N_11);
|
||||||
|
|
||||||
|
vma_int_0_un1_n = (cpu_est_3_reg & N_11);
|
||||||
|
|
||||||
|
vma_int_0_un0_n = (inst_VMA_INTreg & vma_int_0_un3_n);
|
||||||
|
|
||||||
|
uds_000_int_0_un3_n = (!UDS_000_INT_1_sqmuxa);
|
||||||
|
|
||||||
|
uds_000_int_0_un1_n = (inst_UDS_000_INTreg & UDS_000_INT_1_sqmuxa);
|
||||||
|
|
||||||
|
uds_000_int_0_un0_n = (un1_as_000_int2 & uds_000_int_0_un3_n);
|
||||||
|
|
||||||
|
cpu_est_3_reg.D = (!cpu_est_11_0_3__n);
|
||||||
|
|
||||||
|
cpu_est_3_reg.C = (CLK_000_i);
|
||||||
|
|
||||||
|
lds_000_int_0_un3_n = (!UDS_000_INT_1_sqmuxa);
|
||||||
|
|
||||||
|
inst_VMA_INTreg.D = (vma_int_0_un1_n
|
||||||
|
# vma_int_0_un0_n);
|
||||||
|
|
||||||
|
inst_VMA_INTreg.C = (CLK_000_i);
|
||||||
|
|
||||||
|
lds_000_int_0_un1_n = (inst_LDS_000_INTreg & UDS_000_INT_1_sqmuxa);
|
||||||
|
|
||||||
|
cpu_est_0_.D = (cpu_est_i_0__n);
|
||||||
|
|
||||||
|
cpu_est_0_.C = (CLK_000_i);
|
||||||
|
|
||||||
|
lds_000_int_0_un0_n = (un1_as_000_int2_1 & lds_000_int_0_un3_n);
|
||||||
|
|
||||||
|
cpu_est_1_.D = (!cpu_est_11_0_1__n);
|
||||||
|
|
||||||
|
cpu_est_1_.C = (CLK_000_i);
|
||||||
|
|
||||||
|
a_23__n = (A_23_);
|
||||||
|
|
||||||
|
inst_AS_000_INT_D.D = (inst_AS_000_INT);
|
||||||
|
|
||||||
|
inst_AS_000_INT_D.AP = (N_48_i);
|
||||||
|
|
||||||
|
inst_AS_000_INT_D.C = (CLK_000_c);
|
||||||
|
|
||||||
|
inst_AS_000_INT_DD.D = (inst_AS_000_INT_D);
|
||||||
|
|
||||||
|
inst_AS_000_INT_DD.AP = (N_48_i);
|
||||||
|
|
||||||
|
inst_AS_000_INT_DD.C = (CLK_000_c);
|
||||||
|
|
||||||
|
a_22__n = (A_22_);
|
||||||
|
|
||||||
|
inst_AS_030_AMIGA_ENABLE.D = (as_edge_un11_as_030_ne_9_n & as_edge_un11_as_030_ne_8_n);
|
||||||
|
|
||||||
|
inst_AS_030_AMIGA_ENABLE.AP = (RST_i);
|
||||||
|
|
||||||
|
inst_AS_030_AMIGA_ENABLE.C = (CLK_030_i);
|
||||||
|
|
||||||
|
vcc_n_n = (1);
|
||||||
|
|
||||||
|
a_21__n = (A_21_);
|
||||||
|
|
||||||
|
gnd_n_n = (0);
|
||||||
|
|
||||||
|
cpu_est_2_.D = (N_40_i & N_41_i);
|
||||||
|
|
||||||
|
cpu_est_2_.C = (CLK_000_i);
|
||||||
|
|
||||||
|
a_20__n = (A_20_);
|
||||||
|
|
||||||
|
inst_AS_030_delay.D = (AS_030_c);
|
||||||
|
|
||||||
|
inst_AS_030_delay.AP = (RST_i);
|
||||||
|
|
||||||
|
inst_AS_030_delay.C = (CLK_030_i);
|
||||||
|
|
||||||
|
DSACK_INT_1_.D = (N_15_i_1 & N_43_i);
|
||||||
|
|
||||||
|
DSACK_INT_1_.AP = (N_48_i);
|
||||||
|
|
||||||
|
DSACK_INT_1_.C = (CLK_000_c);
|
||||||
|
|
||||||
|
a_15__n = (A_15_);
|
||||||
|
|
||||||
|
un1_as_000_int2 = (!un1_as_000_int2_0);
|
||||||
|
|
||||||
|
a_14__n = (A_14_);
|
||||||
|
|
||||||
|
un22_fpu_cs_int = (un22_fpu_cs_int_4 & un22_fpu_cs_int_5);
|
||||||
|
|
||||||
|
inst_AS_000_INT.D = (!inst_AS_030_AMIGA_ENABLE);
|
||||||
|
|
||||||
|
inst_AS_000_INT.AP = (N_48_i);
|
||||||
|
|
||||||
|
inst_AS_000_INT.C = (CLK_000_c);
|
||||||
|
|
||||||
|
a_13__n = (A_13_);
|
||||||
|
|
||||||
|
un1_as_000_int2_1 = (!un1_as_000_int2_1_0);
|
||||||
|
|
||||||
|
a_12__n = (A_12_);
|
||||||
|
|
||||||
|
UDS_000_INT_1_sqmuxa = (UDS_000_INT_1_sqmuxa_1 & inst_AS_030_AMIGA_ENABLE);
|
||||||
|
|
||||||
|
inst_LDS_000_INTreg.D = (lds_000_int_0_un1_n
|
||||||
|
# lds_000_int_0_un0_n);
|
||||||
|
|
||||||
|
inst_LDS_000_INTreg.AP = (N_48_i);
|
||||||
|
|
||||||
|
inst_LDS_000_INTreg.C = (CLK_000_c);
|
||||||
|
|
||||||
|
a_11__n = (A_11_);
|
||||||
|
|
||||||
|
inst_UDS_000_INTreg.D = (uds_000_int_0_un1_n
|
||||||
|
# uds_000_int_0_un0_n);
|
||||||
|
|
||||||
|
inst_UDS_000_INTreg.AP = (N_48_i);
|
||||||
|
|
||||||
|
inst_UDS_000_INTreg.C = (CLK_000_c);
|
||||||
|
|
||||||
|
un1_dtack_int = (AS_000_i & dsack_i_1__n);
|
||||||
|
|
||||||
|
a_10__n = (A_10_);
|
||||||
|
|
||||||
|
a_9__n = (A_9_);
|
||||||
|
|
||||||
|
a_8__n = (A_8_);
|
||||||
|
|
||||||
|
un5_lds_logic = (!un5_lds_logic_i);
|
||||||
|
|
||||||
|
a_7__n = (A_7_);
|
||||||
|
|
||||||
|
N_11 = (!N_11_0);
|
||||||
|
|
||||||
|
N_22 = (!N_22_i);
|
||||||
|
|
||||||
|
a_6__n = (A_6_);
|
||||||
|
|
||||||
|
N_32 = (!N_32_i);
|
||||||
|
|
||||||
|
N_33 = (!N_33_i);
|
||||||
|
|
||||||
|
a_5__n = (A_5_);
|
||||||
|
|
||||||
|
N_48 = (AS_030_i & RST_c);
|
||||||
|
|
||||||
|
N_39 = (N_39_3 & cpu_est_i_0__n);
|
||||||
|
|
||||||
|
a_4__n = (A_4_);
|
||||||
|
|
||||||
|
N_40 = (N_40_1 & cpu_est_i_3__n);
|
||||||
|
|
||||||
|
N_41 = (N_41_1 & cpu_est_i_2__n);
|
||||||
|
|
||||||
|
a_3__n = (A_3_);
|
||||||
|
|
||||||
|
N_42 = (N_42_1 & VPA_c);
|
||||||
|
|
||||||
|
N_43 = (N_43_1 & VPA_i);
|
||||||
|
|
||||||
|
a_2__n = (A_2_);
|
||||||
|
|
||||||
|
N_44 = (N_32 & cpu_est_i_0__n);
|
||||||
|
|
||||||
|
N_45 = (cpu_est_i_2__n & cpu_est_i_3__n);
|
||||||
|
|
||||||
|
a_1__n = (A_1_);
|
||||||
|
|
||||||
|
N_46 = (N_32_i & cpu_est_0_);
|
||||||
|
|
||||||
|
N_51 = (N_33 & cpu_est_3_reg);
|
||||||
|
|
||||||
|
d_31__n = (D_31_);
|
||||||
|
|
||||||
|
N_52 = (N_33_i & cpu_est_i_2__n);
|
||||||
|
|
||||||
|
N_53 = (N_53_1 & cpu_est_i_2__n);
|
||||||
|
|
||||||
|
d_30__n = (D_30_);
|
||||||
|
|
||||||
|
N_55 = (N_22_i & cpu_est_3_reg);
|
||||||
|
|
||||||
|
N_57 = (N_55 & cpu_est_0_);
|
||||||
|
|
||||||
|
d_29__n = (D_29_);
|
||||||
|
|
||||||
|
N_69 = (!N_69_i);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_i = (!un22_fpu_cs_int);
|
||||||
|
|
||||||
|
d_28__n = (D_28_);
|
||||||
|
|
||||||
|
AS_000_i = (!AS_000_c);
|
||||||
|
|
||||||
|
VPA_i = (!VPA_c);
|
||||||
|
|
||||||
|
cpu_est_i_0__n = (!cpu_est_0_);
|
||||||
|
|
||||||
|
AS_030_i = (!AS_030_c);
|
||||||
|
|
||||||
|
cpu_est_i_1__n = (!cpu_est_1_);
|
||||||
|
|
||||||
|
cpu_est_i_2__n = (!cpu_est_2_);
|
||||||
|
|
||||||
|
cpu_est_i_3__n = (!cpu_est_3_reg);
|
||||||
|
|
||||||
|
VMA_INT_i = (!inst_VMA_INTreg);
|
||||||
|
|
||||||
|
AS_000_INT_DD_i = (!inst_AS_000_INT_DD);
|
||||||
|
|
||||||
|
DTACK_i = (!DTACK_c);
|
||||||
|
|
||||||
|
dsack_i_1__n = (!dsack_c_1__n);
|
||||||
|
|
||||||
|
RW_i = (!RW_c);
|
||||||
|
|
||||||
|
BGACK_000_i = (!BGACK_000_c);
|
||||||
|
|
||||||
|
a_i_18__n = (!a_c_18__n);
|
||||||
|
|
||||||
|
a_i_19__n = (!a_c_19__n);
|
||||||
|
|
||||||
|
a_i_16__n = (!a_c_16__n);
|
||||||
|
|
||||||
|
a_i_30__n = (!a_c_30__n);
|
||||||
|
|
||||||
|
a_i_31__n = (!a_c_31__n);
|
||||||
|
|
||||||
|
a_i_28__n = (!a_c_28__n);
|
||||||
|
|
||||||
|
a_i_29__n = (!a_c_29__n);
|
||||||
|
|
||||||
|
a_i_26__n = (!a_c_26__n);
|
||||||
|
|
||||||
|
a_i_27__n = (!a_c_27__n);
|
||||||
|
|
||||||
|
a_i_24__n = (!a_c_24__n);
|
||||||
|
|
||||||
|
a_i_25__n = (!a_c_25__n);
|
||||||
|
|
||||||
|
CLK_030_i = (!CLK_030_c);
|
||||||
|
|
||||||
|
RST_i = (!RST_c);
|
||||||
|
|
||||||
|
N_48_i = (!N_48);
|
||||||
|
|
||||||
|
CLK_000_i = (!CLK_000_c);
|
||||||
|
|
||||||
|
un1_dtack_int_i = (!un1_dtack_int);
|
||||||
|
|
||||||
|
AS_030_c = (AS_030);
|
||||||
|
|
||||||
|
AS_000_c = (AS_000.PIN);
|
||||||
|
|
||||||
|
size_c_0__n = (SIZE_0_);
|
||||||
|
|
||||||
|
size_c_1__n = (SIZE_1_);
|
||||||
|
|
||||||
|
a_c_0__n = (A_0_);
|
||||||
|
|
||||||
|
a_c_16__n = (A_16_);
|
||||||
|
|
||||||
|
a_c_17__n = (A_17_);
|
||||||
|
|
||||||
|
a_c_18__n = (A_18_);
|
||||||
|
|
||||||
|
a_c_19__n = (A_19_);
|
||||||
|
|
||||||
|
a_c_24__n = (A_24_);
|
||||||
|
|
||||||
|
a_c_25__n = (A_25_);
|
||||||
|
|
||||||
|
a_c_26__n = (A_26_);
|
||||||
|
|
||||||
|
a_c_27__n = (A_27_);
|
||||||
|
|
||||||
|
a_c_28__n = (A_28_);
|
||||||
|
|
||||||
|
a_c_29__n = (A_29_);
|
||||||
|
|
||||||
|
a_c_30__n = (A_30_);
|
||||||
|
|
||||||
|
a_c_31__n = (A_31_);
|
||||||
|
|
||||||
|
CPU_SPACE_c = (CPU_SPACE);
|
||||||
|
|
||||||
|
BG_000DFFSHreg.D = (!bg_amiga_un1_as_030_0_n);
|
||||||
|
|
||||||
|
BG_000DFFSHreg.AP = (BG_030);
|
||||||
|
|
||||||
|
BG_000DFFSHreg.C = (CLK_000_i);
|
||||||
|
|
||||||
|
BGACK_000_c = (BGACK_000);
|
||||||
|
|
||||||
|
CLK_030_c = (CLK_030);
|
||||||
|
|
||||||
|
CLK_000_c = (CLK_000);
|
||||||
|
|
||||||
|
CLK_OUT_INTreg.D = (!CLK_OUT_INTreg);
|
||||||
|
|
||||||
|
CLK_OUT_INTreg.C = (CLK_OSZI);
|
||||||
|
|
||||||
|
IPL_030DFF_0_reg.D = (IPL_0_);
|
||||||
|
|
||||||
|
IPL_030DFF_0_reg.C = (CLK_000_c);
|
||||||
|
|
||||||
|
IPL_030DFF_1_reg.D = (IPL_1_);
|
||||||
|
|
||||||
|
IPL_030DFF_1_reg.C = (CLK_000_c);
|
||||||
|
|
||||||
|
IPL_030DFF_2_reg.D = (IPL_2_);
|
||||||
|
|
||||||
|
IPL_030DFF_2_reg.C = (CLK_000_c);
|
||||||
|
|
||||||
|
dsack_c_1__n = (DSACK_1_.PIN);
|
||||||
|
|
||||||
|
DTACK_c = (DTACK.PIN);
|
||||||
|
|
||||||
|
VPA_c = (VPA);
|
||||||
|
|
||||||
|
RST_c = (RST);
|
||||||
|
|
||||||
|
RW_c = (RW);
|
||||||
|
|
||||||
|
fc_c_0__n = (FC_0_);
|
||||||
|
|
||||||
|
fc_c_1__n = (FC_1_);
|
||||||
|
|
||||||
|
N_70 = (CLK_000_i & N_69);
|
||||||
|
|
||||||
|
cpu_est_11_0_1__n = (cpu_est_11_0_1_1__n & cpu_est_11_0_2_1__n);
|
||||||
|
|
||||||
|
N_46_i = (!N_46);
|
||||||
|
|
||||||
|
N_55_i = (!N_55);
|
||||||
|
|
||||||
|
N_44_i = (!N_44);
|
||||||
|
|
||||||
|
N_45_i = (!N_45);
|
||||||
|
|
||||||
|
N_33_i = (cpu_est_0_ & cpu_est_1_);
|
||||||
|
|
||||||
|
N_32_i = (cpu_est_i_1__n & cpu_est_i_3__n);
|
||||||
|
|
||||||
|
N_22_i = (cpu_est_1_ & cpu_est_2_);
|
||||||
|
|
||||||
|
N_51_i = (!N_51);
|
||||||
|
|
||||||
|
N_52_i = (!N_52);
|
||||||
|
|
||||||
|
N_53_i = (!N_53);
|
||||||
|
|
||||||
|
cpu_est_11_0_3__n = (cpu_est_11_0_1_3__n & N_52_i);
|
||||||
|
|
||||||
|
N_42_i = (!N_42);
|
||||||
|
|
||||||
|
N_43_i = (!N_43);
|
||||||
|
|
||||||
|
N_40_i = (!N_40);
|
||||||
|
|
||||||
|
N_41_i = (!N_41);
|
||||||
|
|
||||||
|
N_39_i = (!N_39);
|
||||||
|
|
||||||
|
N_57_i = (!N_57);
|
||||||
|
|
||||||
|
N_11_0 = (N_39_i & N_57_i);
|
||||||
|
|
||||||
|
bg_amiga_un1_as_030_0_n = (AS_030_c & CPU_SPACE_c);
|
||||||
|
|
||||||
|
N_47_i = (CPU_SPACE_c & VPA_c);
|
||||||
|
|
||||||
|
un5_lds_logic_i = (un5_lds_logic_i_1 & size_c_0__n);
|
||||||
|
|
||||||
|
a_c_i_0__n = (!a_c_0__n);
|
||||||
|
|
||||||
|
size_c_i_1__n = (!size_c_1__n);
|
||||||
|
|
||||||
|
un1_as_000_int2_1_0 = (inst_AS_030_AMIGA_ENABLE & un5_lds_logic);
|
||||||
|
|
||||||
|
un1_as_000_int2_0 = (inst_AS_030_AMIGA_ENABLE & a_c_i_0__n);
|
||||||
|
|
||||||
|
N_70_i = (!N_70);
|
||||||
|
|
||||||
|
N_69_i = (BGACK_000_c & N_70_i);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_1 = (a_c_17__n & a_i_16__n);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_2 = (a_i_18__n & a_i_19__n);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_3 = (fc_c_1__n & BGACK_000_i);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_4 = (un22_fpu_cs_int_1 & un22_fpu_cs_int_2);
|
||||||
|
|
||||||
|
un22_fpu_cs_int_5 = (un22_fpu_cs_int_3 & fc_c_0__n);
|
||||||
|
|
||||||
|
UDS_000_INT_1_sqmuxa_1 = (RW_i & inst_AS_000_INT_D);
|
||||||
|
|
||||||
|
un5_lds_logic_i_1 = (size_c_i_1__n & a_c_i_0__n);
|
||||||
|
|
||||||
|
cpu_est_11_0_1_1__n = (N_44_i & N_45_i);
|
||||||
|
|
||||||
|
cpu_est_11_0_2_1__n = (N_46_i & N_55_i);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_1_n = (CPU_SPACE_c & a_i_30__n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_2_n = (a_i_31__n & inst_AS_030_delay);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_3_n = (AS_030_i & a_i_24__n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_4_n = (a_i_25__n & a_i_26__n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_5_n = (a_i_27__n & a_i_28__n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_6_n = (as_edge_un11_as_030_ne_1_n & as_edge_un11_as_030_ne_2_n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_7_n = (as_edge_un11_as_030_ne_3_n & as_edge_un11_as_030_ne_4_n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_8_n = (as_edge_un11_as_030_ne_5_n & a_i_29__n);
|
||||||
|
|
||||||
|
as_edge_un11_as_030_ne_9_n = (as_edge_un11_as_030_ne_6_n & as_edge_un11_as_030_ne_7_n);
|
||||||
|
|
||||||
|
N_39_1 = (AS_000_i & N_32_i);
|
||||||
|
|
||||||
|
N_39_2 = (VPA_i & cpu_est_2_);
|
||||||
|
|
||||||
|
N_39_3 = (N_39_1 & N_39_2);
|
||||||
|
|
||||||
|
cpu_est_11_0_1_3__n = (N_53_i & N_51_i);
|
||||||
|
|
||||||
|
N_15_i_1 = (DSACK_INT_1_ & N_42_i);
|
||||||
|
|
||||||
|
N_53_1 = (cpu_est_i_0__n & cpu_est_i_1__n);
|
||||||
|
|
||||||
|
N_43_1 = (N_57 & VMA_INT_i);
|
||||||
|
|
||||||
|
N_42_1 = (AS_000_INT_DD_i & DTACK_i);
|
||||||
|
|
||||||
|
|
||||||
|
Reverse-Polarity Equations:
|
||||||
|
|
||||||
|
!IPL_030_2_ = (!IPL_030DFF_2_reg);
|
||||||
|
|
||||||
|
!DSACK_1_ = (!DSACK_INT_1_);
|
||||||
|
|
||||||
|
!DSACK_1_.OE = (!CPU_SPACE_c);
|
||||||
|
|
||||||
|
!AS_000 = (!inst_AS_000_INT);
|
||||||
|
|
||||||
|
!AS_000.OE = (!N_69_i);
|
||||||
|
|
||||||
|
!UDS_000 = (!inst_UDS_000_INTreg);
|
||||||
|
|
||||||
|
!UDS_000.OE = (!N_69_i);
|
||||||
|
|
||||||
|
!LDS_000 = (!inst_LDS_000_INTreg);
|
||||||
|
|
||||||
|
!LDS_000.OE = (!N_69_i);
|
||||||
|
|
||||||
|
!BERR = (!gnd_n_n);
|
||||||
|
|
||||||
|
!BERR.OE = (!un22_fpu_cs_int);
|
||||||
|
|
||||||
|
!BG_000 = (!BG_000DFFSHreg);
|
||||||
|
|
||||||
|
!BGACK_030 = (!N_69_i);
|
||||||
|
|
||||||
|
!CLK_DIV_OUT = (!CLK_OUT_INTreg);
|
||||||
|
|
||||||
|
!CLK_EXP = (!CLK_OUT_INTreg);
|
||||||
|
|
||||||
|
!FPU_CS = (!un22_fpu_cs_int_i);
|
||||||
|
|
||||||
|
!DTACK = (!un1_dtack_int_i);
|
||||||
|
|
||||||
|
!DTACK.OE = (!N_69);
|
||||||
|
|
||||||
|
!AVEC = (!N_47_i);
|
||||||
|
|
||||||
|
!E = (!cpu_est_3_reg);
|
||||||
|
|
||||||
|
!VMA = (!inst_VMA_INTreg);
|
||||||
|
|
||||||
|
!IPL_030_1_ = (!IPL_030DFF_1_reg);
|
||||||
|
|
||||||
|
!IPL_030_0_ = (!IPL_030DFF_0_reg);
|
||||||
|
|
||||||
|
!DSACK_0_ = (!vcc_n_n);
|
||||||
|
|
||||||
|
!DSACK_0_.OE = (!CPU_SPACE_c);
|
||||||
|
|
||||||
|
!cpu_est_3_reg.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!inst_VMA_INTreg.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!cpu_est_0_.D = (!cpu_est_i_0__n);
|
||||||
|
|
||||||
|
!cpu_est_0_.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!cpu_est_1_.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!a_23__n = (!A_23_);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_D.D = (!inst_AS_000_INT);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_D.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_D.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_DD.D = (!inst_AS_000_INT_D);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_DD.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!inst_AS_000_INT_DD.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!a_22__n = (!A_22_);
|
||||||
|
|
||||||
|
!inst_AS_030_AMIGA_ENABLE.AP = (!RST_i);
|
||||||
|
|
||||||
|
!inst_AS_030_AMIGA_ENABLE.C = (!CLK_030_i);
|
||||||
|
|
||||||
|
!a_21__n = (!A_21_);
|
||||||
|
|
||||||
|
!cpu_est_2_.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!a_20__n = (!A_20_);
|
||||||
|
|
||||||
|
!inst_AS_030_delay.D = (!AS_030_c);
|
||||||
|
|
||||||
|
!inst_AS_030_delay.AP = (!RST_i);
|
||||||
|
|
||||||
|
!inst_AS_030_delay.C = (!CLK_030_i);
|
||||||
|
|
||||||
|
!DSACK_INT_1_.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!DSACK_INT_1_.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!a_15__n = (!A_15_);
|
||||||
|
|
||||||
|
!a_14__n = (!A_14_);
|
||||||
|
|
||||||
|
!inst_AS_000_INT.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!inst_AS_000_INT.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!a_13__n = (!A_13_);
|
||||||
|
|
||||||
|
!a_12__n = (!A_12_);
|
||||||
|
|
||||||
|
!inst_LDS_000_INTreg.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!inst_LDS_000_INTreg.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!a_11__n = (!A_11_);
|
||||||
|
|
||||||
|
!inst_UDS_000_INTreg.AP = (!N_48_i);
|
||||||
|
|
||||||
|
!inst_UDS_000_INTreg.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!a_10__n = (!A_10_);
|
||||||
|
|
||||||
|
!a_9__n = (!A_9_);
|
||||||
|
|
||||||
|
!a_8__n = (!A_8_);
|
||||||
|
|
||||||
|
!a_7__n = (!A_7_);
|
||||||
|
|
||||||
|
!a_6__n = (!A_6_);
|
||||||
|
|
||||||
|
!a_5__n = (!A_5_);
|
||||||
|
|
||||||
|
!a_4__n = (!A_4_);
|
||||||
|
|
||||||
|
!a_3__n = (!A_3_);
|
||||||
|
|
||||||
|
!a_2__n = (!A_2_);
|
||||||
|
|
||||||
|
!a_1__n = (!A_1_);
|
||||||
|
|
||||||
|
!d_31__n = (!D_31_);
|
||||||
|
|
||||||
|
!d_30__n = (!D_30_);
|
||||||
|
|
||||||
|
!d_29__n = (!D_29_);
|
||||||
|
|
||||||
|
!d_28__n = (!D_28_);
|
||||||
|
|
||||||
|
!AS_030_c = (!AS_030);
|
||||||
|
|
||||||
|
!AS_000_c = (!AS_000.PIN);
|
||||||
|
|
||||||
|
!size_c_0__n = (!SIZE_0_);
|
||||||
|
|
||||||
|
!size_c_1__n = (!SIZE_1_);
|
||||||
|
|
||||||
|
!a_c_0__n = (!A_0_);
|
||||||
|
|
||||||
|
!a_c_16__n = (!A_16_);
|
||||||
|
|
||||||
|
!a_c_17__n = (!A_17_);
|
||||||
|
|
||||||
|
!a_c_18__n = (!A_18_);
|
||||||
|
|
||||||
|
!a_c_19__n = (!A_19_);
|
||||||
|
|
||||||
|
!a_c_24__n = (!A_24_);
|
||||||
|
|
||||||
|
!a_c_25__n = (!A_25_);
|
||||||
|
|
||||||
|
!a_c_26__n = (!A_26_);
|
||||||
|
|
||||||
|
!a_c_27__n = (!A_27_);
|
||||||
|
|
||||||
|
!a_c_28__n = (!A_28_);
|
||||||
|
|
||||||
|
!a_c_29__n = (!A_29_);
|
||||||
|
|
||||||
|
!a_c_30__n = (!A_30_);
|
||||||
|
|
||||||
|
!a_c_31__n = (!A_31_);
|
||||||
|
|
||||||
|
!CPU_SPACE_c = (!CPU_SPACE);
|
||||||
|
|
||||||
|
!BG_000DFFSHreg.AP = (!BG_030);
|
||||||
|
|
||||||
|
!BG_000DFFSHreg.C = (!CLK_000_i);
|
||||||
|
|
||||||
|
!BGACK_000_c = (!BGACK_000);
|
||||||
|
|
||||||
|
!CLK_030_c = (!CLK_030);
|
||||||
|
|
||||||
|
!CLK_000_c = (!CLK_000);
|
||||||
|
|
||||||
|
!CLK_OUT_INTreg.C = (!CLK_OSZI);
|
||||||
|
|
||||||
|
!IPL_030DFF_0_reg.D = (!IPL_0_);
|
||||||
|
|
||||||
|
!IPL_030DFF_0_reg.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!IPL_030DFF_1_reg.D = (!IPL_1_);
|
||||||
|
|
||||||
|
!IPL_030DFF_1_reg.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!IPL_030DFF_2_reg.D = (!IPL_2_);
|
||||||
|
|
||||||
|
!IPL_030DFF_2_reg.C = (!CLK_000_c);
|
||||||
|
|
||||||
|
!dsack_c_1__n = (!DSACK_1_.PIN);
|
||||||
|
|
||||||
|
!DTACK_c = (!DTACK.PIN);
|
||||||
|
|
||||||
|
!VPA_c = (!VPA);
|
||||||
|
|
||||||
|
!RST_c = (!RST);
|
||||||
|
|
||||||
|
!RW_c = (!RW);
|
||||||
|
|
||||||
|
!fc_c_0__n = (!FC_0_);
|
||||||
|
|
||||||
|
!fc_c_1__n = (!FC_1_);
|
||||||
|
|
|
@ -0,0 +1,20 @@
|
||||||
|
|
||||||
|
fsm_encoding {722022201} onehot
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} idle_p {00000001}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} idle_n {00000010}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} as_set_p {00000100}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} as_set_n {00001000}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} sample_dtack_p {00010000}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} data_fetch_n {00100000}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} data_fetch_p {01000000}
|
||||||
|
|
||||||
|
fsm_state_encoding {722022201} end_cycle_n {10000000}
|
||||||
|
|
||||||
|
fsm_registers {722022201} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}
|
|
@ -0,0 +1,74 @@
|
||||||
|
AS_030 b
|
||||||
|
AS_000 b
|
||||||
|
DS_030 b
|
||||||
|
UDS_000 b
|
||||||
|
LDS_000 b
|
||||||
|
SIZE[1] b
|
||||||
|
SIZE[0] b
|
||||||
|
A[31] b
|
||||||
|
A[30] b
|
||||||
|
A[29] b
|
||||||
|
A[28] b
|
||||||
|
A[27] b
|
||||||
|
A[26] b
|
||||||
|
A[25] b
|
||||||
|
A[24] b
|
||||||
|
A[23] b
|
||||||
|
A[22] b
|
||||||
|
A[21] b
|
||||||
|
A[20] b
|
||||||
|
A[19] b
|
||||||
|
A[18] b
|
||||||
|
A[17] b
|
||||||
|
A[16] b
|
||||||
|
A[15] b
|
||||||
|
A[14] b
|
||||||
|
A[13] b
|
||||||
|
A[12] b
|
||||||
|
A[11] b
|
||||||
|
A[10] b
|
||||||
|
A[9] b
|
||||||
|
A[8] b
|
||||||
|
A[7] b
|
||||||
|
A[6] b
|
||||||
|
A[5] b
|
||||||
|
A[4] b
|
||||||
|
A[3] b
|
||||||
|
A[2] b
|
||||||
|
A[1] b
|
||||||
|
A[0] b
|
||||||
|
CPU_SPACE i
|
||||||
|
BERR b
|
||||||
|
BG_030 i
|
||||||
|
BG_000 o
|
||||||
|
BGACK_030 o
|
||||||
|
BGACK_000 i
|
||||||
|
CLK_030 i
|
||||||
|
CLK_000 i
|
||||||
|
CLK_OSZI i
|
||||||
|
CLK_DIV_OUT o
|
||||||
|
CLK_EXP o
|
||||||
|
FPU_CS o
|
||||||
|
IPL_030[2] o
|
||||||
|
IPL_030[1] o
|
||||||
|
IPL_030[0] o
|
||||||
|
IPL[2] i
|
||||||
|
IPL[1] i
|
||||||
|
IPL[0] i
|
||||||
|
DSACK[1] b
|
||||||
|
DSACK[0] b
|
||||||
|
DTACK b
|
||||||
|
AVEC o
|
||||||
|
AVEC_EXP b
|
||||||
|
E o
|
||||||
|
VPA i
|
||||||
|
VMA o
|
||||||
|
RST i
|
||||||
|
RESET o
|
||||||
|
RW i
|
||||||
|
FC[1] i
|
||||||
|
FC[0] i
|
||||||
|
AMIGA_BUS_ENABLE o
|
||||||
|
AMIGA_BUS_DATA_DIR o
|
||||||
|
AMIGA_BUS_ENABLE_LOW o
|
||||||
|
CIIN o
|
|
@ -0,0 +1,34 @@
|
||||||
|
#-- Lattice Semiconductor Corporation Ltd.
|
||||||
|
#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/logic\BUS68030.prj
|
||||||
|
#-- Written on Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
|
||||||
|
#device options
|
||||||
|
set_option -technology mach
|
||||||
|
set_option -part M4A5-128
|
||||||
|
|
||||||
|
#compilation/mapping options
|
||||||
|
|
||||||
|
#map options
|
||||||
|
|
||||||
|
#simulation options
|
||||||
|
set_option -write_verilog false
|
||||||
|
set_option -write_vhdl false
|
||||||
|
|
||||||
|
#timing analysis options
|
||||||
|
set_option -synthesis_onoff_pragma false
|
||||||
|
|
||||||
|
#-- add_file options
|
||||||
|
add_file -vhdl -lib work "68030-68000-bus.vhd"
|
||||||
|
|
||||||
|
#-- top module name
|
||||||
|
set_option -top_module BUS68030
|
||||||
|
|
||||||
|
#-- set result format/file last
|
||||||
|
project -result_file "BUS68030.edi"
|
||||||
|
|
||||||
|
#-- error message log file
|
||||||
|
project -log_file bus68030.srf
|
||||||
|
|
||||||
|
#-- run Synplify with 'arrange VHDL file'
|
||||||
|
project -run
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,94 @@
|
||||||
|
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
|
||||||
|
#install: C:\Program Files (x86)\ispLever\synpbase
|
||||||
|
#OS: Windows 7 6.1
|
||||||
|
#Hostname: DEEPTHOUGHT
|
||||||
|
|
||||||
|
#Implementation: logic
|
||||||
|
|
||||||
|
$ Start of Compile
|
||||||
|
#Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||||
|
@N|Running in 64-bit mode
|
||||||
|
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||||
|
|
||||||
|
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||||
|
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030.
|
||||||
|
File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
|
VHDL syntax check successful!
|
||||||
|
File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
|
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral
|
||||||
|
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven
|
||||||
|
Post processing for work.bus68030.behavioral
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA
|
||||||
|
@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
||||||
|
@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0)
|
||||||
|
@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ...
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA
|
||||||
|
Extracted state machine for register SM_AMIGA
|
||||||
|
State machine has 8 reachable states with original encodings of:
|
||||||
|
000
|
||||||
|
001
|
||||||
|
010
|
||||||
|
011
|
||||||
|
100
|
||||||
|
101
|
||||||
|
110
|
||||||
|
111
|
||||||
|
@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA
|
||||||
|
@END
|
||||||
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
|
# Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
###########################################################]
|
||||||
|
Map & Optimize Report
|
||||||
|
|
||||||
|
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
||||||
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||||
|
Product Version G-2012.09LC-SP1
|
||||||
|
@N: MF248 |Running in 64-bit mode.
|
||||||
|
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||||
|
original code -> new code
|
||||||
|
000 -> 00000001
|
||||||
|
001 -> 00000010
|
||||||
|
010 -> 00000100
|
||||||
|
011 -> 00001000
|
||||||
|
100 -> 00010000
|
||||||
|
101 -> 00100000
|
||||||
|
110 -> 01000000
|
||||||
|
111 -> 10000000
|
||||||
|
@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
|
---------------------------------------
|
||||||
|
Resource Usage Report
|
||||||
|
|
||||||
|
Simple gate primitives:
|
||||||
|
DFFRH 7 uses
|
||||||
|
DFF 19 uses
|
||||||
|
DFFSH 16 uses
|
||||||
|
IBUF 35 uses
|
||||||
|
BUFTH 7 uses
|
||||||
|
OBUF 15 uses
|
||||||
|
BI_DIR 2 uses
|
||||||
|
AND2 179 uses
|
||||||
|
INV 143 uses
|
||||||
|
OR2 20 uses
|
||||||
|
XOR2 8 uses
|
||||||
|
|
||||||
|
|
||||||
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
|
G-2012.09LC-SP1
|
||||||
|
Mapper successful!
|
||||||
|
|
||||||
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
||||||
|
|
||||||
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
|
# Thu May 15 19:20:48 2014
|
||||||
|
|
||||||
|
###########################################################]
|
Binary file not shown.
|
@ -0,0 +1,56 @@
|
||||||
|
<?xml version='1.0' encoding='utf-8' ?>
|
||||||
|
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||||
|
<ispXCF version="18.0.3">
|
||||||
|
<Comment></Comment>
|
||||||
|
<Chain>
|
||||||
|
<Comm>JTAG</Comm>
|
||||||
|
<Device>
|
||||||
|
<Pos>1</Pos>
|
||||||
|
<Vendor>Vantis</Vendor>
|
||||||
|
<Family>MACH4A</Family>
|
||||||
|
<Name>iM4A5-128/64</Name>
|
||||||
|
<IDCode>0x2756a157</IDCode>
|
||||||
|
<Package>All</Package>
|
||||||
|
<PON>M4A5-128/64</PON>
|
||||||
|
<Bypass>
|
||||||
|
<InstrLen>6</InstrLen>
|
||||||
|
<InstrVal>010001</InstrVal>
|
||||||
|
<BScanLen>1</BScanLen>
|
||||||
|
<BScanVal>0</BScanVal>
|
||||||
|
</Bypass>
|
||||||
|
<File>C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\Logic\68030_tk.jed</File>
|
||||||
|
<FileTime>04/26/14 13:40:41</FileTime>
|
||||||
|
<JedecChecksum>0x04D9</JedecChecksum>
|
||||||
|
<Operation>Erase,Program,Verify</Operation>
|
||||||
|
<Option>
|
||||||
|
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||||
|
<IOState>HighZ</IOState>
|
||||||
|
<PreloadLength>198</PreloadLength>
|
||||||
|
<IOVectorData>0x00000000000000000000000000000000000000000000000000</IOVectorData>
|
||||||
|
<Reinitialize value="TRUE"/>
|
||||||
|
<OverideUES value="TRUE"/>
|
||||||
|
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||||
|
<SVFProcessor>ispVM</SVFProcessor>
|
||||||
|
<Usercode>0x00000000</Usercode>
|
||||||
|
</Option>
|
||||||
|
</Device>
|
||||||
|
</Chain>
|
||||||
|
<ProjectOptions>
|
||||||
|
<Program>SEQUENTIAL</Program>
|
||||||
|
<Process>ENTIRED CHAIN</Process>
|
||||||
|
<OperationOverride>No Override</OperationOverride>
|
||||||
|
<StartTAP>TLR</StartTAP>
|
||||||
|
<EndTAP>TLR</EndTAP>
|
||||||
|
<DeGlitch value="TRUE"/>
|
||||||
|
<VerifyUsercode value="TRUE"/>
|
||||||
|
<PinSetting>
|
||||||
|
TMS LOW;
|
||||||
|
TCK LOW;
|
||||||
|
TDI LOW;
|
||||||
|
TDO LOW;
|
||||||
|
CableEN HIGH;
|
||||||
|
ISPEN LOW;
|
||||||
|
TRST HIGH;
|
||||||
|
</PinSetting>
|
||||||
|
</ProjectOptions>
|
||||||
|
</ispXCF>
|
|
@ -0,0 +1 @@
|
||||||
|
Need not generate svf file according to the constraints, exit
|
|
@ -0,0 +1,670 @@
|
||||||
|
Section Type Array Num Name Real Name Base Number Increment
|
||||||
|
// -------------------------------------------------------------------------------------------------
|
||||||
|
Port 1 SIZE(1:0) SIZE 1 2 -1
|
||||||
|
Port 2 A(31:0) A 31 32 -1
|
||||||
|
Port 3 IPL(2:0) IPL 2 3 -1
|
||||||
|
Port 4 FC(1:0) FC 1 2 -1
|
||||||
|
Port 5 IPL_030(2:0) IPL_030 2 3 -1
|
||||||
|
Port 6 DSACK(1:0) DSACK 1 2 -1
|
||||||
|
End
|
||||||
|
Section Member Rename Array-Notation Array Number Index
|
||||||
|
// -------------------------------------------------------------------------------------
|
||||||
|
Port SIZE_1_ SIZE[1] 1 0
|
||||||
|
Port SIZE_0_ SIZE[0] 1 1
|
||||||
|
Port A_31_ A[31] 2 0
|
||||||
|
Port A_30_ A[30] 2 1
|
||||||
|
Port A_29_ A[29] 2 2
|
||||||
|
Port A_28_ A[28] 2 3
|
||||||
|
Port A_27_ A[27] 2 4
|
||||||
|
Port A_26_ A[26] 2 5
|
||||||
|
Port A_25_ A[25] 2 6
|
||||||
|
Port A_24_ A[24] 2 7
|
||||||
|
Port A_23_ A[23] 2 8
|
||||||
|
Port A_22_ A[22] 2 9
|
||||||
|
Port A_21_ A[21] 2 10
|
||||||
|
Port A_20_ A[20] 2 11
|
||||||
|
Port A_19_ A[19] 2 12
|
||||||
|
Port A_18_ A[18] 2 13
|
||||||
|
Port A_17_ A[17] 2 14
|
||||||
|
Port A_16_ A[16] 2 15
|
||||||
|
Port A_15_ A[15] 2 16
|
||||||
|
Port A_14_ A[14] 2 17
|
||||||
|
Port A_13_ A[13] 2 18
|
||||||
|
Port A_12_ A[12] 2 19
|
||||||
|
Port A_11_ A[11] 2 20
|
||||||
|
Port A_10_ A[10] 2 21
|
||||||
|
Port A_9_ A[9] 2 22
|
||||||
|
Port A_8_ A[8] 2 23
|
||||||
|
Port A_7_ A[7] 2 24
|
||||||
|
Port A_6_ A[6] 2 25
|
||||||
|
Port A_5_ A[5] 2 26
|
||||||
|
Port A_4_ A[4] 2 27
|
||||||
|
Port A_3_ A[3] 2 28
|
||||||
|
Port A_2_ A[2] 2 29
|
||||||
|
Port A_1_ A[1] 2 30
|
||||||
|
Port A_0_ A[0] 2 31
|
||||||
|
Port IPL_030_2_ IPL_030[2] 5 0
|
||||||
|
Port IPL_030_1_ IPL_030[1] 5 1
|
||||||
|
Port IPL_030_0_ IPL_030[0] 5 2
|
||||||
|
Port IPL_2_ IPL[2] 3 0
|
||||||
|
Port IPL_1_ IPL[1] 3 1
|
||||||
|
Port IPL_0_ IPL[0] 3 2
|
||||||
|
Port DSACK_1_ DSACK[1] 6 0
|
||||||
|
Port DSACK_0_ DSACK[0] 6 1
|
||||||
|
Port FC_1_ FC[1] 4 0
|
||||||
|
Port FC_0_ FC[0] 4 1
|
||||||
|
End
|
||||||
|
Section Cross Reference File
|
||||||
|
Design 'BUS68030' created Thu May 15 19:20:52 2014
|
||||||
|
Type New Name Original Name
|
||||||
|
// ----------------------------------------------------------------------
|
||||||
|
Inst i_z2M2M AS_000
|
||||||
|
Inst i_z2O2O UDS_000
|
||||||
|
Inst i_z2P2P LDS_000
|
||||||
|
Inst i_z3E3E BERR
|
||||||
|
Inst i_z4141 DTACK
|
||||||
|
Inst i_z4343 AVEC_EXP
|
||||||
|
Inst i_z4F4F CIIN
|
||||||
|
Inst clk_cpu_est_11_0_i_3_ clk.cpu_est_11_0_i[3]
|
||||||
|
Inst SM_AMIGA_ns_o2_i_5_ SM_AMIGA_ns_o2_i[5]
|
||||||
|
Inst SM_AMIGA_ns_o2_i_4_ SM_AMIGA_ns_o2_i[4]
|
||||||
|
Inst state_machine_un9_clk_000_d_i_o3_i state_machine.un9_clk_000_d_i_o3_i
|
||||||
|
Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5]
|
||||||
|
Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4]
|
||||||
|
Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1]
|
||||||
|
Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3]
|
||||||
|
Inst clk_cpu_est_11_0_i_1_ clk.cpu_est_11_0_i[1]
|
||||||
|
Inst cpu_est_0_1__r cpu_est_0_1_.r
|
||||||
|
Inst cpu_est_0_1__m cpu_est_0_1_.m
|
||||||
|
Inst cpu_est_0_1__n cpu_est_0_1_.n
|
||||||
|
Inst cpu_est_0_1__p cpu_est_0_1_.p
|
||||||
|
Inst VMA_INT_0_r VMA_INT_0.r
|
||||||
|
Inst VMA_INT_0_m VMA_INT_0.m
|
||||||
|
Inst VMA_INT_0_n VMA_INT_0.n
|
||||||
|
Inst VMA_INT_0_p VMA_INT_0.p
|
||||||
|
Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1]
|
||||||
|
Inst cpu_est_i_2_ cpu_est_i[2]
|
||||||
|
Inst cpu_est_i_3_ cpu_est_i[3]
|
||||||
|
Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1]
|
||||||
|
Inst cpu_est_i_0_ cpu_est_i[0]
|
||||||
|
Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1]
|
||||||
|
Inst SM_AMIGA_4_ SM_AMIGA[4]
|
||||||
|
Inst SM_AMIGA_3_ SM_AMIGA[3]
|
||||||
|
Inst SM_AMIGA_2_ SM_AMIGA[2]
|
||||||
|
Inst SM_AMIGA_1_ SM_AMIGA[1]
|
||||||
|
Inst clk_un3_clk_000_dd clk.un3_clk_000_dd
|
||||||
|
Inst SM_AMIGA_0_ SM_AMIGA[0]
|
||||||
|
Inst cpu_est_0_3__r cpu_est_0_3_.r
|
||||||
|
Inst cpu_est_0_ cpu_est[0]
|
||||||
|
Inst cpu_est_0_3__m cpu_est_0_3_.m
|
||||||
|
Inst cpu_est_1_ cpu_est[1]
|
||||||
|
Inst cpu_est_0_3__n cpu_est_0_3_.n
|
||||||
|
Inst cpu_est_2_ cpu_est[2]
|
||||||
|
Inst cpu_est_0_3__p cpu_est_0_3_.p
|
||||||
|
Inst cpu_est_3_ cpu_est[3]
|
||||||
|
Inst cpu_est_0_2__r cpu_est_0_2_.r
|
||||||
|
Inst SM_AMIGA_7_ SM_AMIGA[7]
|
||||||
|
Inst cpu_est_0_2__m cpu_est_0_2_.m
|
||||||
|
Inst SM_AMIGA_6_ SM_AMIGA[6]
|
||||||
|
Inst cpu_est_0_2__n cpu_est_0_2_.n
|
||||||
|
Inst SM_AMIGA_5_ SM_AMIGA[5]
|
||||||
|
Inst cpu_est_0_2__p cpu_est_0_2_.p
|
||||||
|
Inst CLK_000_CNT_0_ CLK_000_CNT[0]
|
||||||
|
Inst CLK_000_CNT_1_ CLK_000_CNT[1]
|
||||||
|
Inst SM_AMIGA_ns_o2_5_ SM_AMIGA_ns_o2[5]
|
||||||
|
Inst CLK_000_CNT_2_ CLK_000_CNT[2]
|
||||||
|
Inst CLK_000_CNT_3_ CLK_000_CNT[3]
|
||||||
|
Inst SM_AMIGA_D_0_ SM_AMIGA_D[0]
|
||||||
|
Inst cpu_est_0_0_ cpu_est_0[0]
|
||||||
|
Inst SM_AMIGA_D_1_ SM_AMIGA_D[1]
|
||||||
|
Inst SM_AMIGA_D_2_ SM_AMIGA_D[2]
|
||||||
|
Inst SM_AMIGA_ns_i_a2_0_2_6_ SM_AMIGA_ns_i_a2_0_2[6]
|
||||||
|
Inst IPL_030DFFSH_0_ IPL_030DFFSH[0]
|
||||||
|
Inst IPL_030DFFSH_1_ IPL_030DFFSH[1]
|
||||||
|
Inst cpu_est_i_1_ cpu_est_i[1]
|
||||||
|
Inst IPL_030DFFSH_2_ IPL_030DFFSH[2]
|
||||||
|
Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3]
|
||||||
|
Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1]
|
||||||
|
Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2]
|
||||||
|
Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3]
|
||||||
|
Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3]
|
||||||
|
Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1]
|
||||||
|
Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2]
|
||||||
|
Inst SM_AMIGA_ns_4_ SM_AMIGA_ns[4]
|
||||||
|
Inst DSACK_INT_1_ DSACK_INT[1]
|
||||||
|
Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5]
|
||||||
|
Inst state_machine_un9_clk_000_d_i_o3 state_machine.un9_clk_000_d_i_o3
|
||||||
|
Inst SM_AMIGA_ns_o2_4_ SM_AMIGA_ns_o2[4]
|
||||||
|
Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
|
||||||
|
Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
|
||||||
|
Inst CLK_CNT_0_ CLK_CNT[0]
|
||||||
|
Inst DTACK_SYNC_0_r DTACK_SYNC_0.r
|
||||||
|
Inst DTACK_SYNC_0_m DTACK_SYNC_0.m
|
||||||
|
Inst DTACK_SYNC_0_n DTACK_SYNC_0.n
|
||||||
|
Inst DTACK_SYNC_0_p DTACK_SYNC_0.p
|
||||||
|
Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0]
|
||||||
|
Inst SM_AMIGA_i_0_ SM_AMIGA_i[0]
|
||||||
|
Inst SIZE_0_ SIZE[0]
|
||||||
|
Inst SM_AMIGA_ns_i_o2_0_ SM_AMIGA_ns_i_o2[0]
|
||||||
|
Inst SIZE_1_ SIZE[1]
|
||||||
|
Inst A_0_ A[0]
|
||||||
|
Inst SM_AMIGA_D_0_0__r SM_AMIGA_D_0_0_.r
|
||||||
|
Inst A_16_ A[16]
|
||||||
|
Inst SM_AMIGA_D_0_0__m SM_AMIGA_D_0_0_.m
|
||||||
|
Inst A_17_ A[17]
|
||||||
|
Inst SM_AMIGA_D_0_0__n SM_AMIGA_D_0_0_.n
|
||||||
|
Inst A_18_ A[18]
|
||||||
|
Inst SM_AMIGA_D_0_0__p SM_AMIGA_D_0_0_.p
|
||||||
|
Inst A_19_ A[19]
|
||||||
|
Inst state_machine_un15_clk_000_d state_machine.un15_clk_000_d
|
||||||
|
Inst A_20_ A[20]
|
||||||
|
Inst A_21_ A[21]
|
||||||
|
Inst state_machine_un15_clk_000_d_i state_machine.un15_clk_000_d_i
|
||||||
|
Inst A_22_ A[22]
|
||||||
|
Inst A_23_ A[23]
|
||||||
|
Inst A_24_ A[24]
|
||||||
|
Inst SM_AMIGA_ns_i_a3_2_ SM_AMIGA_ns_i_a3[2]
|
||||||
|
Inst A_25_ A[25]
|
||||||
|
Inst SM_AMIGA_ns_a3_4_ SM_AMIGA_ns_a3[4]
|
||||||
|
Inst A_26_ A[26]
|
||||||
|
Inst SM_AMIGA_ns_a3_0_4_ SM_AMIGA_ns_a3_0[4]
|
||||||
|
Inst A_27_ A[27]
|
||||||
|
Inst SM_AMIGA_i_5_ SM_AMIGA_i[5]
|
||||||
|
Inst A_28_ A[28]
|
||||||
|
Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3]
|
||||||
|
Inst A_29_ A[29]
|
||||||
|
Inst BGACK_030_INT_0_r BGACK_030_INT_0.r
|
||||||
|
Inst A_30_ A[30]
|
||||||
|
Inst BGACK_030_INT_0_m BGACK_030_INT_0.m
|
||||||
|
Inst A_31_ A[31]
|
||||||
|
Inst BGACK_030_INT_0_n BGACK_030_INT_0.n
|
||||||
|
Inst BGACK_030_INT_0_p BGACK_030_INT_0.p
|
||||||
|
Inst BG_000_0_r BG_000_0.r
|
||||||
|
Inst BG_000_0_m BG_000_0.m
|
||||||
|
Inst BG_000_0_n BG_000_0.n
|
||||||
|
Inst BG_000_0_p BG_000_0.p
|
||||||
|
Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r
|
||||||
|
Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m
|
||||||
|
Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n
|
||||||
|
Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p
|
||||||
|
Inst FPU_CS_INT_0_r FPU_CS_INT_0.r
|
||||||
|
Inst FPU_CS_INT_0_m FPU_CS_INT_0.m
|
||||||
|
Inst FPU_CS_INT_0_n FPU_CS_INT_0.n
|
||||||
|
Inst IPL_030_0_ IPL_030[0]
|
||||||
|
Inst FPU_CS_INT_0_p FPU_CS_INT_0.p
|
||||||
|
Inst IPL_030_1_ IPL_030[1]
|
||||||
|
Inst IPL_030_2_ IPL_030[2]
|
||||||
|
Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r
|
||||||
|
Inst IPL_0_ IPL[0]
|
||||||
|
Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m
|
||||||
|
Inst IPL_1_ IPL[1]
|
||||||
|
Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n
|
||||||
|
Inst IPL_2_ IPL[2]
|
||||||
|
Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p
|
||||||
|
Inst DSACK_0_ DSACK[0]
|
||||||
|
Inst VPA_SYNC_0_r VPA_SYNC_0.r
|
||||||
|
Inst DSACK_1_ DSACK[1]
|
||||||
|
Inst VPA_SYNC_0_m VPA_SYNC_0.m
|
||||||
|
Inst VPA_SYNC_0_n VPA_SYNC_0.n
|
||||||
|
Inst VPA_SYNC_0_p VPA_SYNC_0.p
|
||||||
|
Inst AS_000_INT_0_r AS_000_INT_0.r
|
||||||
|
Inst AS_000_INT_0_m AS_000_INT_0.m
|
||||||
|
Inst AS_000_INT_0_n AS_000_INT_0.n
|
||||||
|
Inst AS_000_INT_0_p AS_000_INT_0.p
|
||||||
|
Inst state_machine_un14_as_000_int state_machine.un14_as_000_int
|
||||||
|
Inst FC_0_ FC[0]
|
||||||
|
Inst FC_1_ FC[1]
|
||||||
|
Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
|
||||||
|
Inst SM_AMIGA_ns_i_a3_0_ SM_AMIGA_ns_i_a3[0]
|
||||||
|
Inst SM_AMIGA_ns_i_a3_1_ SM_AMIGA_ns_i_a3[1]
|
||||||
|
Inst state_machine_un5_clk_030_i_a3 state_machine.un5_clk_030_i_a3
|
||||||
|
Inst clk_cpu_est_11_0_a4_1_1_3_ clk.cpu_est_11_0_a4_1_1[3]
|
||||||
|
Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3]
|
||||||
|
Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i
|
||||||
|
Inst state_machine_un17_clk_030 state_machine.un17_clk_030
|
||||||
|
Inst un9_i_a3_2_2_ un9_i_a3_2[2]
|
||||||
|
Inst un9_i_a3_2_ un9_i_a3[2]
|
||||||
|
Inst state_machine_un1_clk_030 state_machine.un1_clk_030
|
||||||
|
Inst state_machine_un4_bgack_000 state_machine.un4_bgack_000
|
||||||
|
Inst A_i_19_ A_i[19]
|
||||||
|
Inst A_i_18_ A_i[18]
|
||||||
|
Inst A_i_16_ A_i[16]
|
||||||
|
Inst IPL_030_0_2__r IPL_030_0_2_.r
|
||||||
|
Inst IPL_030_0_2__m IPL_030_0_2_.m
|
||||||
|
Inst IPL_030_0_2__n IPL_030_0_2_.n
|
||||||
|
Inst IPL_030_0_2__p IPL_030_0_2_.p
|
||||||
|
Inst IPL_030_0_1__r IPL_030_0_1_.r
|
||||||
|
Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2]
|
||||||
|
Inst IPL_030_0_1__m IPL_030_0_1_.m
|
||||||
|
Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2]
|
||||||
|
Inst IPL_030_0_1__n IPL_030_0_1_.n
|
||||||
|
Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2]
|
||||||
|
Inst IPL_030_0_1__p IPL_030_0_1_.p
|
||||||
|
Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2]
|
||||||
|
Inst IPL_030_0_0__r IPL_030_0_0_.r
|
||||||
|
Inst SM_AMIGA_ns_i_a2_0_2_0_6_ SM_AMIGA_ns_i_a2_0_2_0[6]
|
||||||
|
Inst IPL_030_0_0__m IPL_030_0_0_.m
|
||||||
|
Inst SM_AMIGA_ns_i_a2_0_6_ SM_AMIGA_ns_i_a2_0[6]
|
||||||
|
Inst IPL_030_0_0__n IPL_030_0_0_.n
|
||||||
|
Inst un9_i_a3_1_0_ un9_i_a3_1[0]
|
||||||
|
Inst IPL_030_0_0__p IPL_030_0_0_.p
|
||||||
|
Inst un9_i_a3_0_ un9_i_a3[0]
|
||||||
|
Inst SM_AMIGA_ns_a3_0_5_ SM_AMIGA_ns_a3_0[5]
|
||||||
|
Inst un9_i_a3_1_1_ un9_i_a3_1[1]
|
||||||
|
Inst state_machine_LDS_000_INT_8 state_machine.LDS_000_INT_8
|
||||||
|
Inst un9_i_a3_1_ un9_i_a3[1]
|
||||||
|
Inst state_machine_UDS_000_INT_8 state_machine.UDS_000_INT_8
|
||||||
|
Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1
|
||||||
|
Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2
|
||||||
|
Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3
|
||||||
|
Inst SM_AMIGA_D_0_2__r SM_AMIGA_D_0_2_.r
|
||||||
|
Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4
|
||||||
|
Inst SM_AMIGA_D_0_2__m SM_AMIGA_D_0_2_.m
|
||||||
|
Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5
|
||||||
|
Inst SM_AMIGA_D_0_2__n SM_AMIGA_D_0_2_.n
|
||||||
|
Inst state_machine_un42_clk_030 state_machine.un42_clk_030
|
||||||
|
Inst SM_AMIGA_D_0_2__p SM_AMIGA_D_0_2_.p
|
||||||
|
Inst SM_AMIGA_ns_a3_1_5_ SM_AMIGA_ns_a3_1[5]
|
||||||
|
Inst SM_AMIGA_ns_a3_5_ SM_AMIGA_ns_a3[5]
|
||||||
|
Inst SM_AMIGA_D_0_1__r SM_AMIGA_D_0_1_.r
|
||||||
|
Inst un9_i_a3_1_2_ un9_i_a3_1[2]
|
||||||
|
Inst SM_AMIGA_D_0_1__m SM_AMIGA_D_0_1_.m
|
||||||
|
Inst SM_AMIGA_D_0_1__n SM_AMIGA_D_0_1_.n
|
||||||
|
Inst SM_AMIGA_D_0_1__p SM_AMIGA_D_0_1_.p
|
||||||
|
Inst LDS_000_INT_0_r LDS_000_INT_0.r
|
||||||
|
Inst LDS_000_INT_0_m LDS_000_INT_0.m
|
||||||
|
Inst LDS_000_INT_0_n LDS_000_INT_0.n
|
||||||
|
Inst LDS_000_INT_0_p LDS_000_INT_0.p
|
||||||
|
Inst UDS_000_INT_0_r UDS_000_INT_0.r
|
||||||
|
Inst UDS_000_INT_0_m UDS_000_INT_0.m
|
||||||
|
Inst UDS_000_INT_0_n UDS_000_INT_0.n
|
||||||
|
Inst UDS_000_INT_0_p UDS_000_INT_0.p
|
||||||
|
Inst SM_AMIGA_ns_i_o2_1_ SM_AMIGA_ns_i_o2[1]
|
||||||
|
Inst SM_AMIGA_ns_i_o2_2_ SM_AMIGA_ns_i_o2[2]
|
||||||
|
Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1]
|
||||||
|
Inst SM_AMIGA_ns_i_a2_0_1_6_ SM_AMIGA_ns_i_a2_0_1[6]
|
||||||
|
Inst SM_AMIGA_ns_i_a3_0_1_ SM_AMIGA_ns_i_a3_0[1]
|
||||||
|
Inst state_machine_un25_clk_000_d state_machine.un25_clk_000_d
|
||||||
|
Inst state_machine_un67_clk_000_d state_machine.un67_clk_000_d
|
||||||
|
Inst SM_AMIGA_ns_i_1_6_ SM_AMIGA_ns_i_1[6]
|
||||||
|
Inst state_machine_un80_clk_000_d state_machine.un80_clk_000_d
|
||||||
|
Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6]
|
||||||
|
Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1
|
||||||
|
Inst SM_AMIGA_i_3_ SM_AMIGA_i[3]
|
||||||
|
Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3
|
||||||
|
Inst SM_AMIGA_ns_i_a3_6_ SM_AMIGA_ns_i_a3[6]
|
||||||
|
Inst SM_AMIGA_ns_a3_0_7_ SM_AMIGA_ns_a3_0[7]
|
||||||
|
Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7]
|
||||||
|
Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3]
|
||||||
|
Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3]
|
||||||
|
Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3]
|
||||||
|
Inst SM_AMIGA_i_2_ SM_AMIGA_i[2]
|
||||||
|
Inst clk_cpu_est_11_0_1_1_ clk.cpu_est_11_0_1[1]
|
||||||
|
Inst SM_AMIGA_i_1_ SM_AMIGA_i[1]
|
||||||
|
Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1]
|
||||||
|
Inst SM_AMIGA_ns_i_a2_6_ SM_AMIGA_ns_i_a2[6]
|
||||||
|
Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1]
|
||||||
|
Inst SM_AMIGA_ns_a3_7_ SM_AMIGA_ns_a3[7]
|
||||||
|
Inst state_machine_un67_clk_000_d_i state_machine.un67_clk_000_d_i
|
||||||
|
Inst state_machine_un78_clk_000_d_i state_machine.un78_clk_000_d_i
|
||||||
|
Inst clk_RISING_CLK_AMIGA_1_i clk.RISING_CLK_AMIGA_1_i
|
||||||
|
Inst un1_CLK_000_CNT_0_ un1_CLK_000_CNT[0]
|
||||||
|
Inst un1_CLK_000_CNT_1_ un1_CLK_000_CNT[1]
|
||||||
|
Inst SM_AMIGA_ns_i_o2_i_6_ SM_AMIGA_ns_i_o2_i[6]
|
||||||
|
Inst un1_CLK_000_CNT_2_ un1_CLK_000_CNT[2]
|
||||||
|
Inst CLK_000_CNT_i_1_ CLK_000_CNT_i[1]
|
||||||
|
Inst un1_CLK_000_CNT_3_ un1_CLK_000_CNT[3]
|
||||||
|
Inst CLK_000_CNT_i_0_ CLK_000_CNT_i[0]
|
||||||
|
Inst CLK_000_CNT_i_3_ CLK_000_CNT_i[3]
|
||||||
|
Inst SM_AMIGA_ns_a3_0_1_7_ SM_AMIGA_ns_a3_0_1[7]
|
||||||
|
Inst CLK_000_CNT_i_2_ CLK_000_CNT_i[2]
|
||||||
|
Inst SM_AMIGA_ns_i_o2_6_ SM_AMIGA_ns_i_o2[6]
|
||||||
|
Inst clk_un1_clk_000_i clk.un1_clk_000_i
|
||||||
|
Inst clk_un1_clk_000_i_a3 clk.un1_clk_000_i_a3
|
||||||
|
Inst clk_RISING_CLK_AMIGA_1_0_a3 clk.RISING_CLK_AMIGA_1_0_a3
|
||||||
|
Inst state_machine_un25_clk_000_d_1 state_machine.un25_clk_000_d_1
|
||||||
|
Inst state_machine_un78_clk_000_d state_machine.un78_clk_000_d
|
||||||
|
Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i
|
||||||
|
Inst A_i_24_ A_i[24]
|
||||||
|
Inst A_i_25_ A_i[25]
|
||||||
|
Inst A_i_26_ A_i[26]
|
||||||
|
Inst A_c_i_0_ A_c_i[0]
|
||||||
|
Inst A_i_27_ A_i[27]
|
||||||
|
Inst state_machine_UDS_000_INT_8_i state_machine.UDS_000_INT_8_i
|
||||||
|
Inst A_i_28_ A_i[28]
|
||||||
|
Inst state_machine_LDS_000_INT_8_i state_machine.LDS_000_INT_8_i
|
||||||
|
Inst A_i_29_ A_i[29]
|
||||||
|
Inst A_i_30_ A_i[30]
|
||||||
|
Inst A_i_31_ A_i[31]
|
||||||
|
Inst state_machine_un14_as_000_int_i state_machine.un14_as_000_int_i
|
||||||
|
Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7]
|
||||||
|
Inst CLK_CNT_i_0_ CLK_CNT_i[0]
|
||||||
|
Inst un1_CLK_000_CNT_i_3_ un1_CLK_000_CNT_i[3]
|
||||||
|
Inst SIZE_c_i_1_ SIZE_c_i[1]
|
||||||
|
Inst state_machine_un25_clk_000_d_i_0 state_machine.un25_clk_000_d_i_0
|
||||||
|
Inst state_machine_un80_clk_000_d_i state_machine.un80_clk_000_d_i
|
||||||
|
Inst SM_AMIGA_ns_i_o2_i_0_ SM_AMIGA_ns_i_o2_i[0]
|
||||||
|
Inst state_machine_un4_bgack_000_i state_machine.un4_bgack_000_i
|
||||||
|
Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i
|
||||||
|
Inst state_machine_un17_clk_030_i state_machine.un17_clk_030_i
|
||||||
|
Inst SM_AMIGA_ns_i_o2_i_2_ SM_AMIGA_ns_i_o2_i[2]
|
||||||
|
Inst SM_AMIGA_ns_i_o2_i_1_ SM_AMIGA_ns_i_o2_i[1]
|
||||||
|
Net a_21__n A[21]
|
||||||
|
Net a_15__n A[15]
|
||||||
|
Net a_c_22__n A_c[22]
|
||||||
|
Net a_22__n A[22]
|
||||||
|
Net a_14__n A[14]
|
||||||
|
Net a_c_23__n A_c[23]
|
||||||
|
Net a_23__n A[23]
|
||||||
|
Net a_13__n A[13]
|
||||||
|
Net a_c_24__n A_c[24]
|
||||||
|
Net a_24__n A[24]
|
||||||
|
Net a_12__n A[12]
|
||||||
|
Net a_c_25__n A_c[25]
|
||||||
|
Net a_25__n A[25]
|
||||||
|
Net a_11__n A[11]
|
||||||
|
Net a_c_26__n A_c[26]
|
||||||
|
Net cpu_est_3__n cpu_est[3]
|
||||||
|
Net a_26__n A[26]
|
||||||
|
Net a_10__n A[10]
|
||||||
|
Net a_c_27__n A_c[27]
|
||||||
|
Net gnd_n_n GND
|
||||||
|
Net a_27__n A[27]
|
||||||
|
Net a_9__n A[9]
|
||||||
|
Net cpu_est_1__n cpu_est[1]
|
||||||
|
Net a_c_28__n A_c[28]
|
||||||
|
Net a_28__n A[28]
|
||||||
|
Net a_8__n A[8]
|
||||||
|
Net a_c_29__n A_c[29]
|
||||||
|
Net a_29__n A[29]
|
||||||
|
Net a_7__n A[7]
|
||||||
|
Net a_c_30__n A_c[30]
|
||||||
|
Net a_30__n A[30]
|
||||||
|
Net a_6__n A[6]
|
||||||
|
Net a_c_31__n A_c[31]
|
||||||
|
Net a_5__n A[5]
|
||||||
|
Net vcc_n_n VCC
|
||||||
|
Net a_4__n A[4]
|
||||||
|
Net cpu_est_0__n cpu_est[0]
|
||||||
|
Net cpu_est_2__n cpu_est[2]
|
||||||
|
Net a_3__n A[3]
|
||||||
|
Net clk_cnt_0__n CLK_CNT[0]
|
||||||
|
Net sm_amiga_6__n SM_AMIGA[6]
|
||||||
|
Net a_2__n A[2]
|
||||||
|
Net sm_amiga_7__n SM_AMIGA[7]
|
||||||
|
Net a_1__n A[1]
|
||||||
|
Net dsack_int_1__n DSACK_INT[1]
|
||||||
|
Net sm_amiga_4__n SM_AMIGA[4]
|
||||||
|
Net sm_amiga_3__n SM_AMIGA[3]
|
||||||
|
Net sm_amiga_5__n SM_AMIGA[5]
|
||||||
|
Net un1_clk_000_cnt_3__n un1_CLK_000_CNT[3]
|
||||||
|
Net clk_000_cnt_0__n CLK_000_CNT[0]
|
||||||
|
Net clk_000_cnt_1__n CLK_000_CNT[1]
|
||||||
|
Net clk_000_cnt_2__n CLK_000_CNT[2]
|
||||||
|
Net clk_000_cnt_3__n CLK_000_CNT[3]
|
||||||
|
Net ipl_030_c_0__n IPL_030_c[0]
|
||||||
|
Net state_machine_un14_as_000_int_n state_machine.un14_as_000_int
|
||||||
|
Net ipl_030_0__n IPL_030[0]
|
||||||
|
Net sm_amiga_2__n SM_AMIGA[2]
|
||||||
|
Net ipl_030_c_1__n IPL_030_c[1]
|
||||||
|
Net sm_amiga_1__n SM_AMIGA[1]
|
||||||
|
Net ipl_030_1__n IPL_030[1]
|
||||||
|
Net sm_amiga_0__n SM_AMIGA[0]
|
||||||
|
Net ipl_030_c_2__n IPL_030_c[2]
|
||||||
|
Net sm_amiga_d_0__n SM_AMIGA_D[0]
|
||||||
|
Net sm_amiga_d_1__n SM_AMIGA_D[1]
|
||||||
|
Net ipl_c_0__n IPL_c[0]
|
||||||
|
Net sm_amiga_d_2__n SM_AMIGA_D[2]
|
||||||
|
Net ipl_0__n IPL[0]
|
||||||
|
Net ipl_c_1__n IPL_c[1]
|
||||||
|
Net clk_clk_000_cnt_3_1__n clk.CLK_000_CNT_3[1]
|
||||||
|
Net ipl_1__n IPL[1]
|
||||||
|
Net clk_clk_000_cnt_3_2__n clk.CLK_000_CNT_3[2]
|
||||||
|
Net ipl_c_2__n IPL_c[2]
|
||||||
|
Net clk_clk_000_cnt_3_3__n clk.CLK_000_CNT_3[3]
|
||||||
|
Net dsack_0__n DSACK[0]
|
||||||
|
Net dsack_c_1__n DSACK_c[1]
|
||||||
|
Net fc_c_0__n FC_c[0]
|
||||||
|
Net fc_0__n FC[0]
|
||||||
|
Net fc_c_1__n FC_c[1]
|
||||||
|
Net sm_amiga_ns_4__n SM_AMIGA_ns[4]
|
||||||
|
Net sm_amiga_ns_5__n SM_AMIGA_ns[5]
|
||||||
|
Net sm_amiga_ns_7__n SM_AMIGA_ns[7]
|
||||||
|
Net clk_rising_clk_amiga_1_n clk.RISING_CLK_AMIGA_1
|
||||||
|
Net un1_clk_000_cnt_0__n un1_CLK_000_CNT[0]
|
||||||
|
Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1]
|
||||||
|
Net un1_clk_000_cnt_1__n un1_CLK_000_CNT[1]
|
||||||
|
Net un1_clk_000_cnt_2__n un1_CLK_000_CNT[2]
|
||||||
|
Net state_machine_un69_clk_000_d_n state_machine.un69_clk_000_d
|
||||||
|
Net state_machine_un78_clk_000_d_n state_machine.un78_clk_000_d
|
||||||
|
Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3]
|
||||||
|
Net state_machine_un67_clk_000_d_n state_machine.un67_clk_000_d
|
||||||
|
Net state_machine_un80_clk_000_d_n state_machine.un80_clk_000_d
|
||||||
|
Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5]
|
||||||
|
Net state_machine_un25_clk_000_d_n state_machine.un25_clk_000_d
|
||||||
|
Net sm_amiga_ns_0_4__n SM_AMIGA_ns_0[4]
|
||||||
|
Net state_machine_lds_000_int_8_n state_machine.LDS_000_INT_8
|
||||||
|
Net state_machine_uds_000_int_8_n state_machine.UDS_000_INT_8
|
||||||
|
Net state_machine_un42_clk_030_n state_machine.un42_clk_030
|
||||||
|
Net state_machine_un4_bgack_000_0_n state_machine.un4_bgack_000_0
|
||||||
|
Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3
|
||||||
|
Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0
|
||||||
|
Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0
|
||||||
|
Net state_machine_un17_clk_030_n state_machine.un17_clk_030
|
||||||
|
Net state_machine_un1_clk_030_n state_machine.un1_clk_030
|
||||||
|
Net state_machine_un4_bgack_000_n state_machine.un4_bgack_000
|
||||||
|
Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2
|
||||||
|
Net a_c_i_0__n A_c_i[0]
|
||||||
|
Net state_machine_uds_000_int_8_0_n state_machine.UDS_000_INT_8_0
|
||||||
|
Net state_machine_lds_000_int_8_0_n state_machine.LDS_000_INT_8_0
|
||||||
|
Net state_machine_un15_clk_000_d_n state_machine.un15_clk_000_d
|
||||||
|
Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7]
|
||||||
|
Net size_c_i_1__n SIZE_c_i[1]
|
||||||
|
Net state_machine_un25_clk_000_d_i_n state_machine.un25_clk_000_d_i
|
||||||
|
Net state_machine_un80_clk_000_d_i_n state_machine.un80_clk_000_d_i
|
||||||
|
Net state_machine_un67_clk_000_d_i_n state_machine.un67_clk_000_d_i
|
||||||
|
Net state_machine_un78_clk_000_d_0_n state_machine.un78_clk_000_d_0
|
||||||
|
Net clk_rising_clk_amiga_1_i_n clk.RISING_CLK_AMIGA_1_i
|
||||||
|
Net clk_un3_clk_000_dd_n clk.un3_clk_000_dd
|
||||||
|
Net clk_000_cnt_i_1__n CLK_000_CNT_i[1]
|
||||||
|
Net clk_000_cnt_i_0__n CLK_000_CNT_i[0]
|
||||||
|
Net clk_cpu_est_11_3__n clk.cpu_est_11[3]
|
||||||
|
Net clk_000_cnt_i_3__n CLK_000_CNT_i[3]
|
||||||
|
Net clk_000_cnt_i_2__n CLK_000_CNT_i[2]
|
||||||
|
Net state_machine_un69_clk_000_d_0_n state_machine.un69_clk_000_d_0
|
||||||
|
Net state_machine_un69_clk_000_d_0_1_n state_machine.un69_clk_000_d_0_1
|
||||||
|
Net clk_cpu_est_11_1__n clk.cpu_est_11[1]
|
||||||
|
Net state_machine_un69_clk_000_d_0_2_n state_machine.un69_clk_000_d_0_2
|
||||||
|
Net state_machine_un25_clk_000_d_i_1_n state_machine.un25_clk_000_d_i_1
|
||||||
|
Net state_machine_as_030_000_sync_3_2_1_n state_machine.AS_030_000_SYNC_3_2_1
|
||||||
|
Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3]
|
||||||
|
Net clk_cpu_est_11_0_1_1__n clk.cpu_est_11_0_1[1]
|
||||||
|
Net clk_cpu_est_11_0_2_1__n clk.cpu_est_11_0_2[1]
|
||||||
|
Net cpu_est_i_0__n cpu_est_i[0]
|
||||||
|
Net cpu_est_i_2__n cpu_est_i[2]
|
||||||
|
Net cpu_est_i_3__n cpu_est_i[3]
|
||||||
|
Net cpu_est_i_1__n cpu_est_i[1]
|
||||||
|
Net state_machine_un42_clk_030_1_n state_machine.un42_clk_030_1
|
||||||
|
Net sm_amiga_i_4__n SM_AMIGA_i[4]
|
||||||
|
Net state_machine_un42_clk_030_2_n state_machine.un42_clk_030_2
|
||||||
|
Net sm_amiga_i_6__n SM_AMIGA_i[6]
|
||||||
|
Net state_machine_un42_clk_030_3_n state_machine.un42_clk_030_3
|
||||||
|
Net sm_amiga_i_5__n SM_AMIGA_i[5]
|
||||||
|
Net state_machine_un42_clk_030_4_n state_machine.un42_clk_030_4
|
||||||
|
Net state_machine_un42_clk_030_5_n state_machine.un42_clk_030_5
|
||||||
|
Net state_machine_un15_clk_000_d_i_n state_machine.un15_clk_000_d_i
|
||||||
|
Net sm_amiga_i_0__n SM_AMIGA_i[0]
|
||||||
|
Net sm_amiga_i_7__n SM_AMIGA_i[7]
|
||||||
|
Net dsack_i_1__n DSACK_i[1]
|
||||||
|
Net a_i_18__n A_i[18]
|
||||||
|
Net a_i_16__n A_i[16]
|
||||||
|
Net a_i_19__n A_i[19]
|
||||||
|
Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i
|
||||||
|
Net cpu_est_0_1__un3_n cpu_est_0_1_.un3
|
||||||
|
Net cpu_est_0_1__un1_n cpu_est_0_1_.un1
|
||||||
|
Net sm_amiga_i_2__n SM_AMIGA_i[2]
|
||||||
|
Net cpu_est_0_1__un0_n cpu_est_0_1_.un0
|
||||||
|
Net sm_amiga_i_1__n SM_AMIGA_i[1]
|
||||||
|
Net vma_int_0_un3_n VMA_INT_0.un3
|
||||||
|
Net sm_amiga_i_3__n SM_AMIGA_i[3]
|
||||||
|
Net vma_int_0_un1_n VMA_INT_0.un1
|
||||||
|
Net vma_int_0_un0_n VMA_INT_0.un0
|
||||||
|
Net a_i_30__n A_i[30]
|
||||||
|
Net cpu_est_0_3__un3_n cpu_est_0_3_.un3
|
||||||
|
Net a_i_31__n A_i[31]
|
||||||
|
Net cpu_est_0_3__un1_n cpu_est_0_3_.un1
|
||||||
|
Net a_i_28__n A_i[28]
|
||||||
|
Net cpu_est_0_3__un0_n cpu_est_0_3_.un0
|
||||||
|
Net a_i_29__n A_i[29]
|
||||||
|
Net cpu_est_0_2__un3_n cpu_est_0_2_.un3
|
||||||
|
Net a_i_26__n A_i[26]
|
||||||
|
Net cpu_est_0_2__un1_n cpu_est_0_2_.un1
|
||||||
|
Net a_i_27__n A_i[27]
|
||||||
|
Net cpu_est_0_2__un0_n cpu_est_0_2_.un0
|
||||||
|
Net a_i_24__n A_i[24]
|
||||||
|
Net dtack_sync_0_un3_n DTACK_SYNC_0.un3
|
||||||
|
Net a_i_25__n A_i[25]
|
||||||
|
Net dtack_sync_0_un1_n DTACK_SYNC_0.un1
|
||||||
|
Net clk_cnt_i_0__n CLK_CNT_i[0]
|
||||||
|
Net dtack_sync_0_un0_n DTACK_SYNC_0.un0
|
||||||
|
Net state_machine_un14_as_000_int_i_n state_machine.un14_as_000_int_i
|
||||||
|
Net sm_amiga_d_0_0__un3_n SM_AMIGA_D_0_0_.un3
|
||||||
|
Net sm_amiga_d_0_0__un1_n SM_AMIGA_D_0_0_.un1
|
||||||
|
Net un1_clk_000_cnt_i_3__n un1_CLK_000_CNT_i[3]
|
||||||
|
Net sm_amiga_d_0_0__un0_n SM_AMIGA_D_0_0_.un0
|
||||||
|
Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3
|
||||||
|
Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1
|
||||||
|
Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0
|
||||||
|
Net bg_000_0_un3_n BG_000_0.un3
|
||||||
|
Net bg_000_0_un1_n BG_000_0.un1
|
||||||
|
Net bg_000_0_un0_n BG_000_0.un0
|
||||||
|
Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3
|
||||||
|
Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1
|
||||||
|
Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0
|
||||||
|
Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3
|
||||||
|
Net size_c_0__n SIZE_c[0]
|
||||||
|
Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1
|
||||||
|
Net size_0__n SIZE[0]
|
||||||
|
Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0
|
||||||
|
Net size_c_1__n SIZE_c[1]
|
||||||
|
Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3
|
||||||
|
Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1
|
||||||
|
Net a_c_0__n A_c[0]
|
||||||
|
Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0
|
||||||
|
Net a_0__n A[0]
|
||||||
|
Net vpa_sync_0_un3_n VPA_SYNC_0.un3
|
||||||
|
Net vpa_sync_0_un1_n VPA_SYNC_0.un1
|
||||||
|
Net vpa_sync_0_un0_n VPA_SYNC_0.un0
|
||||||
|
Net as_000_int_0_un3_n AS_000_INT_0.un3
|
||||||
|
Net as_000_int_0_un1_n AS_000_INT_0.un1
|
||||||
|
Net as_000_int_0_un0_n AS_000_INT_0.un0
|
||||||
|
Net ipl_030_0_2__un3_n IPL_030_0_2_.un3
|
||||||
|
Net ipl_030_0_2__un1_n IPL_030_0_2_.un1
|
||||||
|
Net ipl_030_0_2__un0_n IPL_030_0_2_.un0
|
||||||
|
Net ipl_030_0_1__un3_n IPL_030_0_1_.un3
|
||||||
|
Net ipl_030_0_1__un1_n IPL_030_0_1_.un1
|
||||||
|
Net ipl_030_0_1__un0_n IPL_030_0_1_.un0
|
||||||
|
Net ipl_030_0_0__un3_n IPL_030_0_0_.un3
|
||||||
|
Net ipl_030_0_0__un1_n IPL_030_0_0_.un1
|
||||||
|
Net ipl_030_0_0__un0_n IPL_030_0_0_.un0
|
||||||
|
Net sm_amiga_d_0_2__un3_n SM_AMIGA_D_0_2_.un3
|
||||||
|
Net a_c_16__n A_c[16]
|
||||||
|
Net sm_amiga_d_0_2__un1_n SM_AMIGA_D_0_2_.un1
|
||||||
|
Net a_16__n A[16]
|
||||||
|
Net sm_amiga_d_0_2__un0_n SM_AMIGA_D_0_2_.un0
|
||||||
|
Net a_c_17__n A_c[17]
|
||||||
|
Net sm_amiga_d_0_1__un3_n SM_AMIGA_D_0_1_.un3
|
||||||
|
Net a_17__n A[17]
|
||||||
|
Net sm_amiga_d_0_1__un1_n SM_AMIGA_D_0_1_.un1
|
||||||
|
Net a_c_18__n A_c[18]
|
||||||
|
Net sm_amiga_d_0_1__un0_n SM_AMIGA_D_0_1_.un0
|
||||||
|
Net a_18__n A[18]
|
||||||
|
Net lds_000_int_0_un3_n LDS_000_INT_0.un3
|
||||||
|
Net a_c_19__n A_c[19]
|
||||||
|
Net lds_000_int_0_un1_n LDS_000_INT_0.un1
|
||||||
|
Net a_19__n A[19]
|
||||||
|
Net lds_000_int_0_un0_n LDS_000_INT_0.un0
|
||||||
|
Net a_c_20__n A_c[20]
|
||||||
|
Net uds_000_int_0_un3_n UDS_000_INT_0.un3
|
||||||
|
Net a_20__n A[20]
|
||||||
|
Net uds_000_int_0_un1_n UDS_000_INT_0.un1
|
||||||
|
Net a_c_21__n A_c[21]
|
||||||
|
Net uds_000_int_0_un0_n UDS_000_INT_0.un0
|
||||||
|
End
|
||||||
|
Section Type Name
|
||||||
|
// ----------------------------------------------------------------------
|
||||||
|
Input SIZE_1_
|
||||||
|
Input A_31_
|
||||||
|
Input IPL_2_
|
||||||
|
Input FC_1_
|
||||||
|
Input AS_030
|
||||||
|
Input DS_030
|
||||||
|
Input CPU_SPACE
|
||||||
|
Input BG_030
|
||||||
|
Input BGACK_000
|
||||||
|
Input CLK_030
|
||||||
|
Input CLK_000
|
||||||
|
Input CLK_OSZI
|
||||||
|
Input VPA
|
||||||
|
Input RST
|
||||||
|
Input RW
|
||||||
|
Input SIZE_0_
|
||||||
|
Input A_30_
|
||||||
|
Input A_29_
|
||||||
|
Input A_28_
|
||||||
|
Input A_27_
|
||||||
|
Input A_26_
|
||||||
|
Input A_25_
|
||||||
|
Input A_24_
|
||||||
|
Input A_23_
|
||||||
|
Input A_22_
|
||||||
|
Input A_21_
|
||||||
|
Input A_20_
|
||||||
|
Input A_19_
|
||||||
|
Input A_18_
|
||||||
|
Input A_17_
|
||||||
|
Input A_16_
|
||||||
|
Input A_15_
|
||||||
|
Input A_14_
|
||||||
|
Input A_13_
|
||||||
|
Input A_12_
|
||||||
|
Input A_11_
|
||||||
|
Input A_10_
|
||||||
|
Input A_9_
|
||||||
|
Input A_8_
|
||||||
|
Input A_7_
|
||||||
|
Input A_6_
|
||||||
|
Input A_5_
|
||||||
|
Input A_4_
|
||||||
|
Input A_3_
|
||||||
|
Input A_2_
|
||||||
|
Input A_1_
|
||||||
|
Input A_0_
|
||||||
|
Input IPL_1_
|
||||||
|
Input IPL_0_
|
||||||
|
Input FC_0_
|
||||||
|
Output IPL_030_2_
|
||||||
|
Output AS_000
|
||||||
|
Output UDS_000
|
||||||
|
Output LDS_000
|
||||||
|
Output BERR
|
||||||
|
Output BG_000
|
||||||
|
Output BGACK_030
|
||||||
|
Output CLK_DIV_OUT
|
||||||
|
Output CLK_EXP
|
||||||
|
Output FPU_CS
|
||||||
|
Output AVEC
|
||||||
|
Output AVEC_EXP
|
||||||
|
Output E
|
||||||
|
Output VMA
|
||||||
|
Output RESET
|
||||||
|
Output AMIGA_BUS_ENABLE
|
||||||
|
Output AMIGA_BUS_DATA_DIR
|
||||||
|
Output AMIGA_BUS_ENABLE_LOW
|
||||||
|
Output CIIN
|
||||||
|
Output IPL_030_1_
|
||||||
|
Output IPL_030_0_
|
||||||
|
Bidi DSACK_1_
|
||||||
|
Bidi DTACK
|
||||||
|
Bidi DSACK_0_
|
||||||
|
End
|
|
@ -0,0 +1,94 @@
|
||||||
|
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
|
||||||
|
#install: C:\Program Files (x86)\ispLever\synpbase
|
||||||
|
#OS: Windows 7 6.1
|
||||||
|
#Hostname: DEEPTHOUGHT
|
||||||
|
|
||||||
|
#Implementation: logic
|
||||||
|
|
||||||
|
$ Start of Compile
|
||||||
|
#Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||||
|
@N|Running in 64-bit mode
|
||||||
|
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||||
|
|
||||||
|
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||||
|
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030.
|
||||||
|
File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
|
VHDL syntax check successful!
|
||||||
|
File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
|
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral
|
||||||
|
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven
|
||||||
|
Post processing for work.bus68030.behavioral
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA
|
||||||
|
@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
||||||
|
@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0)
|
||||||
|
@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ...
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA
|
||||||
|
Extracted state machine for register SM_AMIGA
|
||||||
|
State machine has 8 reachable states with original encodings of:
|
||||||
|
000
|
||||||
|
001
|
||||||
|
010
|
||||||
|
011
|
||||||
|
100
|
||||||
|
101
|
||||||
|
110
|
||||||
|
111
|
||||||
|
@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA
|
||||||
|
@END
|
||||||
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
|
# Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
###########################################################]
|
||||||
|
Map & Optimize Report
|
||||||
|
|
||||||
|
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
||||||
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||||
|
Product Version G-2012.09LC-SP1
|
||||||
|
@N: MF248 |Running in 64-bit mode.
|
||||||
|
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||||
|
original code -> new code
|
||||||
|
000 -> 00000001
|
||||||
|
001 -> 00000010
|
||||||
|
010 -> 00000100
|
||||||
|
011 -> 00001000
|
||||||
|
100 -> 00010000
|
||||||
|
101 -> 00100000
|
||||||
|
110 -> 01000000
|
||||||
|
111 -> 10000000
|
||||||
|
@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
|
---------------------------------------
|
||||||
|
Resource Usage Report
|
||||||
|
|
||||||
|
Simple gate primitives:
|
||||||
|
DFFRH 7 uses
|
||||||
|
DFF 19 uses
|
||||||
|
DFFSH 16 uses
|
||||||
|
IBUF 35 uses
|
||||||
|
BUFTH 7 uses
|
||||||
|
OBUF 15 uses
|
||||||
|
BI_DIR 2 uses
|
||||||
|
AND2 179 uses
|
||||||
|
INV 143 uses
|
||||||
|
OR2 20 uses
|
||||||
|
XOR2 8 uses
|
||||||
|
|
||||||
|
|
||||||
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
|
G-2012.09LC-SP1
|
||||||
|
Mapper successful!
|
||||||
|
|
||||||
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
||||||
|
|
||||||
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
|
# Thu May 15 19:20:48 2014
|
||||||
|
|
||||||
|
###########################################################]
|
|
@ -0,0 +1,37 @@
|
||||||
|
%%% protect protected_file
|
||||||
|
@EG<?lPDRCHs#F"M=4"3jROCMFM8Hok="0UV-"
|
||||||
|
?>
|
||||||
|
-<!-7R]pHR]CssNORE$7HCVMHH0FwMRHRDCwlFsN-0R-<>
|
||||||
|
]17p0Osk0CksRsPC#MHF=3"4j
|
||||||
|
">
|
||||||
|
!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
|
||||||
|
<k1Fs#OC>S
|
||||||
|
S<k1FsROCbB=":s\uFNoslHRwDRC#5nGU2#\HbPpCC#s\$LMbN\#CD\HLP\E8#308P"E8R"N=jD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||||
|
/>S1S<FOksC=Rb"\B:uosFsRNlwCHD#GR5U\n2Hp#bCsPC\M#$b#LNCH\DLE\P8M\#bE#_N_b#b3 oP"E8R"N=4D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||||
|
/>S1S<FOksC=Rb"\B:uosFsRNlwCHD#GR5U\n2Hp#bCsPC\M#$b#LNCH\DLE\P80\#8n44cE3P8N"R="".R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
|
||||||
|
S<k1FsROCbB=":s\uFNoslHRwDRC#5nGU2#\HbPpCC#s\$LMbN\#CD\HLP\E8MCkls3HOP"E8R"N=dD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||||
|
/>S1S<FOksC=Rb"\B:uosFsRNlwCHD#GR5U\n2Hp#bCsPC\M#$b#LNCH\DLE\P8l\ksN_Ob3HlP"E8R"N=cD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||||
|
/>S1S<FOksC=Rb"\B:uosFsRNlwCHD#GR5U\n2Hp#bCsPC\M#$b#LNCH\DLE\P8s\NH30EP"E8R"N=6D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||||
|
/>S1S<FOksC=Rb"\B:uosFsRNlwCHD#GR5U\n2Hp#bCsPC\M#$b#LNCH\DLE\P8M\k#MHoCP83ER8"Nn=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
|
||||||
|
SF<1kCsOR"b=Bk:\##Cs\0lNxNC\lNHo\sEN8sINCOEN n#\Ujjd-\0 DHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4"><
|
||||||
|
S/k1Fs#OC>S
|
||||||
|
|
||||||
|
<-!-R8vFkRDCs0FFR>--
|
||||||
|
)S<FRF0MI="F3s Anz1Ujjd3ELCNFPHs"ND/
|
||||||
|
>
|
||||||
|
|
||||||
|
<
|
||||||
|
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||||
|
S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
|
||||||
|
SR<WN(=""DRL=""nR=LO"R("C"D=nC"RO4="c/"R>S
|
||||||
|
S<MqR=N"3sVOEH"DCR"P=(>"/
|
||||||
|
<SSq=RM"F3l8CkDVCHD"=RP"/(">S
|
||||||
|
S<MqR=O"3F0M#N_M0s"CoR"P=&FJk01;7q_BiQrhaj49R
|
||||||
|
iBp_aBhrR49jk&JF"0;/S>
|
||||||
|
SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
|
||||||
|
/>SqS<R"M=3HFsolhNCP"R=J"&k;F0Anz1Ujjd&FJk0/;">
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/S<7>CV
|
||||||
|
]</70p1s0kOk>sC
|
|
@ -0,0 +1 @@
|
||||||
|
-src 68030_tk.tt4 -type PLA -devfile "C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4"
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1 @@
|
||||||
|
-global -lci 68030_tk.lct -touch 68030_tk.imp
|
|
@ -0,0 +1,52 @@
|
||||||
|
#-- Synopsys, Inc.
|
||||||
|
#-- Version G-2012.09LC-SP1
|
||||||
|
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\logic\run_options.txt
|
||||||
|
#-- Written on Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
|
||||||
|
#project files
|
||||||
|
add_file -vhdl -lib work "./68030-68000-bus.vhd"
|
||||||
|
|
||||||
|
|
||||||
|
#implementation: "logic"
|
||||||
|
impl -add logic -type fpga
|
||||||
|
|
||||||
|
#device options
|
||||||
|
set_option -technology mach
|
||||||
|
set_option -part M4A5-128
|
||||||
|
set_option -package ""
|
||||||
|
set_option -speed_grade ""
|
||||||
|
set_option -part_companion ""
|
||||||
|
|
||||||
|
#compilation/mapping options
|
||||||
|
set_option -top_module "BUS68030"
|
||||||
|
|
||||||
|
# mapper_options
|
||||||
|
set_option -frequency 1
|
||||||
|
set_option -write_verilog 0
|
||||||
|
set_option -write_vhdl 0
|
||||||
|
set_option -srs_instrumentation 1
|
||||||
|
|
||||||
|
# Lattice ispMACH4000
|
||||||
|
set_option -maxfanin 20
|
||||||
|
set_option -RWCheckOnRam 1
|
||||||
|
set_option -maxterms 16
|
||||||
|
set_option -areadelay 0
|
||||||
|
set_option -disable_io_insertion 0
|
||||||
|
|
||||||
|
# sequential_optimization_options
|
||||||
|
set_option -symbolic_fsm_compiler 1
|
||||||
|
|
||||||
|
# Compiler Options
|
||||||
|
set_option -compiler_compatible 0
|
||||||
|
set_option -resource_sharing 1
|
||||||
|
|
||||||
|
#automatic place and route (vendor) options
|
||||||
|
set_option -write_apr_constraint 1
|
||||||
|
|
||||||
|
#set result format/file last
|
||||||
|
project -result_file "./BUS68030.edi"
|
||||||
|
|
||||||
|
#set log file
|
||||||
|
set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/bus68030.srf"
|
||||||
|
impl -active "logic"
|
|
@ -0,0 +1,50 @@
|
||||||
|
#-- Synopsys, Inc.
|
||||||
|
#-- Version G-2012.09LC-SP1
|
||||||
|
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\logic\scratchproject.prs
|
||||||
|
|
||||||
|
#project files
|
||||||
|
add_file -vhdl -lib work "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/68030-68000-bus.vhd"
|
||||||
|
|
||||||
|
|
||||||
|
#implementation: "logic"
|
||||||
|
impl -add C:\users\matze\amiga\hardwarehacks\68030-tk\logic -type fpga
|
||||||
|
|
||||||
|
#device options
|
||||||
|
set_option -technology mach
|
||||||
|
set_option -part M4A5-128
|
||||||
|
set_option -package ""
|
||||||
|
set_option -speed_grade ""
|
||||||
|
set_option -part_companion ""
|
||||||
|
|
||||||
|
#compilation/mapping options
|
||||||
|
set_option -top_module "BUS68030"
|
||||||
|
|
||||||
|
# mapper_options
|
||||||
|
set_option -frequency 1
|
||||||
|
set_option -write_verilog 0
|
||||||
|
set_option -write_vhdl 0
|
||||||
|
set_option -srs_instrumentation 1
|
||||||
|
|
||||||
|
# Lattice ispMACH4000
|
||||||
|
set_option -maxfanin 20
|
||||||
|
set_option -RWCheckOnRam 1
|
||||||
|
set_option -maxterms 16
|
||||||
|
set_option -areadelay 0
|
||||||
|
set_option -disable_io_insertion 0
|
||||||
|
|
||||||
|
# sequential_optimization_options
|
||||||
|
set_option -symbolic_fsm_compiler 1
|
||||||
|
|
||||||
|
# Compiler Options
|
||||||
|
set_option -compiler_compatible 0
|
||||||
|
set_option -resource_sharing 1
|
||||||
|
|
||||||
|
#automatic place and route (vendor) options
|
||||||
|
set_option -write_apr_constraint 1
|
||||||
|
|
||||||
|
#set result format/file last
|
||||||
|
project -result_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/BUS68030.edi"
|
||||||
|
|
||||||
|
#set log file
|
||||||
|
set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/bus68030.srf"
|
||||||
|
impl -active "logic"
|
|
@ -0,0 +1,39 @@
|
||||||
|
ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||||
|
DIOEDA_ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||||
|
DIOEDA_ActiveHDL=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||||
|
DIOEDA_ActiveHDLPath=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||||
|
DIOEDA_AppNotes=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||||
|
DIOEDA_Bin=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||||
|
DIOEDA_Config=C:\Program Files (x86)\ispLever\ispcpld\config
|
||||||
|
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||||
|
DIOEDA_DSPPATH=C:\Program Files (x86)\ispLever\ispLeverDSP
|
||||||
|
DIOEDA_EPICPATH=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||||
|
DIOEDA_Examples=C:\Program Files (x86)\ispLever\examples
|
||||||
|
DIOEDA_FPGABinPath=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||||
|
DIOEDA_FPGAPath=C:\Program Files (x86)\ispLever\ispfpga
|
||||||
|
DIOEDA_HDLExplorer=C:\Program Files (x86)\ispLever\hdle\win32
|
||||||
|
DIOEDA_INI=C:\lsc_env
|
||||||
|
DIOEDA_ispVM=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||||
|
DIOEDA_ispVMSystem=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||||
|
DIOEDA_License=C:\Program Files (x86)\ispLever\license
|
||||||
|
DIOEDA_MachPath=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||||
|
DIOEDA_Manuals=C:\Program Files (x86)\ispLever\ispcpld\manuals
|
||||||
|
DIOEDA_ModelSim=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||||
|
DIOEDA_ModelsimPath=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||||
|
DIOEDA_PDSPath=C:\Program Files (x86)\ispLever\ispcomp
|
||||||
|
DIOEDA_Precision=C:\isptools\precision
|
||||||
|
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||||
|
DIOEDA_ProductName=ispLEVER
|
||||||
|
DIOEDA_ProductPrefix=SYN
|
||||||
|
DIOEDA_ProductTitle=ispLEVER
|
||||||
|
DIOEDA_ProductType=1.7.00.05.28.13_LS_HDL_BASE_PC_N
|
||||||
|
DIOEDA_ProductVersion=1.7.00.05
|
||||||
|
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.7
|
||||||
|
DIOEDA_Root=C:\Program Files (x86)\ispLever\ispcpld
|
||||||
|
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||||
|
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||||
|
DIOEDA_Synplify=C:\Program Files (x86)\ispLever\synpbase
|
||||||
|
DIOEDA_SynplifyPath=C:\Program Files (x86)\ispLever\synpbase
|
||||||
|
DIOEDA_Tutorial=C:\Program Files (x86)\ispLever\ispcpld\tutorial
|
||||||
|
DIOPRODUCT=ispLEVER
|
||||||
|
PATH=C:\Program Files (x86)\ispLever\ispcpld\bin
|
|
@ -0,0 +1,42 @@
|
||||||
|
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
||||||
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||||
|
Product Version G-2012.09LC-SP1
|
||||||
|
@N: MF248 |Running in 64-bit mode.
|
||||||
|
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||||
|
original code -> new code
|
||||||
|
000 -> 00000001
|
||||||
|
001 -> 00000010
|
||||||
|
010 -> 00000100
|
||||||
|
011 -> 00001000
|
||||||
|
100 -> 00010000
|
||||||
|
101 -> 00100000
|
||||||
|
110 -> 01000000
|
||||||
|
111 -> 10000000
|
||||||
|
@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
|
---------------------------------------
|
||||||
|
Resource Usage Report
|
||||||
|
|
||||||
|
Simple gate primitives:
|
||||||
|
DFFRH 7 uses
|
||||||
|
DFF 19 uses
|
||||||
|
DFFSH 16 uses
|
||||||
|
IBUF 35 uses
|
||||||
|
BUFTH 7 uses
|
||||||
|
OBUF 15 uses
|
||||||
|
BI_DIR 2 uses
|
||||||
|
AND2 179 uses
|
||||||
|
INV 143 uses
|
||||||
|
OR2 20 uses
|
||||||
|
XOR2 8 uses
|
||||||
|
|
||||||
|
|
||||||
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
|
G-2012.09LC-SP1
|
||||||
|
Mapper successful!
|
||||||
|
|
||||||
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
||||||
|
|
||||||
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
|
# Thu May 15 19:20:48 2014
|
||||||
|
|
||||||
|
###########################################################]
|
|
@ -0,0 +1,3 @@
|
||||||
|
@E: CS187 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":300:12:300:12|Expecting <=
|
||||||
|
@E|Parse errors encountered - exiting
|
||||||
|
|
|
@ -0,0 +1,7 @@
|
||||||
|
@N|Running in 64-bit mode
|
||||||
|
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||||
|
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030.
|
||||||
|
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA
|
||||||
|
|
|
@ -0,0 +1,41 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||||||
|
<!-- *************************************************************************************
|
||||||
|
FILE DESCRIPTION
|
||||||
|
The file contains the job information from compiler to be displayed as part of the summary report.
|
||||||
|
*******************************************************************************************-->
|
||||||
|
|
||||||
|
<job_run_status name="compiler">
|
||||||
|
<report_link name="Detailed report">
|
||||||
|
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\BUS68030.srr</data>
|
||||||
|
<title>$ Start of Compile</title>
|
||||||
|
</report_link>
|
||||||
|
<job_status>
|
||||||
|
<data>Completed </data>
|
||||||
|
</job_status>
|
||||||
|
<job_info>
|
||||||
|
<info name="Notes">
|
||||||
|
<data>6</data>
|
||||||
|
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||||
|
</info>
|
||||||
|
<info name="Warnings">
|
||||||
|
<data>11</data>
|
||||||
|
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||||
|
</info>
|
||||||
|
<info name="Errors">
|
||||||
|
<data>0</data>
|
||||||
|
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_errors.txt</data></report_link>
|
||||||
|
</info>
|
||||||
|
<info name="CPU Time">
|
||||||
|
<data>-</data>
|
||||||
|
</info>
|
||||||
|
<info name="Real Time">
|
||||||
|
<data>0h:00m:00s</data>
|
||||||
|
</info>
|
||||||
|
<info name="Peak Memory">
|
||||||
|
<data>-</data>
|
||||||
|
</info>
|
||||||
|
<info name="Date &Time">
|
||||||
|
<data type="timestamp">1400174446</data>
|
||||||
|
</info>
|
||||||
|
</job_info>
|
||||||
|
</job_run_status>
|
|
@ -0,0 +1,12 @@
|
||||||
|
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA
|
||||||
|
@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0)
|
||||||
|
@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ...
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
|
||||||
|
@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA
|
||||||
|
|
|
@ -0,0 +1,3 @@
|
||||||
|
@N: MF248 |Running in 64-bit mode.
|
||||||
|
@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
|
@ -0,0 +1,45 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||||||
|
<!-- *************************************************************************************
|
||||||
|
FILE DESCRIPTION
|
||||||
|
The file contains the job information from mapper to be displayed as part of the summary report.
|
||||||
|
*******************************************************************************************-->
|
||||||
|
<job_run_status name="Mapper">
|
||||||
|
<report_link name="Detailed report">
|
||||||
|
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\BUS68030_fpga_mapper.srr</data>
|
||||||
|
</report_link>
|
||||||
|
<job_status>
|
||||||
|
<data>Completed</data>
|
||||||
|
</job_status>
|
||||||
|
<job_info>
|
||||||
|
<info name="Notes">
|
||||||
|
<data>3</data>
|
||||||
|
<report_link name="more">
|
||||||
|
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt</data>
|
||||||
|
</report_link>
|
||||||
|
</info>
|
||||||
|
<info name="Warnings">
|
||||||
|
<data>0</data>
|
||||||
|
<report_link name="more">
|
||||||
|
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||||
|
</report_link>
|
||||||
|
</info>
|
||||||
|
<info name="Errors">
|
||||||
|
<data>0</data>
|
||||||
|
<report_link name="more">
|
||||||
|
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_errors.txt</data>
|
||||||
|
</report_link>
|
||||||
|
</info>
|
||||||
|
<info name="CPU Time">
|
||||||
|
<data>0h:00m:00s</data>
|
||||||
|
</info>
|
||||||
|
<info name="Real Time">
|
||||||
|
<data>0h:00m:00s</data>
|
||||||
|
</info>
|
||||||
|
<info name="Peak Memory">
|
||||||
|
<data>95MB</data>
|
||||||
|
</info>
|
||||||
|
<info name="Date & Time">
|
||||||
|
<data type="timestamp">1400174448</data>
|
||||||
|
</info>
|
||||||
|
</job_info>
|
||||||
|
</job_run_status>
|
|
@ -0,0 +1,18 @@
|
||||||
|
<?xml version="1.0" encoding="utf-8"?>
|
||||||
|
<!--
|
||||||
|
Synopsys, Inc.
|
||||||
|
Version G-2012.09LC-SP1
|
||||||
|
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\logic\syntmp\run_option.xml
|
||||||
|
Written on Thu May 15 19:20:46 2014
|
||||||
|
|
||||||
|
|
||||||
|
-->
|
||||||
|
<project_attribute_list name="Project Settings">
|
||||||
|
<option name="project_name" display_name="Project Name">BUS68030</option>
|
||||||
|
<option name="impl_name" display_name="Implementation Name">logic</option>
|
||||||
|
<option name="top_module" display_name="Top Module">BUS68030</option>
|
||||||
|
<option name="resource_sharing" display_name="Resource Sharing">1</option>
|
||||||
|
<option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
|
||||||
|
<option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
|
||||||
|
</project_attribute_list>
|
||||||
|
|
|
@ -0,0 +1,28 @@
|
||||||
|
%%% protect protected_file
|
||||||
|
#defaultlanguage:vhdl
|
||||||
|
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work"
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363693660
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||||
|
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\logic\\68030-68000-bus.vhd":1400174441
|
||||||
|
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
|
# Dependency Lists (Uses list)
|
||||||
|
0 -1
|
||||||
|
|
||||||
|
# Dependency Lists (Users Of)
|
||||||
|
0 -1
|
||||||
|
|
||||||
|
# Design Unit to File Association
|
||||||
|
arch work bus68030 behavioral 0
|
||||||
|
module work bus68030 0
|
||||||
|
|
||||||
|
|
||||||
|
# Configuration files used
|
||||||
|
0 -1
|
|
@ -0,0 +1,24 @@
|
||||||
|
%%% protect protected_file
|
||||||
|
#defaultlanguage:vhdl
|
||||||
|
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work"
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363693660
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||||
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||||
|
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\logic\\68030-68000-bus.vhd":1400174441
|
||||||
|
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
|
# Dependency Lists (Uses list)
|
||||||
|
0 -1
|
||||||
|
|
||||||
|
# Dependency Lists (Users Of)
|
||||||
|
0 -1
|
||||||
|
|
||||||
|
# Design Unit to File Association
|
||||||
|
arch work bus68030 behavioral 0
|
||||||
|
module work bus68030 0
|
Binary file not shown.
|
@ -0,0 +1,26 @@
|
||||||
|
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral
|
||||||
|
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven
|
||||||
|
Post processing for work.bus68030.behavioral
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0)
|
||||||
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START
|
||||||
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0)
|
||||||
|
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA
|
||||||
|
@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
||||||
|
@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0)
|
||||||
|
@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ...
|
||||||
|
@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est
|
||||||
|
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA
|
||||||
|
Extracted state machine for register SM_AMIGA
|
||||||
|
State machine has 8 reachable states with original encodings of:
|
||||||
|
000
|
||||||
|
001
|
||||||
|
010
|
||||||
|
011
|
||||||
|
100
|
||||||
|
101
|
||||||
|
110
|
||||||
|
111
|
||||||
|
@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA
|
|
@ -0,0 +1,18 @@
|
||||||
|
This project consists of an layout and PCB of an CPU replacement board for 68000-DIP based Systems. Its basicly build for an Amiga but could be used elsewhere.
|
||||||
|
|
||||||
|
The hardware manly solves these tasks:
|
||||||
|
|
||||||
|
FPU integration
|
||||||
|
Adaptation of the 68030-protocoll to the 68000-protocoll
|
||||||
|
E-Clock-Generation
|
||||||
|
DMA-Bussizing for 16-bit DMA access
|
||||||
|
An expansionport for further developement
|
||||||
|
|
||||||
|
It contains two folders:
|
||||||
|
|
||||||
|
1. a PCB for the Hardware
|
||||||
|
2. a Logic core for the adaptation
|
||||||
|
|
||||||
|
Have fun developping it!
|
||||||
|
|
||||||
|
Matthias Heinrichs
|
Loading…
Reference in New Issue