The I/N bit in the special status word on the stack should be set
when returning from RTE results in a PC that isn't word aligned.
Every other case pretty much, it should be clear
Adjusted the PC value stored when an Address Error fault occurs to
use the size of the access operation.
I also flipped the IN bit in the word that's written to the top of
the stack on an AddressError, even though that's opposite of what
the docs say. It seems to pass the tests. I probably have something
else going wrong, but it shouldn't be an important bit either way.
Added support for RTR and RESET.
Fixed flags behavior for ASd
Added function to set PC, and fixed some instruction's handling of
an address fault a bit better
Some debug code was enabled that prevented illegal instructions
from being handled normally with a processor exception
The brief instruction word decoding could cause an illegal instruction
if it didn't match the docs, but the actual implementation would not
complain in those cases, so I modified it to not perform validation
for <=MC68010
Increment and Decrement addressing modes, when using the stack pointer,
will always inc/dec by at least 2 bytes, even if it's a byte operation,
to keep the stack aligned to the nearest word boundary
For instructions that use an operand twice, where it called
get_target_value and set_target_value, if the addressing mode was
one where it would increment or decrement a pointer, it was
causing a double inc/dec because of the two calls to get/set target.
I added an argument to let the functions know if they will be called
twice, in which case it assumes that get will be the first and set
will be the second, and inc/decs only once in the appropriate function
for whether it pre-incs or post-decs
Previously it would show a dump of whatever device was next scheduled
to step, if it was Debuggable, but now each debuggable device has a
flag for whether that device is being debugging, and a system flag
to disable it entirely. When the system flag is set, it will try
to enable debugging on the device labelled "cpu". I need to also add
a way of setting a breakpoint on a named device, which will enable
debugging of that device
It was previously decrementing addresses if the direction was from
registers to memory, but that's incorrect. It should increment the
address always when using an addressing mode other than the ARecDec
mode. I also added a memory location to the test cases to test the
MOVEM instruction by comparing what memory was read/written (but it's
only one u32 because that's the minimum we need)
Previously the m68k wasn't masking interrupts with an equal priorty.
I also modified how they work, such that the cpus will check the
controller rather than wait for the notification call
The BusPort is created before the CPU and is passed to it. It can
have an offset, limit the address sizes, and break up bus request
beyond a certain number of bytes into multiple requests
