transistor
4bdbe7c7f0
Refactored a bit
...
Now all traits are in the devices file, and host adapters will be
in under src/host/.
2021-10-16 20:30:50 -07:00
transistor
93c9307829
Moved I/O to a separate thread
...
but I'm not happy with it, and will likely change it in future,
possibly to use two threads and two sets of channels to pass chars
back and forth
2021-10-16 16:11:50 -07:00
transistor
853626584e
Once again modified how the memory addressing works
2021-10-16 10:58:27 -07:00
transistor
24e050a840
Added supervisor checks
2021-10-16 10:01:14 -07:00
transistor
ffd4faa9a3
Fixed decode of EXT, and fixed some bugs with 020+ code
2021-10-15 14:37:31 -07:00
transistor
1732c90f5b
Added formatter for Instruction to output assembly
2021-10-15 11:12:47 -07:00
transistor
eba1f9c9fc
Fixed bug with ANDtoSR, which was actually using "or"
2021-10-14 22:04:14 -07:00
transistor
72457aca5c
Minor changes
2021-10-14 21:53:42 -07:00
transistor
43b1abfa19
Minor changes
2021-10-14 21:16:31 -07:00
transistor
e558fc01bf
Refactored and fixed some warnings
2021-10-11 15:16:04 -07:00
transistor
91825e1cb9
Added a bunch of unit tests
2021-10-11 15:04:39 -07:00
transistor
39ecd1b0d9
Added decode for ABCD and SBCD
2021-10-10 20:47:51 -07:00
transistor
94141e112e
Reorganized decode and add some support for other m68k processors
2021-10-10 14:26:54 -07:00
transistor
b588563acc
Updated readme
2021-10-09 20:35:52 -07:00
transistor
fbb5153121
Refactored mc68681 to make a common port struct and fixed a bug in DIV
2021-10-09 17:35:23 -07:00
transistor
f0637e81f1
Added separate interrupt controller
2021-10-09 11:00:32 -07:00
transistor
c4f41d73ab
Put the types and traits from system into new devices file
2021-10-08 23:11:52 -07:00
transistor
8bb43f61ee
Fixed interrupts and added tx enable for OS buffered output
2021-10-08 10:52:15 -07:00
transistor
ecbaf6a68b
Added interrupt triggering from mc68681
2021-10-07 13:57:50 -07:00
transistor
7bd7f3e64f
Added cpu to system, and refactored m68k a bit
2021-10-07 11:35:15 -07:00
transistor
73d11ddb79
Switched to using Rc<RefCell<Box<dyn Trait>>> for devices
2021-10-07 09:41:01 -07:00
transistor
e186637f49
Refactored such that System is the top level object
2021-10-06 16:14:56 -07:00
transistor
5ea2ccc128
Added TRAP instruction and exception handling
2021-10-05 21:53:18 -07:00
transistor
59019d9c8e
Refactored address space again
2021-10-05 19:58:22 -07:00
transistor
f2a23a21cb
Added ROd instruction and fixed bug with MOVEM
2021-10-05 16:22:21 -07:00
transistor
f5283730c2
Added start of ata device
2021-10-04 13:02:58 -07:00
transistor
e561c533ef
Added stack tracer and fixed bug with CMPA instruction
2021-10-04 11:13:10 -07:00
transistor
2f54c18fcf
Modified memory operations to be simpler
2021-10-03 21:05:10 -07:00
transistor
dd21771bb3
Added better processing of debug commands, and timers
2021-10-03 20:45:50 -07:00
transistor
bc7fee5221
Updated readme
2021-10-03 10:00:58 -07:00
transistor
338e68a1d9
Fixed some erroneous instruction decodes and added binaries
2021-10-03 09:55:20 -07:00
transistor
10e905674b
Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags
...
With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case. This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target
2021-10-02 21:59:28 -07:00
transistor
98883e3daa
Added the Asd, LINK, and UNLK instructions
2021-10-02 15:35:08 -07:00
transistor
80c8fe9797
Fixed bug with PC offsets and the value of PC when calculated
2021-10-02 09:48:21 -07:00
transistor
4b577ad403
Separated debugging code into its own file
2021-10-02 09:35:25 -07:00
transistor
38bcf0af3f
Reorganized state and decoding into their own structs
2021-10-02 08:47:20 -07:00
transistor
f453e6dde2
Fixed bug in MOVEM and added multiple breakpoints
2021-10-01 22:06:53 -07:00
transistor
b0f094cb59
Added start of a testsuite
2021-10-01 19:27:05 -07:00
transistor
3c4e69378a
Fixed pty code to actually read input
2021-10-01 17:53:55 -07:00
transistor
a5cac4d309
Fixed indexing, flags, and added logical shift
...
The effective modes that used signed offsets were not properly
sign extending the immediate or register index values before adding
them to the address, resulting in incorrect addresses.
The flags were incorrect for some instructions, and I added the
logical shift instruction implementation
2021-10-01 15:38:21 -07:00
transistor
f7529bbb41
Added PTY terminal for I/O via the MC68681 module
...
Also fixed a bug where MOVEA needs to behave differently than MOVE,
such that the data is sign extended to a long and the condition flags
are not changed. I also modifed how Addressable returns data because
I need to return owned data from MC68681, so that the stored data can
be updated (ie. the status flag must be modified after a read)
2021-10-01 12:25:23 -07:00
transistor
01b4bdf859
Added bit test instructions and got boot message working
2021-09-30 20:27:01 -07:00
transistor
7868bc3014
Fixed instruction decode for MOVEM and EXT
...
It's now possible to run the monitor program until it loops waiting
for the serial transmitter to be ready for writing
2021-09-30 15:15:23 -07:00
transistor
e40663ee9a
Fixed conditionals and split decode and execute cycles for debugging
2021-09-30 12:58:11 -07:00
transistor
b7148d3b06
Added serial device
2021-09-29 23:21:11 -07:00
transistor
92342c23ed
More instruction execution, enough to loop
...
I'm using the monitor.bin binary built from computie to boot the
virtual machine, and it currently runs and loops, but there is no
actual serial device, so it's hard to tell if it's working correctly
2021-09-29 21:52:38 -07:00
transistor
9095333793
Reorganized and started working on the execution code
2021-09-29 17:11:48 -07:00
transistor
f22aa23dfa
Completed most of the instruction decode
2021-09-29 12:24:04 -07:00
transistor
6a4f53ca2b
Initial start with some structure for instruction decoding
2021-09-28 16:09:38 -07:00
