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10,024 Commits 7 Branches 121 Tags 500 MiB
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167 Commits

Author SHA1 Message Date
Thomas Harte
d1298c8863 Correct MOVE timing without breaking PEA, LEA, etc. 2022-06-01 09:06:08 -04:00
Thomas Harte
75e85b80aa Factor out the common stuff of exception state. 2022-06-01 08:20:33 -04:00
Thomas Harte
d6f72d9862 Avoid runtime checking of instruction supervisor requirements. 2022-05-29 14:56:44 -04:00
Thomas Harte
dbf7909b85 Fix timing of CMPM. 2022-05-29 14:49:42 -04:00
Thomas Harte
57aa8d2f17 Correct timing of ADDQ. 2022-05-29 14:34:06 -04:00
Thomas Harte
35e73b77f4 Fix interrupt stack frame. 2022-05-27 21:55:17 -04:00
Thomas Harte
d17d77714f Remove outdated TODO. 2022-05-27 15:40:06 -04:00
Thomas Harte
e8dd8215ba Tweak per empirical results. 2022-05-27 15:39:02 -04:00
Thomas Harte
e11990e453 Make an attempt at DIVS timing. 2022-05-27 15:38:54 -04:00
Thomas Harte
165ebe8ae3 Add time calculation for MULU and MULS. 2022-05-27 15:38:14 -04:00
Thomas Harte
e746637bee Fill in dynamic cost of shifts. 2022-05-27 15:38:08 -04:00
Thomas Harte
67b340fa5e Fix interrupt request address. 2022-05-27 10:33:36 -04:00
Thomas Harte
c97245e626 Fix CalcEA timing; make MOVEfromSR a read-modify-write. 2022-05-27 10:32:28 -04:00
Thomas Harte
367ad8079a Add a call to set register state with population of the prefetch. 2022-05-25 20:22:05 -04:00
Thomas Harte
80c1bedffb Eliminate false prefetch for BSR. 2022-05-25 16:32:02 -04:00
Thomas Harte
56ad6d24ee Fix ANDI/ORI/EORI to CCR/SR timing. 2022-05-25 16:20:26 -04:00
Thomas Harte
4ad0e04c23 Fix macro for n being an expression. 2022-05-25 16:05:45 -04:00
Thomas Harte
ee58301a46 Add RaiseException macro. 2022-05-25 15:45:09 -04:00
Thomas Harte
72425fc2e1 Fix bus data size of MOVE.b xx, -(An). 2022-05-25 13:00:36 -04:00
Thomas Harte
a5f2dfbc0c Initialise registers to 0 for better testability. 
TODO: is this the real initial state?
 2022-05-25 11:47:42 -04:00
Thomas Harte
5db6a937cb Have TRAP and TRAPV push the next instruction address to the stack. 2022-05-25 11:47:21 -04:00
Thomas Harte
9709b9b1b1 Standard exceptions don't raise the interrupt level. 2022-05-25 11:37:39 -04:00
Thomas Harte
5872e0ea4a Resolve MOVE.l xx, -(An) write target. 2022-05-25 08:15:18 -04:00
Thomas Harte
f43d27541b Avoid attempt to establish operand flags for undefined opcodes. 2022-05-24 15:53:12 -04:00
Thomas Harte
0f7cb2fa5a Attempt to honour the trace flag. 2022-05-24 15:47:47 -04:00
Thomas Harte
01e93ba916 Make an attempt at bus/address error. 2022-05-24 15:42:50 -04:00
Thomas Harte
780954f27b Add TRAP, TRAPV. 2022-05-24 15:14:46 -04:00
Thomas Harte
6f048de973 Pull unrecognised instruction handling into the usual switch table. 2022-05-24 12:42:34 -04:00
Thomas Harte
0dfaa7d9cf Interrupt fixes: supply proper address, raise level, fetch from vector. 2022-05-24 12:16:06 -04:00
Thomas Harte
eab720f6ea Ensure proper transition from unrecognised instructions. 2022-05-24 12:16:00 -04:00
Thomas Harte
a7e8aef9d3 Add MOVEA, be slightly more careful about next_operand_. 2022-05-24 11:30:09 -04:00
Thomas Harte
df54f1f1b7 Update TODO. 2022-05-24 11:06:05 -04:00
Thomas Harte
9e3c2b68d7 Eliminate potential future implicit conversion warnings. 2022-05-24 11:05:24 -04:00
Thomas Harte
3349bcaaed Attempt interrupt support. 2022-05-24 10:53:59 -04:00
Thomas Harte
3a4fb81242 Add a dummy STOP state. 2022-05-24 10:25:40 -04:00
Thomas Harte
1df3ad0671 Ensure TAS responds to VPA, BERR. 2022-05-24 09:17:58 -04:00
Thomas Harte
523cdd859b Add bus and address error, and VPA checks. 2022-05-24 09:08:31 -04:00
Thomas Harte
b037c76da6 Add public interface for everything except HALT and BUS REQ/etc. 
... neither of which are used by machines I currently implement.
 2022-05-23 20:55:01 -04:00
Thomas Harte
9cac4ca317 Add MOVE to/from USP. 2022-05-23 20:42:41 -04:00
Thomas Harte
34e5f39571 Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate. 2022-05-23 15:11:33 -04:00
Thomas Harte
e0a279344c Codify the existence of special cases, implement NOP and RESET. 2022-05-23 15:09:46 -04:00
Thomas Harte
e2f4db3e45 Shuffle more of the flow controller methods into their proper place. 2022-05-23 12:06:14 -04:00
Thomas Harte
c1837af84a Add notes to self on work remaining. 2022-05-23 11:02:31 -04:00
Thomas Harte
a87f6a28c9 Fix LINK A7. 2022-05-23 10:43:17 -04:00
Thomas Harte
98325325b1 Fix UNLINK A7. 2022-05-23 10:27:44 -04:00
Thomas Harte
26bf66e3f8 Fix shifts and rolls. 2022-05-23 10:09:46 -04:00
Thomas Harte
363cd97154 Resolve double definition of did_shift. 2022-05-23 10:07:24 -04:00
Thomas Harte
c6b3281274 Attempt the shifts and rolls. 2022-05-23 09:29:19 -04:00
Thomas Harte
1e8adc2bd9 Fix MOVEP to R. 2022-05-23 09:00:37 -04:00
Thomas Harte
c73021cf3c Implement MOVE. 2022-05-23 08:46:06 -04:00
Thomas Harte
1b3acf9cd8 Eliminate assumption. 2022-05-23 08:18:37 -04:00
Thomas Harte
c8ede400eb Fix RTE. 2022-05-22 21:17:28 -04:00
Thomas Harte
269263eecf Implement RTE, RTS, RTR. 2022-05-22 21:16:38 -04:00
Thomas Harte
faef5633f8 Ensure MOVE from SR has an effective address to write to. 2022-05-22 20:52:00 -04:00
Thomas Harte
7d1f1a3175 Implement MOVE [to/from] [CCR/SR]. 2022-05-22 19:45:22 -04:00
Thomas Harte
4e34727195 Fully implement TAS. 2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3 Implement TAS Dn, with detour for other TASes. 2022-05-22 16:08:30 -04:00
Thomas Harte
3b68b9a83b Implement PEA. 2022-05-22 11:27:38 -04:00
Thomas Harte
4279ce87ea Implement LEA. 2022-05-22 08:29:12 -04:00
Thomas Harte
3c1c4f89e9 Add MULU/S functionality, though not timing. 2022-05-22 08:02:32 -04:00
Thomas Harte
4a6512f5d5 Reduce dispatch boilerplate. 2022-05-22 07:39:16 -04:00
Thomas Harte
284f23c6ea Implement JMP. 2022-05-22 07:16:38 -04:00
Thomas Harte
11a9a5c126 Use common macros for the two forms of Perform. 2022-05-22 07:08:14 -04:00
Thomas Harte
4993801741 Add missing prefetch to BSET, BCHG, BCLR. 2022-05-21 21:05:05 -04:00
Thomas Harte
4b35899a12 Bcc: properly establish offset. 2022-05-21 20:59:34 -04:00
Thomas Harte
1304e930eb DBcc is two-operand. 2022-05-21 20:06:03 -04:00
Thomas Harte
94288d5a94 Excludes DBcc from standard operand fetch. 2022-05-21 19:53:28 -04:00
Thomas Harte
3811ab1b82 Fix the two 8bit-with-displacement effective address Calc steps. 2022-05-21 16:20:01 -04:00
Thomas Harte
f97d2a0eb9 Add DIVU/DIVS, at least as far as getting the correct numeric result. 2022-05-21 15:56:09 -04:00
Thomas Harte
2258434326 Ensure proper return addresses are calculated for JSR. 2022-05-21 14:28:44 -04:00
Thomas Harte
e46a3c4046 Implement JSR. 2022-05-21 10:29:36 -04:00
Thomas Harte
0e4cfde657 Fix MOVEM predec. 2022-05-21 08:17:39 -04:00
Thomas Harte
4bd9c36922 Fix postincrement mode. 2022-05-20 21:01:23 -04:00
Thomas Harte
256da43fe5 Fix MOVEM other than postinc and predec. 2022-05-20 20:47:54 -04:00
Thomas Harte
a818650027 Add a faulty attempt at MOVEM. 2022-05-20 18:48:19 -04:00
Thomas Harte
9d79e64f5c Add a mere calculate effective address pathway. 
Plus a lot of waffle to try to justify the further code duplication.
 2022-05-20 16:23:52 -04:00
Thomas Harte
ee942c5c17 Fix PC-relative fetches. 2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49 Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch. 
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
 2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441 Implement MOVEP. 2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453 Attempt BTST, BCHG, BCLR and BSET. 2022-05-20 12:58:45 -04:00
Thomas Harte
b4978d1452 Implement BSR, adding one more test file to the working set. 2022-05-20 12:40:35 -04:00
Thomas Harte
45e9648b8c Implement Bcc. 2022-05-20 12:04:43 -04:00
Thomas Harte
4327af3760 DBcc: add write-back. 2022-05-20 11:37:18 -04:00
Thomas Harte
860cc63e21 Attempt DBcc. 2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000. 2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382 Add missing fallthrough, patterns for all ADDs and SUBs. 2022-05-20 07:02:02 -04:00
Thomas Harte
1ee9c585ca Fix segue into second operand. 2022-05-19 19:38:42 -04:00
Thomas Harte
efe5a5ac26 Signal will_perform even for invalid instructions. 2022-05-19 18:50:43 -04:00
Thomas Harte
334e3ec529 Add privilege and instruction error exceptions; permit two operands to be stored. 2022-05-19 16:55:16 -04:00
Thomas Harte
282c4121d6 CLR also follows the NEGX/NEG/NOT pattern. 2022-05-19 16:30:08 -04:00
Thomas Harte
6c2eee0e44 Implement CHK, and therefore the standard exception pattern. 2022-05-19 16:27:39 -04:00
Thomas Harte
eeb6a088b8 Add a tag to avoid duplication. 2022-05-19 15:49:42 -04:00
Thomas Harte
22b63fe1f8 Add EXT, and notes to self. 2022-05-19 15:41:02 -04:00
Thomas Harte
7ef526e2d3 Fix destination decrement. 2022-05-19 15:22:59 -04:00
Thomas Harte
ce7f94559b Add EXG, ABCD, SBCD. 2022-05-19 15:19:00 -04:00
Thomas Harte
0471decfc8 Implement the complete set of fetch addressing modes. 
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
 2022-05-19 15:03:22 -04:00
Thomas Harte
084d6ca11d Simplify address handling; add perform patterns for CMP, AND, OR, EOR. 2022-05-19 12:18:47 -04:00
Thomas Harte
274902c3c1 Add to-memory write-back. Am going to reconsider usage of temporary_address_ as noted. 2022-05-19 11:23:26 -04:00
Thomas Harte
f46e7c65c5 Add AddressRegisterIndirect fetches. 2022-05-19 10:47:57 -04:00
Thomas Harte
c6c6213460 Bifurcate the fetch-operand flow. 
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
 2022-05-19 10:27:51 -04:00