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5,534 Commits 8 Branches 121 Tags 496 MiB
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815 Commits

Author SHA1 Message Date
Thomas Harte
4b09d7c41d Nudges 6850 towards coherence. 2019-10-20 20:38:55 -04:00
Thomas Harte
b0f5f7bd37 Attempts to start producing actual video. 2019-10-20 20:38:55 -04:00
Thomas Harte
4ead905c3c Adds an empty shell for the ACIA. 2019-10-20 20:38:55 -04:00
Thomas Harte
127bb043e7 Adds enough logic to advance to an ACIA access error. 2019-10-20 20:38:55 -04:00
Thomas Harte
2cf52fb89c Makes an unsuccessful first attempt at some timer functionality. 2019-10-20 20:38:54 -04:00
Thomas Harte
6e1b606adf Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-20 20:38:54 -04:00
Thomas Harte
e095a622d3 Ensures updates even when the event queue is empty. 2019-10-17 23:59:43 -04:00
Thomas Harte
9ab49065cd Starts to transfer serial line decoding logic into the line itself. 2019-10-17 23:34:39 -04:00
Thomas Harte
ab50f17d87 Silences, temporarily. 2019-10-16 23:34:49 -04:00
Thomas Harte
f5a2e180f9 Mostly but not quite fixes serial work. 2019-10-16 23:34:37 -04:00
Thomas Harte
f2e1584275 Starts working on the GPIP functionality block. 2019-10-16 23:21:25 -04:00
Thomas Harte
0fd8813ddb Attempts to tie an intelligent keyboard to the other end of its serial line. 2019-10-16 23:21:14 -04:00
Thomas Harte
b69180ba01 Corrects documentation error. 2019-10-16 23:19:42 -04:00
Thomas Harte
c352d8ae8c Adds a received_data_ register, that presently can never fill. 2019-10-13 23:04:57 -04:00
Thomas Harte
530e831064 Corrects transmission logic — exactly hitting write_data_time_remaining now works properly. 2019-10-13 21:40:46 -04:00
Thomas Harte
3b165a78f2 Ensures remaining_delays_ is set properly after [reset/flush]_writing. 2019-10-13 21:39:25 -04:00
Thomas Harte
8d87e9eb1c The ACIA actually has two clocks, though on an ST they're both 500,000 Hz. 2019-10-13 21:32:34 -04:00
Thomas Harte
f86dc082bb Ensures serial lines know their writer's clock rate. 2019-10-13 20:41:08 -04:00
Thomas Harte
d7982aa84e JustInTimeActors can now specify a clock divider. 2019-10-13 18:19:39 -04:00
Thomas Harte
516d78f5a8 Attempts to implement transmission interrupts and ClockingHint::Source. 2019-10-12 23:46:57 -04:00
Thomas Harte
8b50a7d6e3 Attempts mostly to implement 6850 output. 2019-10-12 23:14:29 -04:00
Thomas Harte
4bf81d3b90 Decodes the 6850 control register, and starts working on standardised serial ports. 2019-10-12 18:19:55 -04:00
Thomas Harte
cd75978e4e Nudges 6850 towards coherence. 2019-10-12 00:04:02 -04:00
Thomas Harte
c5ebf75351 Attempts to start producing actual video. 2019-10-10 22:46:58 -04:00
Thomas Harte
d7ce2c26e8 Adds an empty shell for the ACIA. 2019-10-10 20:54:29 -04:00
Thomas Harte
f88e1b1373 Adds enough logic to advance to an ACIA access error. 2019-10-09 23:01:11 -04:00
Thomas Harte
1de1818ebb Makes an unsuccessful first attempt at some timer functionality. 2019-10-07 22:44:35 -04:00
Thomas Harte
885f890df1 Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-06 23:14:05 -04:00
Thomas Harte
929475d31e Minor correction: round down, not up. 2019-09-28 23:49:32 -04:00
Thomas Harte
7758f9d0a9 Improves nomenclature. 2019-09-24 22:31:36 -04:00
Thomas Harte
8d4a96683a Reduces output noise. 2019-09-18 21:41:29 -04:00
Thomas Harte
f53411a319 Removes local NDEBUG. 2019-09-18 21:35:26 -04:00
Thomas Harte
962275c22a Removes clock for NCR 5380. 
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
 2019-09-18 20:17:47 -04:00
Thomas Harte
2f6c366668 Makes a concerted effort at properly wrapping a hard disk image. 2019-09-17 21:30:04 -04:00
Thomas Harte
2ce1f0a3b1 Implements multi-sector read/write. 
This once again unblocks Apple HD SC Setup. Progress!
 2019-09-16 22:20:42 -04:00
Thomas Harte
960b289e70 Edges closer towards proper DMA operation. 
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
 2019-09-15 15:03:06 -04:00
Thomas Harte
243e40cd79 Adds signalling of DACK. 2019-09-14 13:48:33 -04:00
Thomas Harte
64dad35026 Decreases logging, at least temporarily. 2019-09-03 22:40:32 -04:00
Thomas Harte
1c7e0f3c9d Fixes control line modification by the 5380 and SCSI target command chaining. 
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
 2019-09-02 23:14:37 -04:00
Thomas Harte
ca08716c52 Introduces real hard disk images to the nascent world of SCSI. 2019-08-25 17:03:41 -04:00
Thomas Harte
c86db12f1c Starts implementing DMA support on the 5380. 
The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
 2019-08-24 22:47:11 -04:00
Thomas Harte
2d82855f26 Attempts to provide a data out phase. 2019-08-22 23:16:58 -04:00
Thomas Harte
faec516a2c Starts pushing towards figuring out a proper infrastructure for mass storage. 2019-08-21 23:22:58 -04:00
Thomas Harte
bb1a0a0b76 Sketches out further SCSI infrastructure. 2019-08-21 22:37:39 -04:00
Thomas Harte
252650808d Starts seeking to unbind SCSI bus logic and command performance. 2019-08-19 22:47:01 -04:00
Thomas Harte
e3d9254555 Implements phase-match bit. 
Seemingly causing the command phase to proceed.
 2019-08-18 23:15:54 -04:00
Thomas Harte
955e909e61 Attempts to nudge the command phase further towards functioning. 2019-08-18 22:39:27 -04:00
Thomas Harte
8339e2044c Switches to proper SCSI terminology and better attempts a command phase. 2019-08-18 15:10:07 -04:00
Thomas Harte
0e0c789b02 Starts attempting to introduce a direct access device. 
Without having access to the SCSI-1 standard, a lot of this is guesswork.
 2019-08-17 23:43:42 -04:00
Thomas Harte
7e001c1d03 Corrects data line loading. 
Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
 2019-08-17 21:30:59 -04:00
Thomas Harte
9047932b81 Corrected basic error. Arbitration now seems to succeed. 
This is seemingly followed by a pattern of signalling BUSY+SEL followed by just SEL with the various other potential device IDs in turn. To which nothing ever responds as currently implemented.
 2019-08-15 23:28:30 -04:00
Thomas Harte
f668e4a54c Makes an attempt at getting the 5380 past arbitration. 
Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
 2019-08-15 23:14:40 -04:00
Thomas Harte
ce1c96d68c Starts thinking out the mechanics of emulating a SCSI-1 bus. 2019-08-13 23:09:11 -04:00
Thomas Harte
0f67e490e8 Adjusts NCR address decoding to produce a more plausible initial interaction. 2019-08-11 22:43:25 -04:00
Thomas Harte
a90a74a512 Stubs in just enough of the 5380 to get a Mac Plus too boot. 2019-08-11 20:55:20 -04:00
Thomas Harte
949c1e1668 Adds an empty shell for what will be my 5380 implementation. 2019-08-10 23:53:52 -04:00
Thomas Harte
96005261c7 Adds activity lights for Macintosh disk activity. 
Prompting a quick fix to drives not spinning down.
 2019-08-02 16:26:23 -04:00
Thomas Harte
335dda3d55 Attempts more accurately to match Apple's windowing logic. 2019-08-02 12:49:45 -04:00
Thomas Harte
9bbccd89d3 Adds an extended rationale for current implementation. 
Also strips some cruft of prior guesses.
 2019-07-31 23:19:46 -04:00
Thomas Harte
2aa308efdd Tweaks magic formulas. 
The computer now at least seeks outward, until this attempt at drive speed calculation fails.
 2019-07-30 16:18:36 -04:00
Thomas Harte
74c18d7861 Attempts a full wiring up of 400kb drive speed. 2019-07-30 15:08:55 -04:00
Thomas Harte
a43ada82b2 Experiments with a JustInTimeActor in the Master System. 2019-07-29 15:38:41 -04:00
Thomas Harte
85cf8d89bc Ensures an initial non-zero value. 2019-07-25 21:47:44 -04:00
Thomas Harte
0469f0240b Moves interrupt level selection outside the loop. 2019-07-23 23:13:03 -04:00
Thomas Harte
d69aee4972 Removes stray \n. 2019-07-23 22:17:46 -04:00
Thomas Harte
ee8d853fcb Ensures you can't get a phase 2 for free with run_for(0). 2019-07-17 14:20:27 -04:00
Thomas Harte
67055d8b56 Reduces CheckingWriteProtect costs, negligibly. 2019-07-15 22:39:55 -04:00
Thomas Harte
7baad61746 Attempts a full implementation of asynchronous write mode. 2019-07-15 17:11:12 -04:00
Thomas Harte
1d1e0d74f8 Corrects and introduces new parts. 2019-07-12 21:37:33 -04:00
Thomas Harte
d53d1c616f Continues trying to get to write support. 2019-07-12 21:20:05 -04:00
Thomas Harte
2c39229b13 Adds has-new-disk flag, allowing mounting of software from the desktop. 2019-07-12 13:17:24 -04:00
Thomas Harte
b730ac5d5a Reintroduces 1-second disable implementation. 2019-07-11 23:02:47 -04:00
Thomas Harte
c8917e677b Edging towards implementing IWM write support, but mainly tidied up. 2019-07-11 21:42:34 -04:00
Thomas Harte
cac97a9663 Devolves drive responsibility. 2019-07-10 22:39:56 -04:00
Thomas Harte
be251d6b03 Begins substituting the DoubleDensityDrive for the Sony. 2019-07-10 16:24:48 -04:00
Thomas Harte
6cfaf920ee Added attribution and commentary on rotation speeds. 2019-07-10 16:22:06 -04:00
Thomas Harte
1657f8768c Transfers and slightly extends drive logic into the drive. 2019-07-10 16:17:51 -04:00
Thomas Harte
c4ab0bb867 Starts sketching out an interface for IWM drives, eliminating a dangling use of unsigned as it goes. 2019-07-10 16:05:59 -04:00
Thomas Harte
fb6da1de4a Reduces logging temporarily. 2019-07-08 17:37:15 -04:00
Thomas Harte
245e27c893 Solidifies belief that the shift register bit is cleared on read/write. 2019-07-08 16:45:15 -04:00
Thomas Harte
28de629c08 Fixes the 6522 sufficiently to fix keyboard input. 2019-07-08 15:29:34 -04:00
Thomas Harte
210bcaa56d Introduces an initial shift unit test, and makes it pass. 2019-07-07 22:13:36 -04:00
Thomas Harte
191a7a9386 Reintroduces an empty second drive. 
This prevents the uninitialised disk error. Which is a clue.
 2019-07-02 16:59:00 -04:00
Thomas Harte
b9c2c42bc0 Switches drives to using floats for time counting. 
Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
 2019-07-02 15:43:03 -04:00
Thomas Harte
6c588a1510 Makes some further random swings at tracking the startup procedure. 2019-06-28 13:03:47 -04:00
Thomas Harte
00c32e4b59 Further miscellaneous changes to debug logging. All temporary. 2019-06-18 10:34:31 -04:00
Thomas Harte
877b46d2c1 Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'. 2019-06-15 16:08:54 -04:00
Thomas Harte
cc7226ae9f Starts trying to get a bit more rigorous about collected meanings. 2019-06-13 22:48:10 -04:00
Thomas Harte
bde975a3b9 Possibly mights the tiniest bit of headway with 'the IWM'. 
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
 2019-06-13 22:38:09 -04:00
Thomas Harte
f6f9024631 Corrects Macintosh aspect ratio (and framing). 2019-06-13 18:41:38 -04:00
Thomas Harte
535747e3f2 Restores single-line logging format. 2019-06-13 13:35:03 -04:00
Thomas Harte
d6150645c0 By hook or by crook, mouse input now works. 2019-06-12 22:19:25 -04:00
Thomas Harte
ccd2cb44a2 Fills in enough of the SCC to allow completion of the Macintosh side of that relationship. 2019-06-12 17:51:50 -04:00
Thomas Harte
ad8b68c998 Switches to a proper form of zero-upon-read data. 
Not that it's necessarily correct.
 2019-06-11 19:53:51 -04:00
Thomas Harte
3c075e9542 Switches drives 0 and 1. 2019-06-10 14:58:39 -04:00
Thomas Harte
9230969f43 Corrects enough of the 6522 and Keyboard to get an initial command seemingly working. 2019-06-10 09:28:27 -04:00
Thomas Harte
0e16c67805 Improves shift register connection, towards having the keyboard function properly. 
It now seems not to receive a command terminator, but is at least getting a command.
 2019-06-08 23:04:55 -04:00
Thomas Harte
697e094a4e Sketches out the absolute basics of an SCC interface. 2019-06-08 18:47:11 -04:00
Thomas Harte
50d37798a2 Eradicates magic constants. 2019-06-06 21:37:43 -04:00
Thomas Harte
e9d0676e75 Fiddles further with the tachometer. 2019-06-06 21:36:19 -04:00