Thomas Harte
|
ab8a98f1df
|
Implemented RST.
|
2017-05-26 07:29:19 -04:00 |
|
Thomas Harte
|
efe354a7b1
|
Fixed half carry after logical operation.s
|
2017-05-25 22:55:04 -04:00 |
|
Thomas Harte
|
d50d3fc837
|
Implemented CPL, SCF and CCF.
|
2017-05-25 22:51:08 -04:00 |
|
Thomas Harte
|
83ee92af1a
|
Made DAA work sufficiently well for the FUSE test.
|
2017-05-25 22:41:05 -04:00 |
|
Thomas Harte
|
ea0ad9fd87
|
Took a shot at DAA, seemingly not to Fuse's liking though.
|
2017-05-25 22:17:48 -04:00 |
|
Thomas Harte
|
ff3c60c0e1
|
Implemented the conditional JRs.
|
2017-05-25 21:51:30 -04:00 |
|
Thomas Harte
|
399703a471
|
Implemented JR.
|
2017-05-25 21:48:28 -04:00 |
|
Thomas Harte
|
82017c4aea
|
Implemented DJNZ.
|
2017-05-25 21:44:24 -04:00 |
|
Thomas Harte
|
bdf07c3dc9
|
Implemented EX AF, AF'.
|
2017-05-25 21:26:32 -04:00 |
|
Thomas Harte
|
598be24644
|
Fixed overflow for 8-bit decrementing.
|
2017-05-25 21:23:38 -04:00 |
|
Thomas Harte
|
c668ff9472
|
Added incrementing of the refresh register.
|
2017-05-25 21:01:52 -04:00 |
|
Thomas Harte
|
6575091a78
|
Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
|
2017-05-22 21:50:34 -04:00 |
|
Thomas Harte
|
9e25d014d2
|
Made an attempt to log bus activity for comparison with FUSE results.
|
2017-05-22 19:49:38 -04:00 |
|
Thomas Harte
|
41d5dd8679
|
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
|
2017-05-22 19:24:11 -04:00 |
|
Thomas Harte
|
c3ea6dc1f5
|
Added respect for limiting to the requested number of cycles in the Z80.
|
2017-05-22 19:15:55 -04:00 |
|
Thomas Harte
|
22afa509ca
|
Got to a parsing and towards an attempt to run FUSE tests.
|
2017-05-22 19:14:46 -04:00 |
|
Thomas Harte
|
f2aae72cc2
|
Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
|
2017-05-21 20:43:36 -04:00 |
|
Thomas Harte
|
fe8db1873c
|
Added 16-bit ADC and SBC table entries; once again extended logging.
|
2017-05-21 20:32:06 -04:00 |
|
Thomas Harte
|
c66c715ac9
|
Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
|
2017-05-21 19:26:40 -04:00 |
|
Thomas Harte
|
5dcfd85642
|
Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
|
2017-05-21 19:15:52 -04:00 |
|
Thomas Harte
|
c70dfe1b09
|
Implemented the two variations of loading between (nn) and SP.
|
2017-05-21 13:20:28 -04:00 |
|
Thomas Harte
|
232c591655
|
Threw in a little macro documentation and a missing macro.
|
2017-05-21 13:13:21 -04:00 |
|
Thomas Harte
|
790614b544
|
Added EI and DI.
|
2017-05-21 12:53:17 -04:00 |
|
Thomas Harte
|
32c032cd97
|
Implemented a couple of easy-to-add missing base page instructions.
|
2017-05-21 10:18:43 -04:00 |
|
Thomas Harte
|
e48ee16366
|
Continued cleaning efforts, added conditional RET.
|
2017-05-21 10:13:59 -04:00 |
|
Thomas Harte
|
e92d936ce8
|
Added conditional calls.
|
2017-05-21 10:03:46 -04:00 |
|
Thomas Harte
|
4e210c5396
|
Added LD A, (nn).
|
2017-05-21 10:00:10 -04:00 |
|
Thomas Harte
|
3d3e60b1fc
|
Implemented LD (HL), r.
|
2017-05-21 09:56:41 -04:00 |
|
Thomas Harte
|
f3f0e2f1a9
|
Implemented RRA and RRCA.
|
2017-05-21 09:52:19 -04:00 |
|
Thomas Harte
|
08206eea56
|
This logging has outlived its usefulness for now.
|
2017-05-21 09:47:53 -04:00 |
|
Thomas Harte
|
78296246e8
|
Added ALU n.
|
2017-05-21 09:46:18 -04:00 |
|
Thomas Harte
|
85b5dd35b1
|
Took a shot at 8-bit arithmetic.
|
2017-05-21 09:43:17 -04:00 |
|
Thomas Harte
|
11cfaa3e3d
|
Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.
|
2017-05-21 09:17:30 -04:00 |
|
Thomas Harte
|
103c863534
|
Through temporarily dramatically increased logging, fixed conditional JP.
|
2017-05-20 23:03:52 -04:00 |
|
Thomas Harte
|
6688f83226
|
Took a shot at LDIR.
|
2017-05-20 21:58:24 -04:00 |
|
Thomas Harte
|
01a064dd63
|
Added an empty ED page.
|
2017-05-20 17:29:30 -04:00 |
|
Thomas Harte
|
7b234078ae
|
Implemented EX DE, HL and shuffled to allow instruction pages.
|
2017-05-20 17:04:25 -04:00 |
|
Thomas Harte
|
add02a7897
|
Added LD (nn), A, and reduced double logging to single for now.
|
2017-05-19 23:13:28 -04:00 |
|
Thomas Harte
|
19167df692
|
Consolidated and filled in AND and XOR.
|
2017-05-19 23:03:34 -04:00 |
|
Thomas Harte
|
6766845e21
|
Filled in most of the loads.
|
2017-05-19 22:57:43 -04:00 |
|
Thomas Harte
|
bc3b5f3e35
|
Added 16-bit INCs and DECs. Which don't set flags, so are easy.
|
2017-05-19 22:13:36 -04:00 |
|
Thomas Harte
|
5fe23113ec
|
Moved RET to the correct place, implemented POP AF.
|
2017-05-19 22:03:12 -04:00 |
|
Thomas Harte
|
c55e1c1d17
|
Implemented POP and therefore RET; corrected timing of PUSH.
|
2017-05-19 21:59:45 -04:00 |
|
Thomas Harte
|
d910405648
|
Added enough infrastructure to be able to react to the two CP/M calls this cares about.
|
2017-05-19 21:53:39 -04:00 |
|
Thomas Harte
|
62b432c046
|
Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
|
2017-05-19 21:20:28 -04:00 |
|
Thomas Harte
|
eae1f78221
|
Implemented the main page pushes.
|
2017-05-19 19:28:38 -04:00 |
|
Thomas Harte
|
11d05fb3b8
|
Expanded a little on operations, added an implementation or two.
|
2017-05-19 19:18:35 -04:00 |
|
Thomas Harte
|
58efca835f
|
Sought to add a further opcode.
|
2017-05-18 22:53:43 -04:00 |
|
Thomas Harte
|
99f2060fc1
|
Further improved macros.
|
2017-05-18 22:11:54 -04:00 |
|
Thomas Harte
|
5d3ebcb35a
|
Made a first attempt at LD HL, (nn).
|
2017-05-17 22:42:30 -04:00 |
|
Thomas Harte
|
509d011fbe
|
Implemented JP, my first Z80 operation.
|
2017-05-17 22:31:41 -04:00 |
|
Thomas Harte
|
17ffd604bf
|
Made an attempt to get the Z80 at least as far as rejecting an opcode.
|
2017-05-17 21:45:23 -04:00 |
|
Thomas Harte
|
21d0602305
|
Restored the all RAM 6502's lack of power-on reset.
|
2017-05-17 21:43:40 -04:00 |
|
Thomas Harte
|
1378ab7278
|
Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
|
2017-05-17 07:36:06 -04:00 |
|
Thomas Harte
|
87a021ec2d
|
Made further attempt to get as fas as having the Z80 attempt to do something.
|
2017-05-16 22:19:40 -04:00 |
|
Thomas Harte
|
7190f927b7
|
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
|
2017-05-16 21:28:17 -04:00 |
|
Thomas Harte
|
d559d8b901
|
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
|
2017-05-16 21:19:17 -04:00 |
|
Thomas Harte
|
50bb4f0142
|
There's finally a loop in here, at least.
|
2017-05-15 22:25:52 -04:00 |
|
Thomas Harte
|
7da51602d5
|
Moved flush, added run_for_cycles, which does nothing right now.
|
2017-05-15 07:59:21 -04:00 |
|
Thomas Harte
|
5152517887
|
Added the boilerplate stuff necessary to query registers.
|
2017-05-15 07:55:53 -04:00 |
|
Thomas Harte
|
eb8a2de5d6
|
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
|
2017-05-15 07:38:59 -04:00 |
|
Thomas Harte
|
f2a1a906ff
|
Adapted what negligible amount there is of the z80 as per the new CPU namespace.
|
2017-05-14 22:15:16 -04:00 |
|
Thomas Harte
|
0808e9b6fb
|
Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
|
2017-05-14 22:08:15 -04:00 |
|
Thomas Harte
|
b81a2cc273
|
First tentative steps towards adding a Z80 implementation.
|
2017-05-14 17:46:41 -04:00 |
|
Thomas Harte
|
defec2c9b0
|
Fixed: operation reads now fulfil the promise of seeding the value to be read with 0xff.
|
2017-03-26 20:56:27 -04:00 |
|
Thomas Harte
|
e01f3f06c8
|
Completed curly bracket movement.
|
2017-03-26 14:34:47 -04:00 |
|
Thomas Harte
|
55ce851bb2
|
Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history.
|
2017-03-18 17:04:01 -04:00 |
|
Thomas Harte
|
36b58d03b7
|
Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support.
|
2017-03-18 14:46:46 -04:00 |
|
Thomas Harte
|
14a76af0d3
|
Started trying to float out bus control to cartridges.
|
2017-03-17 20:28:07 -04:00 |
|
Thomas Harte
|
5be22e2f8d
|
Switched to suffix underscores and underscores in general for instance variables.
|
2016-12-03 11:38:53 -05:00 |
|
Thomas Harte
|
7ad44f5152
|
Flipped order of conditional so as negligibly to improve prediction.
|
2016-10-31 22:17:18 -04:00 |
|
Thomas Harte
|
2452a3104f
|
Corrected test: hitting zero is sufficient. No need to cross it.
|
2016-10-30 20:24:30 -04:00 |
|
Thomas Harte
|
9309be229c
|
Moved cycle count test down to the only places where it may actually yield a different result.
|
2016-10-30 20:13:44 -04:00 |
|
Thomas Harte
|
a106018680
|
Fixed initial state: interrupt flag is initially low.
|
2016-10-28 21:22:03 -04:00 |
|
Thomas Harte
|
613b5b3f98
|
Switched to inverse storage of the interrupt flag so as to reduce logical burden when storing IRQ line history.
|
2016-10-28 20:52:43 -04:00 |
|
Thomas Harte
|
4408c60ef7
|
This too should continue, not break, since it doesn't schedule a memory access.
|
2016-10-27 18:32:21 -04:00 |
|
Thomas Harte
|
534b3d085d
|
Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).
|
2016-10-27 08:41:44 -04:00 |
|
Thomas Harte
|
f84b66a5f4
|
Made an attempt to fix wake-from-WAIT.
|
2016-10-25 19:06:46 -04:00 |
|
Thomas Harte
|
4b18c76b84
|
Introduced a bifurcation between break and continue to signify whether a bus access takes place, necessitating a shift in the location of the bus access but allowing the conditional to be dropped. Need to test.
|
2016-10-25 18:45:53 -04:00 |
|
Thomas Harte
|
c253a4258f
|
Made minor restructuring changes, slightly to reduce number of conditionals per operation and to drop a big hint to the optimiser.
|
2016-10-25 18:34:24 -04:00 |
|
Thomas Harte
|
fa7c64bb5d
|
Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success.
|
2016-10-03 22:03:39 -04:00 |
|
Thomas Harte
|
5d40d70c92
|
Fixed 6560 addressing error, added an autotyper for Vic disks (more work potentially needed), fixed semantics for testing whether a 6502 is about to reset.
|
2016-08-01 10:32:32 -04:00 |
|
Thomas Harte
|
740ea0b7e2
|
Added overflow-flag setting logic and ensured disk ROM gets through regardless of ROM/disk installation order.
|
2016-07-31 19:33:18 -04:00 |
|
Thomas Harte
|
1baf21827c
|
Since the ROM is well disassembled, let's actually try to be a 1541 first.
|
2016-07-06 22:17:32 -04:00 |
|
Thomas Harte
|
41809d4597
|
Made an attempt at NMI usurption of IRQ/BRK.
|
2016-06-29 20:59:45 -04:00 |
|
Thomas Harte
|
c02226bc41
|
Ensured stack pointer goes the right way upon reset.
|
2016-06-29 20:42:26 -04:00 |
|
Thomas Harte
|
db7c6430b5
|
Fixed Klaus Dormann termination condition.
|
2016-06-29 19:16:34 -04:00 |
|
Thomas Harte
|
0182b0483a
|
Added a 'power on' flag that is set automatically at construction but can be declined. Saves all that stuff of every machine having to set and then unset the RST line, and fixes an Electron bug related to that.
|
2016-06-29 19:13:24 -04:00 |
|
Thomas Harte
|
6419d9c485
|
Added a single IRQ test case, discovering that I'm two cycles short. Whoops!
|
2016-06-28 21:29:43 -04:00 |
|
Thomas Harte
|
6e698e908e
|
Made an attempt to reduce cost of the most-likely path.
|
2016-06-28 18:46:00 -04:00 |
|
Thomas Harte
|
574aa32b72
|
Made an attempt to implement NMI. Some work to do on the B flag though, I think.
|
2016-06-27 22:01:48 -04:00 |
|
Thomas Harte
|
88e2b382e5
|
Made an attempt at a full and thorough 6532 implementation (and got a bit more explicit about flag size in the 6502).
|
2016-06-20 18:57:35 -04:00 |
|
Thomas Harte
|
ef3ed1f436
|
Implemented full paste ability for any machine that is a typer.
|
2016-06-19 16:35:04 -04:00 |
|
Thomas Harte
|
06fb2ff1c7
|
Started endeavouring to sketch out the boilerplate for writing a 6522 test harness. Added a default implementation of synchronise to the 6522 too, since not everybody is going to want one.
|
2016-06-18 09:28:46 -04:00 |
|
Thomas Harte
|
5c4f35e13f
|
Finally started on generalising the C++ stuff so as to be able to be able to get a working audio binding on the OS-specific side without further repetition by factoring an appropriate protocol out from the Electron and sketching out the correct speaker class for the Atari. Added a method to ask it what a good output frequency would be.
|
2016-05-31 21:23:44 -04:00 |
|
Thomas Harte
|
0242924fb4
|
Various bits of caveman debugging appearing and disappearing, switched to latching ball behaviour.
|
2016-05-22 14:26:02 -04:00 |
|
Thomas Harte
|
e636ae37b4
|
Ensured that calling return_from_subroutine really does unjam the processor if required, causing all tests once again to pass.
|
2016-05-10 21:44:11 -04:00 |
|
Thomas Harte
|
5a4262d74e
|
Confirmed: it is inaccurate for a 6502 to self reset at power up. So that responsibility now rests in the machines.
|
2016-05-10 21:05:52 -04:00 |
|
Thomas Harte
|
9b64f64db7
|
Attempted to normalise some style decisions.`
|
2016-04-24 22:32:24 -04:00 |
|
Thomas Harte
|
a6ef78862c
|
This'll probably do for now.
|
2016-03-24 22:20:00 -04:00 |
|
Thomas Harte
|
f1caf62ff2
|
Continuing the switch around.
|
2016-03-24 19:31:41 -04:00 |
|
Thomas Harte
|
738186e323
|
Edging back towards shifting things to the stack.
|
2016-03-24 19:17:44 -04:00 |
|
Thomas Harte
|
3038704977
|
Attempted to introduce a lowpass filter to the graphics output, reverted 6502 optimisations as seemingly not working.
|
2016-03-21 22:01:25 -04:00 |
|
Thomas Harte
|
5db0f9e2d5
|
Shunted a few more things onto the stack.
|
2016-03-20 22:59:21 -04:00 |
|
Thomas Harte
|
9a82f028aa
|
operation is now also stack local.
|
2016-03-20 22:52:49 -04:00 |
|
Thomas Harte
|
2f174b3a3e
|
Moved operand to stack-local storage.
|
2016-03-20 22:50:16 -04:00 |
|
Thomas Harte
|
5966ac845f
|
Switched symbols and updated all-RAM 6502 in order to fix unit test target.
|
2016-03-20 22:48:56 -04:00 |
|
Thomas Harte
|
a4ec0b023c
|
Made some type conversions explicit.
|
2016-03-15 21:25:02 -04:00 |
|
Thomas Harte
|
20ac630e4d
|
Some minor optimisations and timing tweaks. Nothing of substance.
|
2016-03-10 19:58:50 -05:00 |
|
Thomas Harte
|
1eea28b692
|
Disabled some debugging parts, added some others, marked some things as inline. Ticking over.
|
2016-02-22 23:35:42 -05:00 |
|
Thomas Harte
|
baef1ccd57
|
Made the constructor protected, to emphasise that this class isn't for instantiation. Also added extra comments aplenty.
|
2016-01-21 08:39:34 -05:00 |
|
Thomas Harte
|
9fa35dd559
|
Killed some whitespace lines.
|
2016-01-20 21:58:34 -05:00 |
|
Thomas Harte
|
de7218cdf0
|
Added a lot of commenting to the CPU6502 definition, simplifying its construction. Added missing nullability modifier to CSElectron. Fixed bad-habit Objective-C style naming on the Electron's Interrupt enum.
|
2016-01-20 21:55:38 -05:00 |
|
Thomas Harte
|
93f7df04a0
|
Ensured correctly timed sampling of the interrupt line.
|
2016-01-10 22:55:56 -05:00 |
|
Thomas Harte
|
ccf20299a3
|
Made an attempt at getting some interrupts all up inside this thing.
|
2016-01-10 19:06:46 -05:00 |
|
Thomas Harte
|
7341f5c341
|
This is intended to be enough to start producing something of an output. But something's obviously still broken.
|
2016-01-09 20:26:40 -05:00 |
|
Thomas Harte
|
bfd9957c81
|
You now get an Electron only if you ask for a new file. That'll do for now while it's the only thing that one might want to start without supplying a file. The 6502 now starts from a defined point — being reset. The Electron is starting to grow the absolute most simple buds of its memory map.
|
2016-01-06 21:09:49 -05:00 |
|
Thomas Harte
|
675070c5dd
|
Very, _very_ minor: switched to normal C++ constructor syntax for simple variable initialisation.
|
2015-12-06 16:53:37 -05:00 |
|
Thomas Harte
|
a693c081f8
|
Switched on the appropriate compiler warnings re: signed comparisons and implicit conversions. Fixed all less-than-explicit calls.
|
2015-08-16 16:08:29 -04:00 |
|
Thomas Harte
|
9ca57b80a7
|
Minor steps to help with diagnostics; all commented out or merely to benefit with breakpoint placement.
|
2015-08-13 08:43:10 +01:00 |
|
Thomas Harte
|
cc98534f94
|
Added test for NOP, discovering the undocumented ones to be the incorrect length.
|
2015-08-13 07:32:50 +01:00 |
|
Thomas Harte
|
dd0f17130a
|
Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading.
|
2015-08-13 02:58:39 +01:00 |
|
Thomas Harte
|
975836c30f
|
Added a quick snippet test, discovering that I've cut a cycle from read/modify/writes.
|
2015-08-13 02:18:41 +01:00 |
|
Thomas Harte
|
503d684af0
|
Added a couple of timing tests, both of which seem to pass for now.
|
2015-08-13 01:55:23 +01:00 |
|
Thomas Harte
|
d19f8ed507
|
Removed the implicit reset upon 6502 startup, adding a reset line. Hence all tests now pass again. Added an empty shell for timing tests, the all-RAM 6502 now counting bus cycles.
|
2015-08-13 00:51:06 +01:00 |
|
Thomas Harte
|
c1d1fb65cb
|
Made an attempt properly to emulate the RDY line and the Atari's use of it.
|
2015-07-31 16:54:20 -04:00 |
|
Thomas Harte
|
53dd5c8f16
|
Trying to fix my RDY line emulation. Switched to PAL timings, at least temporarily, since it's starting to make a difference.
|
2015-07-31 16:44:53 -04:00 |
|
Thomas Harte
|
cd0a62d21e
|
With a slight tweak to the informal protocol used for 6502 memory access cycles, ensured the wait strobe actually halts the CPU, to give a more accurate linking of machine time to real time.
|
2015-07-26 15:55:19 -04:00 |
|
Thomas Harte
|
6252f6030f
|
Switched to idiomatic source name, ensured latest project name is in all appropriate header places, threw texture coordinates slightly into the shader mix.
|
2015-07-26 15:25:11 -04:00 |
|
Thomas Harte
|
6558ae1425
|
Imported what little I have so far in the way of a memory-access cycle complete 6502 and just enough of a pretend Atari 2600 on top to be able to see some playfields in ASCII art.
|
2015-07-16 19:56:02 -04:00 |
|