2006-02-05 05:50:24 +00:00
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//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
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2005-04-21 23:30:14 +00:00
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//
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2004-02-25 19:28:19 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-02-25 19:28:19 +00:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 18:45:23 +00:00
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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2004-02-25 19:28:19 +00:00
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//
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//===----------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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2004-02-29 05:18:30 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2004-04-02 20:53:37 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-03-23 18:12:57 +00:00
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#include "llvm/CodeGen/MachineLocation.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2006-11-27 23:37:22 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2004-02-25 19:28:19 +00:00
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#include "llvm/Type.h"
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2007-02-19 21:49:54 +00:00
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#include "llvm/ADT/BitVector.h"
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2004-09-02 02:37:43 +00:00
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#include "llvm/ADT/STLExtras.h"
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2004-02-25 19:28:19 +00:00
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using namespace llvm;
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2006-11-13 23:36:35 +00:00
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
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const TargetInstrInfo &tii)
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2006-02-05 05:50:24 +00:00
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: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
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2006-11-13 23:36:35 +00:00
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Subtarget(st), TII(tii) {
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2006-02-04 06:58:46 +00:00
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}
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2004-02-25 19:28:19 +00:00
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2007-07-14 14:06:15 +00:00
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const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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2007-01-02 21:33:40 +00:00
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static const unsigned CalleeSavedRegs[] = { 0 };
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return CalleeSavedRegs;
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2006-05-18 00:12:58 +00:00
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}
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2007-02-19 21:49:54 +00:00
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G5);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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return Reserved;
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}
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2006-02-05 05:50:24 +00:00
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void SparcRegisterInfo::
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2004-02-25 19:28:19 +00:00
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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2004-10-10 19:57:21 +00:00
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MachineInstr &MI = *I;
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2009-02-13 02:31:35 +00:00
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DebugLoc dl = MI.getDebugLoc();
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2007-12-30 20:49:49 +00:00
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int Size = MI.getOperand(0).getImm();
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2006-02-05 05:50:24 +00:00
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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2005-12-19 02:51:12 +00:00
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Size = -Size;
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if (Size)
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2009-02-13 02:31:35 +00:00
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BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
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2005-12-19 02:51:12 +00:00
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MBB.erase(I);
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2004-02-25 19:28:19 +00:00
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}
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2010-08-26 23:32:16 +00:00
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void
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2009-10-07 17:12:56 +00:00
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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2010-08-26 23:32:16 +00:00
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int SPAdj, RegScavenger *RS) const {
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2007-05-01 09:13:03 +00:00
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assert(SPAdj == 0 && "Unexpected");
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2004-04-02 20:53:37 +00:00
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unsigned i = 0;
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MachineInstr &MI = *II;
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2009-02-13 02:31:35 +00:00
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DebugLoc dl = MI.getDebugLoc();
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2008-10-03 15:45:36 +00:00
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while (!MI.getOperand(i).isFI()) {
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2004-04-02 20:53:37 +00:00
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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2007-12-30 23:10:15 +00:00
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int FrameIndex = MI.getOperand(i).getIndex();
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2004-04-02 20:53:37 +00:00
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2004-04-06 22:10:22 +00:00
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// Addressable stack objects are accessed using neg. offsets from %fp
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2004-08-14 22:57:22 +00:00
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MachineFunction &MF = *MI.getParent()->getParent();
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2004-04-06 22:10:22 +00:00
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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2007-12-30 20:49:49 +00:00
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MI.getOperand(i+1).getImm();
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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2006-09-05 02:31:13 +00:00
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MI.getOperand(i).ChangeToRegister(SP::I6, false);
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2006-05-04 17:52:23 +00:00
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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unsigned OffHi = (unsigned)Offset >> 10U;
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2009-02-13 02:31:35 +00:00
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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// Emit G1 = G1 + I6
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2009-02-13 02:31:35 +00:00
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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2006-11-27 23:37:22 +00:00
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.addReg(SP::I6);
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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// Insert: G1+%lo(offset) into the user.
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2006-09-05 02:31:13 +00:00
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MI.getOperand(i).ChangeToRegister(SP::G1, false);
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2006-05-04 17:52:23 +00:00
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MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
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Reserve G1 for frame offset stuff and use it to handle large stack frames.
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-20 07:56:31 +00:00
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}
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2004-02-25 19:28:19 +00:00
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}
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2006-02-05 05:50:24 +00:00
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void SparcRegisterInfo::
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2004-02-29 05:18:30 +00:00
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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2004-02-25 19:28:19 +00:00
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2006-04-07 16:34:46 +00:00
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unsigned SparcRegisterInfo::getRARegister() const {
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2009-09-08 12:47:30 +00:00
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return SP::I7;
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2006-04-07 16:34:46 +00:00
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}
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2009-11-12 21:00:03 +00:00
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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2009-09-08 12:47:30 +00:00
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return SP::I6;
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2006-03-23 18:12:57 +00:00
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}
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2007-02-21 22:54:50 +00:00
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unsigned SparcRegisterInfo::getEHExceptionRegister() const {
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2009-07-14 16:55:14 +00:00
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llvm_unreachable("What is the exception register");
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2007-02-21 22:54:50 +00:00
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return 0;
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}
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unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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2009-07-14 16:55:14 +00:00
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llvm_unreachable("What is the exception handler register");
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2007-02-21 22:54:50 +00:00
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return 0;
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}
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2007-11-13 19:13:01 +00:00
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int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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2009-09-08 12:47:30 +00:00
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return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
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2007-11-11 19:50:10 +00:00
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}
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2006-02-05 05:50:24 +00:00
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#include "SparcGenRegisterInfo.inc"
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2004-02-25 19:28:19 +00:00
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