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llvm-6502/test/MC/Disassembler/X86/simple-tests.txt

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specify a triple to use, fixing the test on non-x86-64 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 07:01:12 +00:00
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:37:58 +00:00
# CHECK: int $33
0xCD 0x21
# CHECK: int $33
0xCD 0x21
# CHECK: addb %al, (%rax)
various cleanups, make the disassemble reject lines with too much data on them, for example: addb %al, (%rax) simple-tests.txt:11:5: error: excess data detected in input 0 0 0 0 0 ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91896 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:56:51 +00:00
0 0
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:37:58 +00:00
# CHECK: callq -1234
0xe8 0x2e 0xfb 0xff 0xff
add some disassemble testcases for weird instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 23:46:48 +00:00
# CHECK: lfence
0x0f 0xae 0xe8
# CHECK: mfence
0x0f 0xae 0xf0
# CHECK: monitor
0x0f 0x01 0xc8
# CHECK: mwait
0x0f 0x01 0xc9
# CHECK: vmcall
0x0f 0x01 0xc1
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
# CHECK: vmlaunch
0x0f 0x01 0xc2
# CHECK: vmresume
0x0f 0x01 0xc3
# CHECK: vmxoff
0x0f 0x01 0xc4
# CHECK: swapgs
add encoder support and tests for rdtscp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 03:42:24 +00:00
0x0f 0x01 0xf8
# CHECK: rdtscp
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes for the encoding and is not the same as vmptrld. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:17:26 +00:00
0x0f 0x01 0xf9
# CHECK: vmxon
0xf3 0x0f 0xc7 0x30
# CHECK: vmptrld
0x0f 0xc7 0x30
# CHECK: vmptrst
0x0f 0xc7 0x38
testcase for r101538, patch by Nico Schmidt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:22:06 +00:00
# CHECK: movl $0, -4(%rbp)
0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
Eliminated the classification of control registers into %ecr_ and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
# CHECK: movq %cr0, %rcx
0x0f 0x20 0xc1
my work on adding segment registers to LEA missed the disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:23:55 +00:00
# CHECK: leal 4(%rsp), %ecx
Added a testcase for the ENTER instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 00:21:40 +00:00
0x8d 0x4c 0x24 0x04
# CHECK: enter $1, $2
0xc8 0x01 0x00 0x02
Fixed handling of immediate operand sizes, which weren't properly reflecting the OperandSize attribute of the instruction leading to improper decoding of certain instructions with the 66H prefix. Also added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:24:11 +00:00
# CHECK: movw $47416, -66(%rbp)
0x66 0xc7 0x45 0xbe 0x38 0xb9
Basic sanity checks to ensure that 2- and 3-byte VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:32:46 +00:00
# CHECK: vaddpd %ymm13, %ymm1, %ymm0
0xc4 0xc1 0x75 0x58 0xc5
# CHECK: vaddps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x58 0xc3
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 05:28:50 +00:00
# CHECK: vandpd %ymm13, %ymm1, %ymm0
0xc4 0xc1 0x75 0x54 0xc5
# CHECK: vandps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x54 0xc3
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
# CHECK: vzeroall
0xc5 0xfc 0x77
# CHECK: vcvtps2pd %xmm0, %ymm0
0xc5 0xfc 0x5a 0xc0
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 07:42:00 +00:00
# CHECK: vandps (%rdx), %xmm1, %xmm7
0xc5 0xf0 0x54 0x3a
Fix disassembling of VCVTSD2SI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
# CHECK: vcvtss2sil %xmm0, %eax
0xc5 0xfa 0x2d 0xc0
# CHECK: vcvtsd2si %xmm0, %eax
0xc5 0xfb 0x2d 0xc0
# CHECK: vcvtsd2si %xmm0, %rax
0xc4 0xe1 0xfb 0x2d 0xc0
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:09:35 +00:00
# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax)
0xc4 0xe2 0x71 0x2f 0x00
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 04:17:54 +00:00
# CHECK: vmovapd %xmm0, %xmm2
0xc5 0xf9 0x28 0xd0
Change X86 disassembly to print immediates values as signed by default. Special case those instructions that the immediate is not sign-extend. radr://8795217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:01:23 +00:00
# Check X86 immediates print as signed values by default. radr://8795217
# CHECK: andq $-16, %rsp
0x48 0x83 0xe4 0xf0
# Check these special case instructions that the immediate is not sign-extend.
# CHECK: blendps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0c 0xca 0x81
# CHECK: blendpd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0d 0xca 0x81
# CHECK: pblendw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0e 0xca 0x81
# CHECK: mpsadbw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x42 0xca 0x81
# CHECK: dpps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x40 0xca 0x81
# CHECK: dppd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x41 0xca 0x81
# CHECK: insertps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x21 0xca 0x81
# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0xca 0x81
# CHECK: vblendps $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0x08 0x81
# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0xca 0x81
# CHECK: vblendpd $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0x08 0x81
# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x0e 0xca 0x81
# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x42 0xca 0x81
# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0xca 0x81
# CHECK: vdpps $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0x08 0x81
# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x41 0xca 0x81
# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
0xc4 0xe3 0x69 0x21 0xcb 0x81
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 20:23:20 +00:00
# CHECK: pause
0xf3 0x90
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
# CHECK: addl %eax, %edi
0x01 0xc7
# CHECK: addl %edi, %eax
0x03 0xc7
# CHECK: movl %eax, %edi
0x89 0xc7
# CHECK: movl %edi, %eax
0x8b 0xc7
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: movups %xmm1, %xmm0
0x0f 0x10 0xc1
# CHECK: movups %xmm0, %xmm1
0x0f 0x11 0xc1
# CHECK: movaps %xmm1, %xmm0
0x0f 0x28 0xc1
# CHECK: movaps %xmm0, %xmm1
0x0f 0x29 0xc1
# CHECK: movupd %xmm1, %xmm0
0x66 0x0f 0x10 0xc1
# CHECK: movupd %xmm0, %xmm1
0x66 0x0f 0x11 0xc1
# CHECK: movapd %xmm1, %xmm0
0x66 0x0f 0x28 0xc1
# CHECK: movapd %xmm0, %xmm1
0x66 0x0f 0x29 0xc1
# CHECK: vmovups %xmm1, %xmm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf8 0x10 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovups %xmm0, %xmm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf8 0x11 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovaps %xmm1, %xmm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf8 0x28 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovaps %xmm0, %xmm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf8 0x29 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovupd %xmm1, %xmm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf9 0x10 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovupd %xmm0, %xmm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf9 0x11 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovapd %xmm1, %xmm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf9 0x28 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovapd %xmm0, %xmm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xf9 0x29 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovups %ymm1, %ymm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xfc 0x10 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovups %ymm0, %ymm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xfc 0x11 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovaps %ymm1, %ymm0
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xfc 0x28 0xc1
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
# CHECK: vmovaps %ymm0, %ymm1
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 06:54:58 +00:00
0xc5 0xfc 0x29 0xc1
# CHECK: movdqa %xmm1, %xmm0
0x66 0x0f 0x6f 0xc1
# CHECK: movdqa %xmm0, %xmm1
0x66 0x0f 0x7f 0xc1
# CHECK: movdqu %xmm1, %xmm0
0xf3 0x0f 0x6f 0xc1
# CHECK: movdqu %xmm0, %xmm1
0xf3 0x0f 0x7f 0xc1
# CHECK: vmovdqa %xmm1, %xmm0
0xc5 0xf9 0x6f 0xc1
# CHECK: vmovdqa %xmm0, %xmm1
0xc5 0xf9 0x7f 0xc1
# CHECK: vmovdqa %ymm1, %ymm0
0xc5 0xfd 0x6f 0xc1
# CHECK: vmovdqa %ymm0, %ymm1
0xc5 0xfd 0x7f 0xc1
# CHECK: vmovdqu %xmm1, %xmm0
0xc5 0xfa 0x6f 0xc1
# CHECK: vmovdqu %xmm0, %xmm1
0xc5 0xfa 0x7f 0xc1
# CHECK: vmovdqu %ymm1, %ymm0
0xc5 0xfe 0x6f 0xc1
# CHECK: vmovdqu %ymm0, %ymm1
0xc5 0xfe 0x7f 0xc1
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 05:55:28 +00:00
# CHECK: vblendvps %xmm4, %xmm1, %xmm2, %xmm3
0xc4 0xe3 0x69 0x4a 0xd9 0x41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 06:41:26 +00:00
# CHECK: vroundpd $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x09 0xc0 0x00
# CHECK: vroundps $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x08 0xc0 0x00
# CHECK: vroundpd $0, %ymm0, %ymm0
0xc4 0xe3 0x7d 0x09 0xc0 0x00
# CHECK: vroundps $0, %ymm0, %ymm0
0xc4 0xe3 0x7d 0x08 0xc0 0x00
# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x0a 0xc0 0x00
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x0b 0xc0 0x00
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
# CHECK: crc32b %al, %eax
0xf2 0x0f 0x38 0xf0 0xc0
# CHECK: crc32w %ax, %eax
0x66 0xf2 0x0f 0x38 0xf1 0xc0
# CHECK: crc32l %eax, %eax
0xf2 0x0f 0x38 0xf1 0xc0
# CHECK: crc32q %rax, %rax
0xf2 0x48 0x0f 0x38 0xf1 0xc0
Fix disassembling of INVEPT and INVVPID to take operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
# CHECK: invept (%rax), %rax
0x66 0x0f 0x38 0x80 0x00
# CHECK: invvpid (%rax), %rax
0x66 0x0f 0x38 0x81 0x00
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 16:56:09 +00:00
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
# CHECK: invpcid (%rax), %rax
0x66 0x0f 0x38 0x82 0x00
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
# CHECK: nop
0x90
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 16:56:09 +00:00
# CHECK: xchgl %r8d, %eax
0x41 0x90
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
# CHECK: xchgq %r8, %rax
0x49 0x90
# CHECK: addb $0, %al
0x04 0x00
# CHECK: addw $0, %ax
0x66 0x05 0x00 0x00
# CHECK: addl $0, %eax
0x05 0x00 0x00 0x00 0x00
# CHECK: addq $0, %rax
0x48 0x05 0x00 0x00 0x00 0x00
# CHECK: adcb $0, %al
0x14 0x00
# CHECK: adcw $0, %ax
0x66 0x15 0x00 0x00
# CHECK: adcl $0, %eax
0x15 0x00 0x00 0x00 0x00
# CHECK: adcq $0, %rax
0x48 0x15 0x00 0x00 0x00 0x00
# CHECK: cmpb $0, %al
0x3c 0x00
# CHECK: cmpw $0, %ax
0x66 0x3d 0x00 0x00
# CHECK: cmpl $0, %eax
0x3d 0x00 0x00 0x00 0x00
# CHECK: cmpq $0, %rax
0x48 0x3d 0x00 0x00 0x00 0x00
# CHECK: testb $0, %al
0xa8 0x00
# CHECK: testw $0, %ax
0x66 0xa9 0x00 0x00
# CHECK: testl $0, %eax
0xa9 0x00 0x00 0x00 0x00
# CHECK: testq $0, %rax
0x48 0xa9 0x00 0x00 0x00 0x00
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
# CHECK: vaddps %xmm3, %xmm15, %xmm0
0xc4 0xe1 0x00 0x58 0xc3
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:28:23 +00:00
# CHECK: movbel (%rax), %eax
0x0f 0x38 0xf0 0x00
# CHECK: movbel %eax, (%rax)
0x0f 0x38 0xf1 0x00
# CHECK: movbew (%rax), %ax
0x66 0x0f 0x38 0xf0 0x00
# CHECK: movbew %ax, (%rax)
0x66 0x0f 0x38 0xf1 0x00
# CHECK: movbeq (%rax), %rax
0x48 0x0f 0x38 0xf0 0x00
# CHECK: movbeq %rax, (%rax)
0x48 0x0f 0x38 0xf1 0x00
# CHECK: rdrandw %ax
0x66 0x0f 0xc7 0xf0
# CHECK: rdrandl %eax
0x0f 0xc7 0xf0
# CHECK: rdrandq %rax
0x48 0x0f 0xc7 0xf0
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x7d 0x0a 0xc0 0x00
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x7d 0x0b 0xc0 0x00
# CHECK: vcvtsd2si %xmm0, %eax
0xc4 0xe1 0x7f 0x2d 0xc0
# CHECK: vcvtsd2si %xmm0, %rax
0xc4 0xe1 0xff 0x2d 0xc0
# CHECK: vucomisd %xmm1, %xmm0
0xc5 0xfd 0x2e 0xc1
# CHECK: vucomiss %xmm1, %xmm0
0xc5 0xfc 0x2e 0xc1
# CHECK: vcomisd %xmm1, %xmm0
0xc5 0xfd 0x2f 0xc1
# CHECK: vcomiss %xmm1, %xmm0
0xc5 0xfc 0x2f 0xc1
# CHECK: vaddss %xmm1, %xmm0, %xmm0
0xc5 0xfe 0x58 0xc1
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
# CHECK: xsave (%rax)
0x0f 0xae 0x20
# CHECK: xrstor (%rax)
0x0f 0xae 0x28
# CHECK: xsaveopt (%rax)
0x0f 0xae 0x30
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: rdfsbasel %eax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x0f 0xae 0xc0
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: rdgsbasel %eax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x0f 0xae 0xc8
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: wrfsbasel %eax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x0f 0xae 0xd0
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: wrgsbasel %eax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x0f 0xae 0xd8
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: rdfsbaseq %rax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x48 0x0f 0xae 0xc0
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: rdgsbaseq %rax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x48 0x0f 0xae 0xc8
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: wrfsbaseq %rax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x48 0x0f 0xae 0xd0
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: wrgsbaseq %rax
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
0xf3 0x48 0x0f 0xae 0xd8
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: vcvtph2ps %xmm0, %xmm0
0xc4 0xe2 0x79 0x13 0xc0
# CHECK: vcvtph2ps (%rax), %xmm0
0xc4 0xe2 0x79 0x13 0x00
# CHECK: vcvtph2ps %xmm0, %ymm0
0xc4 0xe2 0x7d 0x13 0xc0
# CHECK: vcvtph2ps (%rax), %ymm0
0xc4 0xe2 0x7d 0x13 0x00
# CHECK: vcvtps2ph $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x1d 0xc0 0x00
# CHECK: vcvtps2ph $0, %xmm0, (%rax)
0xc4 0xe3 0x79 0x1d 0x00 0x00
# CHECK: vcvtps2ph $0, %ymm0, %xmm0
0xc4 0xe3 0x7d 0x1d 0xc0 0x00
# CHECK: vcvtps2ph $0, %ymm0, (%rax)
0xc4 0xe3 0x7d 0x1d 0x00 0x00
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
# CHECK: popcntl %eax, %eax
0xf3 0x0f 0xb8 0xc0
# CHECK: popcntw %ax, %ax
0x66 0xf3 0x0f 0xb8 0xc0
# CHECK: popcntq %rax, %rax
0xf3 0x48 0x0f 0xb8 0xc0
Add X86 LZCNT instruction. Including instruction selection support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:44:02 +00:00
# CHECK: lzcntl %eax, %eax
0xf3 0x0f 0xbd 0xc0
# CHECK: lzcntw %ax, %ax
0x66 0xf3 0x0f 0xbd 0xc0
# CHECK: lzcntq %rax, %rax
0xf3 0x48 0x0f 0xbd 0xc0
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
# CHECK: tzcntl %eax, %eax
0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntw %ax, %ax
0x66 0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntq %rax, %rax
0xf3 0x48 0x0f 0xbc 0xc0
Add X86 ANDN instruction. Including instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
# CHECK: andnl %ecx, %r15d, %eax
0xc4 0xe2 0x00 0xf2 0xc1
# CHECK: andnq %rax, %r15, %rax
0xc4 0xe2 0x80 0xf2 0xc0
# CHECK: andnl (%rax), %r15d, %eax
0xc4 0xe2 0x00 0xf2 0x00
# CHECK: andnq (%rax), %r15, %rax
0xc4 0xe2 0x80 0xf2 0x00
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
# CHECK: blsrl (%rax), %r15d
0xc4 0xe2 0x00 0xf3 0x08
# CHECK: blsrq (%rax), %r15
0xc4 0xe2 0x80 0xf3 0x08
# CHECK: blsmskl (%rax), %r15d
0xc4 0xe2 0x00 0xf3 0x10
# CHECK: blsmskq (%rax), %r15
0xc4 0xe2 0x80 0xf3 0x10
# CHECK: blsil (%rax), %r15d
0xc4 0xe2 0x00 0xf3 0x18
# CHECK: blsiq (%rax), %r15
0xc4 0xe2 0x80 0xf3 0x18
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
# CHECK: bextrl %r12d, (%rax), %r10d
0xc4 0x62 0x18 0xf7 0x10
# CHECK: bextrl %r12d, %r11d, %r10d
0xc4 0x42 0x18 0xf7 0xd3
# CHECK: bextrq %r12, (%rax), %r10
0xc4 0x62 0x98 0xf7 0x10
# CHECK: bextrq %r12, %r11, %r10
0xc4 0x42 0x98 0xf7 0xd3
Add X86 BZHI instruction as well as BMI2 feature detection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
# CHECK: bzhil %r12d, (%rax), %r10d
0xc4 0x62 0x18 0xf5 0x10
# CHECK: bzhil %r12d, %r11d, %r10d
0xc4 0x42 0x18 0xf5 0xd3
# CHECK: bzhiq %r12, (%rax), %r10
0xc4 0x62 0x98 0xf5 0x10
# CHECK: bzhiq %r12, %r11, %r10
0xc4 0x42 0x98 0xf5 0xd3
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextl %r12d, %r11d, %r10d
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0x42 0x22 0xf5 0xd4
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextl (%rax), %r11d, %r10d
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0x62 0x22 0xf5 0x10
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextq %r12, %r11, %r10
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0x42 0xa2 0xf5 0xd4
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextq (%rax), %r11, %r10
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0x62 0xa2 0xf5 0x10
# CHECK: pdepl %r12d, %r11d, %r10d
0xc4 0x42 0x23 0xf5 0xd4
# CHECK: pdepl (%rax), %r11d, %r10d
0xc4 0x62 0x23 0xf5 0x10
# CHECK: pdepq %r12, %r11, %r10
0xc4 0x42 0xa3 0xf5 0xd4
# CHECK: pdepq (%rax), %r11, %r10
0xc4 0x62 0xa3 0xf5 0x10
Add X86 MULX instruction for disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 00:33:32 +00:00
# CHECK: mulxl %r12d, %r11d, %r10d
0xc4 0x42 0x23 0xf6 0xd4
# CHECK: mulxl (%rax), %r11d, %r10d
0xc4 0x62 0x23 0xf6 0x10
# CHECK: mulxq %r12, %r11, %r10
0xc4 0x42 0xa3 0xf6 0xd4
# CHECK: mulxq (%rax), %r11, %r10
0xc4 0x62 0xa3 0xf6 0x10
Add X86 RORX instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 07:34:00 +00:00
# CHECK: rorxl $1, %r12d, %r10d
0xc4 0x43 0x7b 0xf0 0xd4 0x01
# CHECK: rorxl $31, (%rax), %r10d
0xc4 0x63 0x7b 0xf0 0x10 0x1f
# CHECK: rorxq $1, %r12, %r10
0xc4 0x43 0xfb 0xf0 0xd4 0x01
# CHECK: rorxq $63, (%rax), %r10
0xc4 0x63 0xfb 0xf0 0x10 0x3f
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