2005-09-01 23:24:04 +00:00
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//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
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2005-09-01 00:19:25 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Nate Begeman and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
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// both before and after the DAG is legalized.
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//
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// FIXME: Missing folds
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// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
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// a sequence of multiplies, shifts, and adds. This should be controlled by
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// some kind of hint from the target that int div is expensive.
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// various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
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//
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2005-09-19 22:34:01 +00:00
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// FIXME: select C, pow2, pow2 -> something smart
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// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
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// FIXME: Dead stores -> nuke
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Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
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// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
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2005-09-01 00:19:25 +00:00
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// FIXME: mul (x, const) -> shifts + adds
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// FIXME: undef values
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2005-09-01 23:24:04 +00:00
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// FIXME: make truncate see through SIGN_EXTEND and AND
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2005-09-02 21:18:40 +00:00
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// FIXME: divide by zero is currently left unfolded. do we want to turn this
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// into an undef?
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2005-10-08 00:29:44 +00:00
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// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
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2005-09-01 00:19:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dagcombine"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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2005-09-07 00:15:36 +00:00
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#include "llvm/Support/Debug.h"
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2005-09-01 00:19:25 +00:00
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetLowering.h"
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2005-09-09 23:53:39 +00:00
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#include <algorithm>
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2005-09-01 00:19:25 +00:00
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#include <cmath>
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2006-01-22 23:41:00 +00:00
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#include <iostream>
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2005-09-01 00:19:25 +00:00
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using namespace llvm;
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namespace {
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Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
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class DAGCombiner {
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SelectionDAG &DAG;
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TargetLowering &TLI;
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2005-09-01 23:24:04 +00:00
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bool AfterLegalize;
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2005-09-01 00:19:25 +00:00
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// Worklist of all of the nodes that need to be simplified.
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std::vector<SDNode*> WorkList;
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/// AddUsersToWorkList - When an instruction is simplified, add all users of
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/// the instruction to the work lists because they might get more simplified
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/// now.
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///
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void AddUsersToWorkList(SDNode *N) {
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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2005-09-01 23:24:04 +00:00
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UI != UE; ++UI)
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WorkList.push_back(*UI);
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2005-09-01 00:19:25 +00:00
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}
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/// removeFromWorkList - remove all instances of N from the worklist.
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2006-03-01 04:03:14 +00:00
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///
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2005-09-01 00:19:25 +00:00
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void removeFromWorkList(SDNode *N) {
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WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
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WorkList.end());
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}
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2006-03-01 04:53:38 +00:00
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public:
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2006-03-01 04:03:14 +00:00
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void AddToWorkList(SDNode *N) {
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WorkList.push_back(N);
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}
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Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
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SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
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2005-10-10 22:31:19 +00:00
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++NodesCombined;
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Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
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DEBUG(std::cerr << "\nReplacing "; N->dump();
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std::cerr << "\nWith: "; To[0].Val->dump();
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std::cerr << " and " << To.size()-1 << " other values\n");
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std::vector<SDNode*> NowDead;
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DAG.ReplaceAllUsesWith(N, To, &NowDead);
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// Push the new nodes and any users onto the worklist
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for (unsigned i = 0, e = To.size(); i != e; ++i) {
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WorkList.push_back(To[i].Val);
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AddUsersToWorkList(To[i].Val);
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}
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// Nodes can end up on the worklist more than once. Make sure we do
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// not process a node that has been replaced.
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removeFromWorkList(N);
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for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
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removeFromWorkList(NowDead[i]);
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// Finally, since the node is now dead, remove it from the graph.
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DAG.DeleteNode(N);
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return SDOperand(N, 0);
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}
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2006-02-16 21:11:51 +00:00
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2006-03-01 04:53:38 +00:00
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SDOperand CombineTo(SDNode *N, SDOperand Res) {
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std::vector<SDOperand> To;
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To.push_back(Res);
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return CombineTo(N, To);
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}
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SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
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std::vector<SDOperand> To;
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To.push_back(Res0);
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To.push_back(Res1);
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return CombineTo(N, To);
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}
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private:
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2006-02-17 21:58:01 +00:00
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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2006-03-01 19:55:35 +00:00
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/// it can be simplified or if things it uses can be simplified by bit
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2006-02-17 21:58:01 +00:00
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/// propagation. If so, return true.
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bool SimplifyDemandedBits(SDOperand Op) {
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2006-02-16 21:11:51 +00:00
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TargetLowering::TargetLoweringOpt TLO(DAG);
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uint64_t KnownZero, KnownOne;
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2006-02-17 21:58:01 +00:00
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uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
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if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
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return false;
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// Revisit the node.
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WorkList.push_back(Op.Val);
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// Replace the old value with the new one.
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++NodesCombined;
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DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
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std::cerr << "\nWith: "; TLO.New.Val->dump());
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std::vector<SDNode*> NowDead;
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DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
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2006-02-20 06:51:04 +00:00
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// Push the new node and any (possibly new) users onto the worklist.
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2006-02-17 21:58:01 +00:00
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WorkList.push_back(TLO.New.Val);
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AddUsersToWorkList(TLO.New.Val);
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// Nodes can end up on the worklist more than once. Make sure we do
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// not process a node that has been replaced.
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for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
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removeFromWorkList(NowDead[i]);
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2006-02-20 06:51:04 +00:00
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// Finally, if the node is now dead, remove it from the graph. The node
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// may not be dead if the replacement process recursively simplified to
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// something else needing this node.
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if (TLO.Old.Val->use_empty()) {
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removeFromWorkList(TLO.Old.Val);
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DAG.DeleteNode(TLO.Old.Val);
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}
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2006-02-17 21:58:01 +00:00
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return true;
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2006-02-16 21:11:51 +00:00
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}
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2005-10-10 22:31:19 +00:00
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2005-09-01 00:19:25 +00:00
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/// visit - call the node-specific routine that knows how to fold each
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/// particular type of node.
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2005-09-06 04:43:02 +00:00
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SDOperand visit(SDNode *N);
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2005-09-01 00:19:25 +00:00
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// Visitation implementation - Implement dag node combining for different
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// node types. The semantics are as follows:
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// Return Value:
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2005-09-07 00:15:36 +00:00
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// SDOperand.Val == 0 - No change was made
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Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
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// SDOperand.Val == N - N was replaced, is dead, and is already handled.
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2005-09-07 00:15:36 +00:00
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// otherwise - N should be replaced by the returned Operand.
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2005-09-01 00:19:25 +00:00
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//
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2005-09-06 04:43:02 +00:00
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SDOperand visitTokenFactor(SDNode *N);
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SDOperand visitADD(SDNode *N);
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SDOperand visitSUB(SDNode *N);
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SDOperand visitMUL(SDNode *N);
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SDOperand visitSDIV(SDNode *N);
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SDOperand visitUDIV(SDNode *N);
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SDOperand visitSREM(SDNode *N);
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SDOperand visitUREM(SDNode *N);
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SDOperand visitMULHU(SDNode *N);
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SDOperand visitMULHS(SDNode *N);
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SDOperand visitAND(SDNode *N);
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SDOperand visitOR(SDNode *N);
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SDOperand visitXOR(SDNode *N);
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SDOperand visitSHL(SDNode *N);
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SDOperand visitSRA(SDNode *N);
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SDOperand visitSRL(SDNode *N);
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SDOperand visitCTLZ(SDNode *N);
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SDOperand visitCTTZ(SDNode *N);
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SDOperand visitCTPOP(SDNode *N);
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2005-09-16 00:54:12 +00:00
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SDOperand visitSELECT(SDNode *N);
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SDOperand visitSELECT_CC(SDNode *N);
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SDOperand visitSETCC(SDNode *N);
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2005-09-06 04:43:02 +00:00
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SDOperand visitSIGN_EXTEND(SDNode *N);
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SDOperand visitZERO_EXTEND(SDNode *N);
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SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
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SDOperand visitTRUNCATE(SDNode *N);
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constant fold bits_convert in getNode and in the dag combiner for fp<->int
conversions. This allows V8 to compiles this:
void %test() {
call float %test2( float 1.000000e+00, float 2.000000e+00, double 3.000000e+00, double* null )
ret void
}
into:
test:
save -96, %o6, %o6
sethi 0, %o3
sethi 1049088, %o2
sethi 1048576, %o1
sethi 1040384, %o0
or %g0, %o3, %o4
call test2
nop
restore %g0, %g0, %g0
retl
nop
instead of:
test:
save -112, %o6, %o6
sethi 0, %o4
sethi 1049088, %l0
st %o4, [%i6+-12]
st %l0, [%i6+-16]
ld [%i6+-12], %o3
ld [%i6+-16], %o2
sethi 1048576, %o1
sethi 1040384, %o0
call test2
nop
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24980 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:30:37 +00:00
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SDOperand visitBIT_CONVERT(SDNode *N);
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2005-09-28 22:28:18 +00:00
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SDOperand visitFADD(SDNode *N);
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SDOperand visitFSUB(SDNode *N);
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SDOperand visitFMUL(SDNode *N);
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SDOperand visitFDIV(SDNode *N);
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SDOperand visitFREM(SDNode *N);
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2006-03-05 05:30:57 +00:00
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SDOperand visitFCOPYSIGN(SDNode *N);
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2005-09-06 04:43:02 +00:00
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SDOperand visitSINT_TO_FP(SDNode *N);
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SDOperand visitUINT_TO_FP(SDNode *N);
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SDOperand visitFP_TO_SINT(SDNode *N);
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SDOperand visitFP_TO_UINT(SDNode *N);
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SDOperand visitFP_ROUND(SDNode *N);
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SDOperand visitFP_ROUND_INREG(SDNode *N);
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SDOperand visitFP_EXTEND(SDNode *N);
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SDOperand visitFNEG(SDNode *N);
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SDOperand visitFABS(SDNode *N);
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2005-09-16 00:54:12 +00:00
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SDOperand visitBRCOND(SDNode *N);
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2005-09-19 22:34:01 +00:00
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SDOperand visitBR_CC(SDNode *N);
|
Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
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SDOperand visitLOAD(SDNode *N);
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2005-10-10 22:31:19 +00:00
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SDOperand visitSTORE(SDNode *N);
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2006-03-19 01:27:56 +00:00
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SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
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SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
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Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
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2006-02-03 06:46:56 +00:00
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SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
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|
|
|
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
|
|
|
|
SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
|
|
|
|
SDOperand N3, ISD::CondCode CC);
|
2005-09-16 00:54:12 +00:00
|
|
|
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
|
2005-10-05 21:43:42 +00:00
|
|
|
ISD::CondCode Cond, bool foldBooleans = true);
|
2005-10-20 02:15:44 +00:00
|
|
|
|
|
|
|
SDOperand BuildSDIV(SDNode *N);
|
|
|
|
SDOperand BuildUDIV(SDNode *N);
|
2005-09-01 00:19:25 +00:00
|
|
|
public:
|
|
|
|
DAGCombiner(SelectionDAG &D)
|
2005-09-02 21:18:40 +00:00
|
|
|
: DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
/// Run - runs the dag combiner on all nodes in the work list
|
2005-09-01 23:24:04 +00:00
|
|
|
void Run(bool RunningAfterLegalize);
|
2005-09-01 00:19:25 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2006-03-01 04:53:38 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// TargetLowering::DAGCombinerInfo implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
|
|
|
|
((DAGCombiner*)DC)->AddToWorkList(N);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand TargetLowering::DAGCombinerInfo::
|
|
|
|
CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
|
|
|
|
return ((DAGCombiner*)DC)->CombineTo(N, To);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand TargetLowering::DAGCombinerInfo::
|
|
|
|
CombineTo(SDNode *N, SDOperand Res) {
|
|
|
|
return ((DAGCombiner*)DC)->CombineTo(N, Res);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
SDOperand TargetLowering::DAGCombinerInfo::
|
|
|
|
CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
|
|
|
|
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
2005-10-20 02:15:44 +00:00
|
|
|
struct ms {
|
|
|
|
int64_t m; // magic number
|
|
|
|
int64_t s; // shift amount
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mu {
|
|
|
|
uint64_t m; // magic number
|
|
|
|
int64_t a; // add indicator
|
|
|
|
int64_t s; // shift amount
|
|
|
|
};
|
|
|
|
|
|
|
|
/// magic - calculate the magic numbers required to codegen an integer sdiv as
|
|
|
|
/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
|
|
|
|
/// or -1.
|
|
|
|
static ms magic32(int32_t d) {
|
|
|
|
int32_t p;
|
|
|
|
uint32_t ad, anc, delta, q1, r1, q2, r2, t;
|
|
|
|
const uint32_t two31 = 0x80000000U;
|
|
|
|
struct ms mag;
|
|
|
|
|
|
|
|
ad = abs(d);
|
|
|
|
t = two31 + ((uint32_t)d >> 31);
|
|
|
|
anc = t - 1 - t%ad; // absolute value of nc
|
|
|
|
p = 31; // initialize p
|
|
|
|
q1 = two31/anc; // initialize q1 = 2p/abs(nc)
|
|
|
|
r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
|
|
|
|
q2 = two31/ad; // initialize q2 = 2p/abs(d)
|
|
|
|
r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
q1 = 2*q1; // update q1 = 2p/abs(nc)
|
|
|
|
r1 = 2*r1; // update r1 = rem(2p/abs(nc))
|
|
|
|
if (r1 >= anc) { // must be unsigned comparison
|
|
|
|
q1 = q1 + 1;
|
|
|
|
r1 = r1 - anc;
|
|
|
|
}
|
|
|
|
q2 = 2*q2; // update q2 = 2p/abs(d)
|
|
|
|
r2 = 2*r2; // update r2 = rem(2p/abs(d))
|
|
|
|
if (r2 >= ad) { // must be unsigned comparison
|
|
|
|
q2 = q2 + 1;
|
|
|
|
r2 = r2 - ad;
|
|
|
|
}
|
|
|
|
delta = ad - r2;
|
|
|
|
} while (q1 < delta || (q1 == delta && r1 == 0));
|
|
|
|
|
|
|
|
mag.m = (int32_t)(q2 + 1); // make sure to sign extend
|
|
|
|
if (d < 0) mag.m = -mag.m; // resulting magic number
|
|
|
|
mag.s = p - 32; // resulting shift
|
|
|
|
return mag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// magicu - calculate the magic numbers required to codegen an integer udiv as
|
|
|
|
/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
|
|
|
|
static mu magicu32(uint32_t d) {
|
|
|
|
int32_t p;
|
|
|
|
uint32_t nc, delta, q1, r1, q2, r2;
|
|
|
|
struct mu magu;
|
|
|
|
magu.a = 0; // initialize "add" indicator
|
|
|
|
nc = - 1 - (-d)%d;
|
|
|
|
p = 31; // initialize p
|
|
|
|
q1 = 0x80000000/nc; // initialize q1 = 2p/nc
|
|
|
|
r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
|
|
|
|
q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
|
|
|
|
r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
if (r1 >= nc - r1 ) {
|
|
|
|
q1 = 2*q1 + 1; // update q1
|
|
|
|
r1 = 2*r1 - nc; // update r1
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
q1 = 2*q1; // update q1
|
|
|
|
r1 = 2*r1; // update r1
|
|
|
|
}
|
|
|
|
if (r2 + 1 >= d - r2) {
|
|
|
|
if (q2 >= 0x7FFFFFFF) magu.a = 1;
|
|
|
|
q2 = 2*q2 + 1; // update q2
|
|
|
|
r2 = 2*r2 + 1 - d; // update r2
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if (q2 >= 0x80000000) magu.a = 1;
|
|
|
|
q2 = 2*q2; // update q2
|
|
|
|
r2 = 2*r2 + 1; // update r2
|
|
|
|
}
|
|
|
|
delta = d - 1 - r2;
|
|
|
|
} while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
|
|
|
|
magu.m = q2 + 1; // resulting magic number
|
|
|
|
magu.s = p - 32; // resulting shift
|
|
|
|
return magu;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// magic - calculate the magic numbers required to codegen an integer sdiv as
|
|
|
|
/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
|
|
|
|
/// or -1.
|
|
|
|
static ms magic64(int64_t d) {
|
|
|
|
int64_t p;
|
|
|
|
uint64_t ad, anc, delta, q1, r1, q2, r2, t;
|
|
|
|
const uint64_t two63 = 9223372036854775808ULL; // 2^63
|
|
|
|
struct ms mag;
|
|
|
|
|
2005-10-20 17:01:00 +00:00
|
|
|
ad = d >= 0 ? d : -d;
|
2005-10-20 02:15:44 +00:00
|
|
|
t = two63 + ((uint64_t)d >> 63);
|
|
|
|
anc = t - 1 - t%ad; // absolute value of nc
|
|
|
|
p = 63; // initialize p
|
|
|
|
q1 = two63/anc; // initialize q1 = 2p/abs(nc)
|
|
|
|
r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
|
|
|
|
q2 = two63/ad; // initialize q2 = 2p/abs(d)
|
|
|
|
r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
q1 = 2*q1; // update q1 = 2p/abs(nc)
|
|
|
|
r1 = 2*r1; // update r1 = rem(2p/abs(nc))
|
|
|
|
if (r1 >= anc) { // must be unsigned comparison
|
|
|
|
q1 = q1 + 1;
|
|
|
|
r1 = r1 - anc;
|
|
|
|
}
|
|
|
|
q2 = 2*q2; // update q2 = 2p/abs(d)
|
|
|
|
r2 = 2*r2; // update r2 = rem(2p/abs(d))
|
|
|
|
if (r2 >= ad) { // must be unsigned comparison
|
|
|
|
q2 = q2 + 1;
|
|
|
|
r2 = r2 - ad;
|
|
|
|
}
|
|
|
|
delta = ad - r2;
|
|
|
|
} while (q1 < delta || (q1 == delta && r1 == 0));
|
|
|
|
|
|
|
|
mag.m = q2 + 1;
|
|
|
|
if (d < 0) mag.m = -mag.m; // resulting magic number
|
|
|
|
mag.s = p - 64; // resulting shift
|
|
|
|
return mag;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// magicu - calculate the magic numbers required to codegen an integer udiv as
|
|
|
|
/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
|
|
|
|
static mu magicu64(uint64_t d)
|
|
|
|
{
|
|
|
|
int64_t p;
|
|
|
|
uint64_t nc, delta, q1, r1, q2, r2;
|
|
|
|
struct mu magu;
|
|
|
|
magu.a = 0; // initialize "add" indicator
|
|
|
|
nc = - 1 - (-d)%d;
|
|
|
|
p = 63; // initialize p
|
|
|
|
q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
|
|
|
|
r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
|
|
|
|
q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
|
|
|
|
r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
|
|
|
|
do {
|
|
|
|
p = p + 1;
|
|
|
|
if (r1 >= nc - r1 ) {
|
|
|
|
q1 = 2*q1 + 1; // update q1
|
|
|
|
r1 = 2*r1 - nc; // update r1
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
q1 = 2*q1; // update q1
|
|
|
|
r1 = 2*r1; // update r1
|
|
|
|
}
|
|
|
|
if (r2 + 1 >= d - r2) {
|
|
|
|
if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
|
|
|
|
q2 = 2*q2 + 1; // update q2
|
|
|
|
r2 = 2*r2 + 1 - d; // update r2
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if (q2 >= 0x8000000000000000ull) magu.a = 1;
|
|
|
|
q2 = 2*q2; // update q2
|
|
|
|
r2 = 2*r2 + 1; // update r2
|
|
|
|
}
|
|
|
|
delta = d - 1 - r2;
|
|
|
|
} while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
|
|
|
|
magu.m = q2 + 1; // resulting magic number
|
|
|
|
magu.s = p - 64; // resulting shift
|
|
|
|
return magu;
|
|
|
|
}
|
|
|
|
|
2005-09-01 23:24:04 +00:00
|
|
|
// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
|
|
|
|
// that selects between the values 1 and 0, making it equivalent to a setcc.
|
2005-09-02 21:18:40 +00:00
|
|
|
// Also, set the incoming LHS, RHS, and CC references to the appropriate
|
|
|
|
// nodes based on the type of node we are checking. This simplifies life a
|
|
|
|
// bit for the callers.
|
|
|
|
static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
|
|
|
|
SDOperand &CC) {
|
|
|
|
if (N.getOpcode() == ISD::SETCC) {
|
|
|
|
LHS = N.getOperand(0);
|
|
|
|
RHS = N.getOperand(1);
|
|
|
|
CC = N.getOperand(2);
|
2005-09-01 23:24:04 +00:00
|
|
|
return true;
|
2005-09-02 21:18:40 +00:00
|
|
|
}
|
2005-09-01 00:19:25 +00:00
|
|
|
if (N.getOpcode() == ISD::SELECT_CC &&
|
|
|
|
N.getOperand(2).getOpcode() == ISD::Constant &&
|
|
|
|
N.getOperand(3).getOpcode() == ISD::Constant &&
|
|
|
|
cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
|
2005-09-02 21:18:40 +00:00
|
|
|
cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
|
|
|
|
LHS = N.getOperand(0);
|
|
|
|
RHS = N.getOperand(1);
|
|
|
|
CC = N.getOperand(4);
|
2005-09-01 00:19:25 +00:00
|
|
|
return true;
|
2005-09-02 21:18:40 +00:00
|
|
|
}
|
2005-09-01 00:19:25 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-09-07 23:25:52 +00:00
|
|
|
// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
|
|
|
|
// one use. If this is true, it allows the users to invert the operation for
|
|
|
|
// free when it is profitable to do so.
|
|
|
|
static bool isOneUseSetCC(SDOperand N) {
|
2005-09-02 21:18:40 +00:00
|
|
|
SDOperand N0, N1, N2;
|
|
|
|
if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
|
2005-09-01 23:24:04 +00:00
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
// FIXME: This should probably go in the ISD class rather than being duplicated
|
|
|
|
// in several files.
|
|
|
|
static bool isCommutativeBinOp(unsigned Opcode) {
|
|
|
|
switch (Opcode) {
|
|
|
|
case ISD::ADD:
|
|
|
|
case ISD::MUL:
|
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR: return true;
|
|
|
|
default: return false; // FIXME: Need commutative info for user ops!
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-03 06:46:56 +00:00
|
|
|
SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
|
|
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
// reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
|
|
|
|
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
|
|
|
|
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
if (isa<ConstantSDNode>(N1)) {
|
|
|
|
SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(OpNode.Val);
|
2006-02-03 06:46:56 +00:00
|
|
|
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
|
|
|
|
} else if (N0.hasOneUse()) {
|
|
|
|
SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(OpNode.Val);
|
2006-02-03 06:46:56 +00:00
|
|
|
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
|
|
|
|
// reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
|
|
|
|
if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
|
|
|
|
if (isa<ConstantSDNode>(N0)) {
|
|
|
|
SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(OpNode.Val);
|
2006-02-03 06:46:56 +00:00
|
|
|
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
|
|
|
|
} else if (N1.hasOneUse()) {
|
|
|
|
SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(OpNode.Val);
|
2006-02-03 06:46:56 +00:00
|
|
|
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-09-01 23:24:04 +00:00
|
|
|
void DAGCombiner::Run(bool RunningAfterLegalize) {
|
|
|
|
// set the instance variable, so that the various visit routines may use it.
|
|
|
|
AfterLegalize = RunningAfterLegalize;
|
|
|
|
|
2005-09-02 21:18:40 +00:00
|
|
|
// Add all the dag nodes to the worklist.
|
2005-11-09 23:47:37 +00:00
|
|
|
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
|
|
|
|
E = DAG.allnodes_end(); I != E; ++I)
|
|
|
|
WorkList.push_back(I);
|
2005-09-06 04:43:02 +00:00
|
|
|
|
2005-10-05 06:35:28 +00:00
|
|
|
// Create a dummy node (which is not added to allnodes), that adds a reference
|
|
|
|
// to the root node, preventing it from being deleted, and tracking any
|
|
|
|
// changes of the root.
|
|
|
|
HandleSDNode Dummy(DAG.getRoot());
|
|
|
|
|
2006-03-01 04:53:38 +00:00
|
|
|
|
|
|
|
/// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
|
|
|
|
TargetLowering::DAGCombinerInfo
|
|
|
|
DagCombineInfo(DAG, !RunningAfterLegalize, this);
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// while the worklist isn't empty, inspect the node on the end of it and
|
|
|
|
// try and combine it.
|
|
|
|
while (!WorkList.empty()) {
|
|
|
|
SDNode *N = WorkList.back();
|
|
|
|
WorkList.pop_back();
|
|
|
|
|
|
|
|
// If N has no uses, it is dead. Make sure to revisit all N's operands once
|
2005-10-05 06:35:28 +00:00
|
|
|
// N is deleted from the DAG, since they too may now be dead or may have a
|
|
|
|
// reduced number of uses, allowing other xforms.
|
|
|
|
if (N->use_empty() && N != &Dummy) {
|
2005-09-01 00:19:25 +00:00
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
|
|
|
|
WorkList.push_back(N->getOperand(i).Val);
|
|
|
|
|
|
|
|
removeFromWorkList(N);
|
2005-10-05 06:35:28 +00:00
|
|
|
DAG.DeleteNode(N);
|
2005-09-01 00:19:25 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand RV = visit(N);
|
2006-03-01 04:53:38 +00:00
|
|
|
|
|
|
|
// If nothing happened, try a target-specific DAG combine.
|
|
|
|
if (RV.Val == 0) {
|
|
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
|
|
|
|
TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
|
|
|
|
RV = TLI.PerformDAGCombine(N, DagCombineInfo);
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
if (RV.Val) {
|
2005-09-01 00:19:25 +00:00
|
|
|
++NodesCombined;
|
2005-09-02 21:18:40 +00:00
|
|
|
// If we get back the same node we passed in, rather than a new node or
|
|
|
|
// zero, we know that the node must have defined multiple values and
|
|
|
|
// CombineTo was used. Since CombineTo takes care of the worklist
|
|
|
|
// mechanics for us, we have no work to do in this case.
|
2005-09-06 04:43:02 +00:00
|
|
|
if (RV.Val != N) {
|
2005-09-07 00:15:36 +00:00
|
|
|
DEBUG(std::cerr << "\nReplacing "; N->dump();
|
|
|
|
std::cerr << "\nWith: "; RV.Val->dump();
|
|
|
|
std::cerr << '\n');
|
Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
|
|
|
std::vector<SDNode*> NowDead;
|
|
|
|
DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
|
2005-09-02 21:18:40 +00:00
|
|
|
|
|
|
|
// Push the new node and any users onto the worklist
|
2005-09-06 04:43:02 +00:00
|
|
|
WorkList.push_back(RV.Val);
|
|
|
|
AddUsersToWorkList(RV.Val);
|
2005-09-02 21:18:40 +00:00
|
|
|
|
|
|
|
// Nodes can end up on the worklist more than once. Make sure we do
|
|
|
|
// not process a node that has been replaced.
|
|
|
|
removeFromWorkList(N);
|
Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
|
|
|
for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
|
|
|
|
removeFromWorkList(NowDead[i]);
|
2005-10-05 06:11:08 +00:00
|
|
|
|
|
|
|
// Finally, since the node is now dead, remove it from the graph.
|
|
|
|
DAG.DeleteNode(N);
|
2005-09-02 21:18:40 +00:00
|
|
|
}
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
}
|
2005-10-05 06:35:28 +00:00
|
|
|
|
|
|
|
// If the root changed (e.g. it was a dead load, update the root).
|
|
|
|
DAG.setRoot(Dummy.getValue());
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visit(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
switch(N->getOpcode()) {
|
|
|
|
default: break;
|
2005-09-01 00:33:32 +00:00
|
|
|
case ISD::TokenFactor: return visitTokenFactor(N);
|
2005-09-02 21:18:40 +00:00
|
|
|
case ISD::ADD: return visitADD(N);
|
|
|
|
case ISD::SUB: return visitSUB(N);
|
|
|
|
case ISD::MUL: return visitMUL(N);
|
|
|
|
case ISD::SDIV: return visitSDIV(N);
|
|
|
|
case ISD::UDIV: return visitUDIV(N);
|
|
|
|
case ISD::SREM: return visitSREM(N);
|
|
|
|
case ISD::UREM: return visitUREM(N);
|
|
|
|
case ISD::MULHU: return visitMULHU(N);
|
|
|
|
case ISD::MULHS: return visitMULHS(N);
|
|
|
|
case ISD::AND: return visitAND(N);
|
|
|
|
case ISD::OR: return visitOR(N);
|
|
|
|
case ISD::XOR: return visitXOR(N);
|
|
|
|
case ISD::SHL: return visitSHL(N);
|
|
|
|
case ISD::SRA: return visitSRA(N);
|
|
|
|
case ISD::SRL: return visitSRL(N);
|
|
|
|
case ISD::CTLZ: return visitCTLZ(N);
|
|
|
|
case ISD::CTTZ: return visitCTTZ(N);
|
|
|
|
case ISD::CTPOP: return visitCTPOP(N);
|
2005-09-16 00:54:12 +00:00
|
|
|
case ISD::SELECT: return visitSELECT(N);
|
|
|
|
case ISD::SELECT_CC: return visitSELECT_CC(N);
|
|
|
|
case ISD::SETCC: return visitSETCC(N);
|
2005-09-02 21:18:40 +00:00
|
|
|
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
|
|
|
|
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
|
|
|
|
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
|
|
|
|
case ISD::TRUNCATE: return visitTRUNCATE(N);
|
constant fold bits_convert in getNode and in the dag combiner for fp<->int
conversions. This allows V8 to compiles this:
void %test() {
call float %test2( float 1.000000e+00, float 2.000000e+00, double 3.000000e+00, double* null )
ret void
}
into:
test:
save -96, %o6, %o6
sethi 0, %o3
sethi 1049088, %o2
sethi 1048576, %o1
sethi 1040384, %o0
or %g0, %o3, %o4
call test2
nop
restore %g0, %g0, %g0
retl
nop
instead of:
test:
save -112, %o6, %o6
sethi 0, %o4
sethi 1049088, %l0
st %o4, [%i6+-12]
st %l0, [%i6+-16]
ld [%i6+-12], %o3
ld [%i6+-16], %o2
sethi 1048576, %o1
sethi 1040384, %o0
call test2
nop
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24980 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:30:37 +00:00
|
|
|
case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
|
2005-09-28 22:28:18 +00:00
|
|
|
case ISD::FADD: return visitFADD(N);
|
|
|
|
case ISD::FSUB: return visitFSUB(N);
|
|
|
|
case ISD::FMUL: return visitFMUL(N);
|
|
|
|
case ISD::FDIV: return visitFDIV(N);
|
|
|
|
case ISD::FREM: return visitFREM(N);
|
2006-03-05 05:30:57 +00:00
|
|
|
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
|
2005-09-02 21:18:40 +00:00
|
|
|
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
|
|
|
|
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
|
|
|
|
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
|
|
|
|
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
|
|
|
|
case ISD::FP_ROUND: return visitFP_ROUND(N);
|
|
|
|
case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
|
|
|
|
case ISD::FP_EXTEND: return visitFP_EXTEND(N);
|
|
|
|
case ISD::FNEG: return visitFNEG(N);
|
|
|
|
case ISD::FABS: return visitFABS(N);
|
2005-09-19 22:34:01 +00:00
|
|
|
case ISD::BRCOND: return visitBRCOND(N);
|
|
|
|
case ISD::BR_CC: return visitBR_CC(N);
|
Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
|
|
|
case ISD::LOAD: return visitLOAD(N);
|
2005-10-10 22:31:19 +00:00
|
|
|
case ISD::STORE: return visitSTORE(N);
|
2006-03-19 01:27:56 +00:00
|
|
|
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
|
|
|
|
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
|
2005-10-13 03:11:28 +00:00
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
bool Changed = false;
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// If the token factor has two operands and one is the entry token, replace
|
|
|
|
// the token factor with the other operand.
|
|
|
|
if (N->getNumOperands() == 2) {
|
|
|
|
if (N->getOperand(0).getOpcode() == ISD::EntryToken)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N->getOperand(1);
|
2005-09-01 00:19:25 +00:00
|
|
|
if (N->getOperand(1).getOpcode() == ISD::EntryToken)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N->getOperand(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-10-13 22:10:05 +00:00
|
|
|
|
2005-10-13 03:11:28 +00:00
|
|
|
// fold (tokenfactor (tokenfactor)) -> tokenfactor
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand Op = N->getOperand(i);
|
|
|
|
if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
|
2006-03-13 18:37:30 +00:00
|
|
|
AddToWorkList(Op.Val); // Remove dead node.
|
2005-10-13 03:11:28 +00:00
|
|
|
Changed = true;
|
|
|
|
for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
|
|
|
|
Ops.push_back(Op.getOperand(j));
|
|
|
|
} else {
|
|
|
|
Ops.push_back(Op);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (Changed)
|
|
|
|
return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitADD(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-07 16:09:19 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (add c1, c2) -> c1+c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::ADD, VT, N0, N1);
|
2005-09-07 23:25:52 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0C && !N1C)
|
|
|
|
return DAG.getNode(ISD::ADD, VT, N1, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (add x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2006-01-12 20:22:43 +00:00
|
|
|
// fold ((c1-A)+c2) -> (c1+c2)-A
|
|
|
|
if (N1C && N0.getOpcode() == ISD::SUB)
|
|
|
|
if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
|
|
|
|
return DAG.getNode(ISD::SUB, VT,
|
|
|
|
DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
|
|
|
|
N0.getOperand(1));
|
2006-02-03 06:46:56 +00:00
|
|
|
// reassociate add
|
|
|
|
SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
|
|
|
|
if (RADD.Val != 0)
|
|
|
|
return RADD;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold ((0-A) + B) -> B-A
|
|
|
|
if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
|
|
|
|
cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
|
2005-09-07 16:09:19 +00:00
|
|
|
return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (A + (0-B)) -> A-B
|
|
|
|
if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
|
|
|
|
cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
|
2005-09-07 16:09:19 +00:00
|
|
|
return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
|
2005-09-28 22:28:18 +00:00
|
|
|
// fold (A+(B-A)) -> B
|
|
|
|
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1.getOperand(0);
|
2006-03-13 06:51:27 +00:00
|
|
|
|
2006-03-01 01:09:54 +00:00
|
|
|
if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
|
2006-02-18 02:40:58 +00:00
|
|
|
return SDOperand();
|
2006-03-13 06:51:27 +00:00
|
|
|
|
|
|
|
// fold (a+b) -> (a|b) iff a and b share no bits.
|
|
|
|
if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
|
|
|
|
uint64_t LHSZero, LHSOne;
|
|
|
|
uint64_t RHSZero, RHSOne;
|
|
|
|
uint64_t Mask = MVT::getIntVTBitMask(VT);
|
|
|
|
TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
|
|
|
|
if (LHSZero) {
|
|
|
|
TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
|
|
|
|
|
|
|
|
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
|
|
|
|
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
|
|
|
|
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
|
|
|
|
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
|
|
|
|
return DAG.getNode(ISD::OR, VT, N0, N1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSUB(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
2005-09-01 00:19:25 +00:00
|
|
|
|
2005-10-17 01:07:11 +00:00
|
|
|
// fold (sub x, x) -> 0
|
|
|
|
if (N0 == N1)
|
|
|
|
return DAG.getConstant(0, N->getValueType(0));
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sub c1, c2) -> c1-c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SUB, VT, N0, N1);
|
2005-10-11 06:07:15 +00:00
|
|
|
// fold (sub x, c) -> (add x, -c)
|
|
|
|
if (N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (A+B)-A -> B
|
2005-09-28 22:28:18 +00:00
|
|
|
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0.getOperand(1);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (A+B)-B -> A
|
2005-09-28 22:28:18 +00:00
|
|
|
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0.getOperand(0);
|
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitMUL(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-08 20:18:10 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (mul c1, c2) -> c1*c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::MUL, VT, N0, N1);
|
2005-09-07 23:25:52 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0C && !N1C)
|
|
|
|
return DAG.getNode(ISD::MUL, VT, N1, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (mul x, 0) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (mul x, -1) -> 0-x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isAllOnesValue())
|
2005-10-21 00:02:42 +00:00
|
|
|
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (mul x, (1 << c)) -> x << c
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && isPowerOf2_64(N1C->getValue()))
|
2005-10-30 06:41:49 +00:00
|
|
|
return DAG.getNode(ISD::SHL, VT, N0,
|
2005-09-02 21:18:40 +00:00
|
|
|
DAG.getConstant(Log2_64(N1C->getValue()),
|
2005-09-06 04:43:02 +00:00
|
|
|
TLI.getShiftAmountTy()));
|
2005-10-30 06:41:49 +00:00
|
|
|
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
|
|
|
|
if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
|
|
|
|
// FIXME: If the input is something that is easily negated (e.g. a
|
|
|
|
// single-use add), we should put the negate there.
|
|
|
|
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
|
|
|
|
DAG.getNode(ISD::SHL, VT, N0,
|
|
|
|
DAG.getConstant(Log2_64(-N1C->getSignExtended()),
|
|
|
|
TLI.getShiftAmountTy())));
|
|
|
|
}
|
2006-03-01 03:44:24 +00:00
|
|
|
|
|
|
|
// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::SHL &&
|
|
|
|
isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(C3.Val);
|
2006-03-01 03:44:24 +00:00
|
|
|
return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
|
|
|
|
// use.
|
|
|
|
{
|
|
|
|
SDOperand Sh(0,0), Y(0,0);
|
|
|
|
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
|
|
|
|
if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
|
|
|
|
N0.Val->hasOneUse()) {
|
|
|
|
Sh = N0; Y = N1;
|
|
|
|
} else if (N1.getOpcode() == ISD::SHL &&
|
|
|
|
isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
|
|
|
|
Sh = N1; Y = N0;
|
|
|
|
}
|
|
|
|
if (Sh.Val) {
|
|
|
|
SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
|
|
|
|
return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
|
|
|
|
}
|
|
|
|
}
|
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26535 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-04 23:33:26 +00:00
|
|
|
// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
return DAG.getNode(ISD::ADD, VT,
|
|
|
|
DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
|
|
|
|
DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
|
|
|
|
}
|
2006-03-01 03:44:24 +00:00
|
|
|
|
2006-02-03 06:46:56 +00:00
|
|
|
// reassociate mul
|
|
|
|
SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
|
|
|
|
if (RMUL.Val != 0)
|
|
|
|
return RMUL;
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSDIV(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (sdiv c1, c2) -> c1/c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C && !N1C->isNullValue())
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SDIV, VT, N0, N1);
|
2005-10-21 00:02:42 +00:00
|
|
|
// fold (sdiv X, 1) -> X
|
|
|
|
if (N1C && N1C->getSignExtended() == 1LL)
|
|
|
|
return N0;
|
|
|
|
// fold (sdiv X, -1) -> 0-X
|
|
|
|
if (N1C && N1C->isAllOnesValue())
|
|
|
|
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
|
2005-10-07 06:10:46 +00:00
|
|
|
// If we know the sign bits of both operands are zero, strength reduce to a
|
|
|
|
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
|
|
|
|
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
|
2006-01-30 04:09:27 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N1, SignBit) &&
|
|
|
|
TLI.MaskedValueIsZero(N0, SignBit))
|
2005-10-07 06:10:46 +00:00
|
|
|
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
|
2006-02-17 07:26:20 +00:00
|
|
|
// fold (sdiv X, pow2) -> simple ops after legalize
|
2006-02-17 19:54:08 +00:00
|
|
|
if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
|
2005-10-21 00:02:42 +00:00
|
|
|
(isPowerOf2_64(N1C->getSignExtended()) ||
|
|
|
|
isPowerOf2_64(-N1C->getSignExtended()))) {
|
|
|
|
// If dividing by powers of two is cheap, then don't perform the following
|
|
|
|
// fold.
|
|
|
|
if (TLI.isPow2DivCheap())
|
|
|
|
return SDOperand();
|
|
|
|
int64_t pow2 = N1C->getSignExtended();
|
|
|
|
int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
|
2006-02-16 08:02:36 +00:00
|
|
|
unsigned lg2 = Log2_64(abs2);
|
|
|
|
// Splat the sign bit into the register
|
|
|
|
SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
|
2005-10-21 00:02:42 +00:00
|
|
|
DAG.getConstant(MVT::getSizeInBits(VT)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SGN.Val);
|
2006-02-16 08:02:36 +00:00
|
|
|
// Add (N0 < 0) ? abs2 - 1 : 0;
|
|
|
|
SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
|
2005-10-21 00:02:42 +00:00
|
|
|
TLI.getShiftAmountTy()));
|
2006-02-16 08:02:36 +00:00
|
|
|
SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SRL.Val);
|
|
|
|
AddToWorkList(ADD.Val); // Divide by pow2
|
2006-02-16 08:02:36 +00:00
|
|
|
SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
|
|
|
|
DAG.getConstant(lg2, TLI.getShiftAmountTy()));
|
2005-10-21 00:02:42 +00:00
|
|
|
// If we're dividing by a positive value, we're done. Otherwise, we must
|
|
|
|
// negate the result.
|
|
|
|
if (pow2 > 0)
|
|
|
|
return SRA;
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SRA.Val);
|
2005-10-21 00:02:42 +00:00
|
|
|
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
|
|
|
|
}
|
2005-10-20 02:15:44 +00:00
|
|
|
// if integer divide is expensive and we satisfy the requirements, emit an
|
|
|
|
// alternate sequence.
|
2005-10-21 00:02:42 +00:00
|
|
|
if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
|
2005-10-22 18:50:15 +00:00
|
|
|
!TLI.isIntDivCheap()) {
|
|
|
|
SDOperand Op = BuildSDIV(N);
|
|
|
|
if (Op.Val) return Op;
|
2005-10-20 02:15:44 +00:00
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitUDIV(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (udiv c1, c2) -> c1/c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C && !N1C->isNullValue())
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::UDIV, VT, N0, N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (udiv x, (1 << c)) -> x >>u c
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && isPowerOf2_64(N1C->getValue()))
|
2006-02-05 07:20:23 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, N0,
|
2005-09-02 21:18:40 +00:00
|
|
|
DAG.getConstant(Log2_64(N1C->getValue()),
|
2005-09-06 04:43:02 +00:00
|
|
|
TLI.getShiftAmountTy()));
|
2006-02-05 07:20:23 +00:00
|
|
|
// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
|
|
|
|
if (N1.getOpcode() == ISD::SHL) {
|
|
|
|
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
|
|
|
|
if (isPowerOf2_64(SHC->getValue())) {
|
|
|
|
MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
|
2006-02-05 07:36:48 +00:00
|
|
|
SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
|
|
|
|
DAG.getConstant(Log2_64(SHC->getValue()),
|
|
|
|
ADDVT));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Add.Val);
|
2006-02-05 07:36:48 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, N0, Add);
|
2006-02-05 07:20:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2005-10-20 02:15:44 +00:00
|
|
|
// fold (udiv x, c) -> alternate
|
2005-10-22 18:50:15 +00:00
|
|
|
if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
|
|
|
|
SDOperand Op = BuildUDIV(N);
|
|
|
|
if (Op.Val) return Op;
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSREM(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (srem c1, c2) -> c1%c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C && !N1C->isNullValue())
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SREM, VT, N0, N1);
|
2005-10-10 21:26:48 +00:00
|
|
|
// If we know the sign bits of both operands are zero, strength reduce to a
|
|
|
|
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
|
|
|
|
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
|
2006-01-30 04:09:27 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N1, SignBit) &&
|
|
|
|
TLI.MaskedValueIsZero(N0, SignBit))
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::UREM, VT, N0, N1);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitUREM(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (urem c1, c2) -> c1%c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C && !N1C->isNullValue())
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::UREM, VT, N0, N1);
|
2005-10-10 21:26:48 +00:00
|
|
|
// fold (urem x, pow2) -> (and x, pow2-1)
|
|
|
|
if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
|
2006-02-05 07:36:48 +00:00
|
|
|
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
|
|
|
|
if (N1.getOpcode() == ISD::SHL) {
|
|
|
|
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
|
|
|
|
if (isPowerOf2_64(SHC->getValue())) {
|
2006-02-05 08:07:24 +00:00
|
|
|
SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Add.Val);
|
2006-02-05 07:36:48 +00:00
|
|
|
return DAG.getNode(ISD::AND, VT, N0, Add);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitMULHS(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (mulhs x, 0) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (mulhs x, 1) -> (sra x, size(x)-1)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->getValue() == 1)
|
2005-09-01 00:19:25 +00:00
|
|
|
return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
|
2005-09-06 04:43:02 +00:00
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitMULHU(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (mulhu x, 0) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (mulhu x, 1) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->getValue() == 1)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, N0.getValueType());
|
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitAND(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2006-02-17 19:54:08 +00:00
|
|
|
SDOperand LL, LR, RL, RR, CC0, CC1;
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N1.getValueType();
|
2005-09-06 04:43:02 +00:00
|
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (and c1, c2) -> c1&c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::AND, VT, N0, N1);
|
2005-09-07 23:25:52 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0C && !N1C)
|
|
|
|
return DAG.getNode(ISD::AND, VT, N1, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (and x, -1) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isAllOnesValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
|
|
|
// if (and x, c) is known to be zero, return 0
|
2006-02-16 21:11:51 +00:00
|
|
|
if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, VT);
|
2006-02-03 06:46:56 +00:00
|
|
|
// reassociate and
|
|
|
|
SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
|
|
|
|
if (RAND.Val != 0)
|
|
|
|
return RAND;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
|
2005-11-02 18:42:59 +00:00
|
|
|
if (N1C && N0.getOpcode() == ISD::OR)
|
2005-09-01 00:19:25 +00:00
|
|
|
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
|
2005-09-02 21:18:40 +00:00
|
|
|
if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 07:17:31 +00:00
|
|
|
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
|
|
|
|
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
|
2006-03-01 21:47:21 +00:00
|
|
|
unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
|
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 07:17:31 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N0.getOperand(0),
|
2006-03-01 21:47:21 +00:00
|
|
|
~N1C->getValue() & InMask)) {
|
|
|
|
SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
|
|
|
|
N0.getOperand(0));
|
|
|
|
|
|
|
|
// Replace uses of the AND with uses of the Zero extend node.
|
|
|
|
CombineTo(N, Zext);
|
|
|
|
|
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 07:17:31 +00:00
|
|
|
// We actually want to replace all uses of the any_extend with the
|
|
|
|
// zero_extend, to avoid duplicating things. This will later cause this
|
|
|
|
// AND to be folded.
|
2006-03-01 21:47:21 +00:00
|
|
|
CombineTo(N0.Val, Zext);
|
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 07:17:31 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
}
|
2005-09-09 19:49:52 +00:00
|
|
|
// fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
|
|
|
|
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
|
|
|
|
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
|
|
|
|
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
|
|
|
|
|
|
|
|
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
|
|
|
|
MVT::isInteger(LL.getValueType())) {
|
|
|
|
// fold (X == 0) & (Y == 0) -> (X|Y == 0)
|
|
|
|
if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
|
|
|
|
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ORNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getSetCC(VT, ORNode, LR, Op1);
|
|
|
|
}
|
|
|
|
// fold (X == -1) & (Y == -1) -> (X&Y == -1)
|
|
|
|
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
|
|
|
|
SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ANDNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getSetCC(VT, ANDNode, LR, Op1);
|
|
|
|
}
|
|
|
|
// fold (X > -1) & (Y > -1) -> (X|Y > -1)
|
|
|
|
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
|
|
|
|
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ORNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getSetCC(VT, ORNode, LR, Op1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// canonicalize equivalent to ll == rl
|
|
|
|
if (LL == RR && LR == RL) {
|
|
|
|
Op1 = ISD::getSetCCSwappedOperands(Op1);
|
|
|
|
std::swap(RL, RR);
|
|
|
|
}
|
|
|
|
if (LL == RL && LR == RR) {
|
|
|
|
bool isInteger = MVT::isInteger(LL.getValueType());
|
|
|
|
ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
|
|
|
|
if (Result != ISD::SETCC_INVALID)
|
|
|
|
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// fold (and (zext x), (zext y)) -> (zext (and x, y))
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N1.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
|
|
|
|
SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ANDNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
|
|
|
|
}
|
2006-01-28 01:06:30 +00:00
|
|
|
// fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
|
2005-09-16 00:54:12 +00:00
|
|
|
if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
|
2006-01-28 01:06:30 +00:00
|
|
|
(N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
|
|
|
|
(N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
|
2005-09-16 00:54:12 +00:00
|
|
|
N0.getOperand(1) == N1.getOperand(1)) {
|
|
|
|
SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ANDNode.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
|
|
|
|
}
|
2006-02-03 22:24:05 +00:00
|
|
|
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
|
|
|
|
// fold (and (sra)) -> (and (srl)) when possible.
|
2006-02-17 21:58:01 +00:00
|
|
|
if (SimplifyDemandedBits(SDOperand(N, 0)))
|
2006-02-03 22:24:05 +00:00
|
|
|
return SDOperand();
|
2005-10-13 03:11:28 +00:00
|
|
|
// fold (zext_inreg (extload x)) -> (zextload x)
|
2005-10-14 01:12:21 +00:00
|
|
|
if (N0.getOpcode() == ISD::EXTLOAD) {
|
2005-10-13 03:11:28 +00:00
|
|
|
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
|
2005-10-13 18:34:58 +00:00
|
|
|
// If we zero all the possible extended bits, then we can turn this into
|
|
|
|
// a zextload if we are running before legalize or the operation is legal.
|
2006-01-30 04:09:27 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
|
2005-10-13 18:16:34 +00:00
|
|
|
(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
|
2005-10-13 03:11:28 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
EVT);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N);
|
2005-10-13 18:16:34 +00:00
|
|
|
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
|
2005-10-13 03:11:28 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
|
2005-10-13 03:11:28 +00:00
|
|
|
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
|
2005-10-13 18:34:58 +00:00
|
|
|
// If we zero all the possible extended bits, then we can turn this into
|
|
|
|
// a zextload if we are running before legalize or the operation is legal.
|
2006-01-30 04:09:27 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
|
2005-10-13 18:34:58 +00:00
|
|
|
(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
|
2005-10-13 03:11:28 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
EVT);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N);
|
2005-10-13 18:16:34 +00:00
|
|
|
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
|
2005-10-13 03:11:28 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
}
|
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
|
|
|
|
Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:49:37 +00:00
|
|
|
// fold (and (load x), 255) -> (zextload x, i8)
|
|
|
|
// fold (and (extload x, i16), 255) -> (zextload x, i8)
|
|
|
|
if (N1C &&
|
|
|
|
(N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
|
|
|
|
N0.getOpcode() == ISD::ZEXTLOAD) &&
|
|
|
|
N0.hasOneUse()) {
|
|
|
|
MVT::ValueType EVT, LoadedVT;
|
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
|
|
|
if (N1C->getValue() == 255)
|
|
|
|
EVT = MVT::i8;
|
|
|
|
else if (N1C->getValue() == 65535)
|
|
|
|
EVT = MVT::i16;
|
|
|
|
else if (N1C->getValue() == ~0U)
|
|
|
|
EVT = MVT::i32;
|
|
|
|
else
|
|
|
|
EVT = MVT::Other;
|
Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:49:37 +00:00
|
|
|
|
|
|
|
LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
|
|
|
|
cast<VTSDNode>(N0.getOperand(3))->getVT();
|
|
|
|
if (EVT != MVT::Other && LoadedVT > EVT) {
|
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
|
|
|
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
|
|
|
|
// For big endian targets, we need to add an offset to the pointer to load
|
|
|
|
// the correct bytes. For little endian systems, we merely need to read
|
|
|
|
// fewer bytes from the same pointer.
|
Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:49:37 +00:00
|
|
|
unsigned PtrOff =
|
|
|
|
(MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
|
|
|
|
SDOperand NewPtr = N0.getOperand(1);
|
|
|
|
if (!TLI.isLittleEndian())
|
|
|
|
NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
|
|
|
|
DAG.getConstant(PtrOff, PtrType));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(NewPtr.Val);
|
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
|
|
|
SDOperand Load =
|
|
|
|
DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
|
|
|
|
N0.getOperand(2), EVT);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N);
|
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-28 06:35:35 +00:00
|
|
|
CombineTo(N0.Val, Load, Load.getValue(1));
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitOR(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-09 19:49:52 +00:00
|
|
|
SDOperand LL, LR, RL, RR, CC0, CC1;
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-06 04:43:02 +00:00
|
|
|
MVT::ValueType VT = N1.getValueType();
|
|
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (or c1, c2) -> c1|c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::OR, VT, N0, N1);
|
2005-09-07 23:25:52 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0C && !N1C)
|
|
|
|
return DAG.getNode(ISD::OR, VT, N1, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (or x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (or x, -1) -> -1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isAllOnesValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
|
|
|
// fold (or x, c) -> c iff (x & ~c) == 0
|
2006-01-30 04:09:27 +00:00
|
|
|
if (N1C &&
|
|
|
|
TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
|
2005-09-06 04:43:02 +00:00
|
|
|
return N1;
|
2006-02-03 06:46:56 +00:00
|
|
|
// reassociate or
|
|
|
|
SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
|
|
|
|
if (ROR.Val != 0)
|
|
|
|
return ROR;
|
|
|
|
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
|
2005-10-27 05:06:38 +00:00
|
|
|
isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
|
|
|
|
return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
|
|
|
|
N1),
|
|
|
|
DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
|
2005-09-08 20:18:10 +00:00
|
|
|
}
|
2005-09-09 19:49:52 +00:00
|
|
|
// fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
|
|
|
|
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
|
|
|
|
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
|
|
|
|
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
|
|
|
|
|
|
|
|
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
|
|
|
|
MVT::isInteger(LL.getValueType())) {
|
|
|
|
// fold (X != 0) | (Y != 0) -> (X|Y != 0)
|
|
|
|
// fold (X < 0) | (Y < 0) -> (X|Y < 0)
|
|
|
|
if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
|
|
|
|
(Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
|
|
|
|
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ORNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getSetCC(VT, ORNode, LR, Op1);
|
|
|
|
}
|
|
|
|
// fold (X != -1) | (Y != -1) -> (X&Y != -1)
|
|
|
|
// fold (X > -1) | (Y > -1) -> (X&Y > -1)
|
|
|
|
if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
|
|
|
|
(Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
|
|
|
|
SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ANDNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getSetCC(VT, ANDNode, LR, Op1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// canonicalize equivalent to ll == rl
|
|
|
|
if (LL == RR && LR == RL) {
|
|
|
|
Op1 = ISD::getSetCCSwappedOperands(Op1);
|
|
|
|
std::swap(RL, RR);
|
|
|
|
}
|
|
|
|
if (LL == RL && LR == RR) {
|
|
|
|
bool isInteger = MVT::isInteger(LL.getValueType());
|
|
|
|
ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
|
|
|
|
if (Result != ISD::SETCC_INVALID)
|
|
|
|
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// fold (or (zext x), (zext y)) -> (zext (or x, y))
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N1.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
|
|
|
|
SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ORNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
|
|
|
|
}
|
2006-02-01 07:19:44 +00:00
|
|
|
// fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
|
|
|
|
if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
|
|
|
|
(N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
|
|
|
|
(N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
|
|
|
|
N0.getOperand(1) == N1.getOperand(1)) {
|
|
|
|
SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ORNode.Val);
|
2006-02-01 07:19:44 +00:00
|
|
|
return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
|
|
|
|
}
|
2006-01-11 21:21:00 +00:00
|
|
|
// canonicalize shl to left side in a shl/srl pair, to match rotate
|
|
|
|
if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
|
|
|
|
std::swap(N0, N1);
|
|
|
|
// check for rotl, rotr
|
|
|
|
if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
|
|
|
|
N0.getOperand(0) == N1.getOperand(0) &&
|
2006-01-12 18:57:33 +00:00
|
|
|
TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
|
2006-01-11 21:21:00 +00:00
|
|
|
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
|
|
|
|
if (N0.getOperand(1).getOpcode() == ISD::Constant &&
|
|
|
|
N1.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
|
|
|
uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
|
|
|
|
if ((c1val + c2val) == OpSizeInBits)
|
|
|
|
return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
|
|
|
|
}
|
|
|
|
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
|
|
|
|
if (N1.getOperand(1).getOpcode() == ISD::SUB &&
|
|
|
|
N0.getOperand(1) == N1.getOperand(1).getOperand(1))
|
|
|
|
if (ConstantSDNode *SUBC =
|
|
|
|
dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
|
|
|
|
if (SUBC->getValue() == OpSizeInBits)
|
|
|
|
return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
|
|
|
|
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
|
|
|
|
if (N0.getOperand(1).getOpcode() == ISD::SUB &&
|
|
|
|
N1.getOperand(1) == N0.getOperand(1).getOperand(1))
|
|
|
|
if (ConstantSDNode *SUBC =
|
|
|
|
dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
|
|
|
|
if (SUBC->getValue() == OpSizeInBits) {
|
2006-01-12 18:57:33 +00:00
|
|
|
if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
|
2006-01-11 21:21:00 +00:00
|
|
|
return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
|
|
|
|
N1.getOperand(1));
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1));
|
|
|
|
}
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitXOR(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
SDOperand LHS, RHS, CC;
|
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
|
|
|
|
// fold (xor c1, c2) -> c1^c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::XOR, VT, N0, N1);
|
2005-09-07 23:25:52 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0C && !N1C)
|
|
|
|
return DAG.getNode(ISD::XOR, VT, N1, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (xor x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2006-02-03 06:46:56 +00:00
|
|
|
// reassociate xor
|
|
|
|
SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
|
|
|
|
if (RXOR.Val != 0)
|
|
|
|
return RXOR;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold !(x cc y) -> (x !cc y)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
|
|
|
|
bool isInt = MVT::isInteger(LHS.getValueType());
|
|
|
|
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
|
|
|
|
isInt);
|
|
|
|
if (N0.getOpcode() == ISD::SETCC)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getSetCC(VT, LHS, RHS, NotCC);
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0.getOpcode() == ISD::SELECT_CC)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
|
2005-09-02 21:18:40 +00:00
|
|
|
assert(0 && "Unhandled SetCC Equivalent!");
|
|
|
|
abort();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-07 23:25:52 +00:00
|
|
|
// fold !(x or y) -> (!x and !y) iff x or y are setcc
|
|
|
|
if (N1C && N1C->getValue() == 1 &&
|
|
|
|
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
|
2005-09-07 23:25:52 +00:00
|
|
|
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
|
|
|
|
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
|
2005-09-01 00:19:25 +00:00
|
|
|
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
|
|
|
|
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
|
2005-09-07 23:25:52 +00:00
|
|
|
return DAG.getNode(NewOpcode, VT, LHS, RHS);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
}
|
2005-09-07 23:25:52 +00:00
|
|
|
// fold !(x or y) -> (!x and !y) iff x or y are constants
|
|
|
|
if (N1C && N1C->isAllOnesValue() &&
|
|
|
|
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
|
2005-09-07 23:25:52 +00:00
|
|
|
if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
|
|
|
|
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
|
2005-09-01 00:19:25 +00:00
|
|
|
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
|
|
|
|
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
|
2005-09-07 23:25:52 +00:00
|
|
|
return DAG.getNode(NewOpcode, VT, LHS, RHS);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
}
|
2005-09-08 20:18:10 +00:00
|
|
|
// fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::XOR) {
|
|
|
|
ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
|
|
|
|
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
|
|
|
|
if (N00C)
|
|
|
|
return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
|
|
|
|
DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
|
|
|
|
if (N01C)
|
|
|
|
return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
|
|
|
|
}
|
|
|
|
// fold (xor x, x) -> 0
|
|
|
|
if (N0 == N1)
|
|
|
|
return DAG.getConstant(0, VT);
|
2005-09-09 19:49:52 +00:00
|
|
|
// fold (xor (zext x), (zext y)) -> (zext (xor x, y))
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N1.getOpcode() == ISD::ZERO_EXTEND &&
|
|
|
|
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
|
|
|
|
SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(XORNode.Val);
|
2005-09-09 19:49:52 +00:00
|
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
|
|
|
|
}
|
2006-02-01 07:19:44 +00:00
|
|
|
// fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
|
|
|
|
if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
|
|
|
|
(N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
|
|
|
|
(N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
|
|
|
|
N0.getOperand(1) == N1.getOperand(1)) {
|
|
|
|
SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
|
|
|
|
N0.getOperand(0), N1.getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(XORNode.Val);
|
2006-02-01 07:19:44 +00:00
|
|
|
return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSHL(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
|
|
|
|
|
|
|
// fold (shl c1, c2) -> c1<<c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SHL, VT, N0, N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (shl 0, x) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N0C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (shl x, c >= size(x)) -> undef
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->getValue() >= OpSizeInBits)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::UNDEF, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (shl x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// if (shl x, c) is known to be zero, return 0
|
2006-02-17 19:54:08 +00:00
|
|
|
if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, VT);
|
2006-02-17 21:58:01 +00:00
|
|
|
if (SimplifyDemandedBits(SDOperand(N, 0)))
|
2006-02-03 22:24:05 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N0.getOpcode() == ISD::SHL &&
|
2005-09-01 00:19:25 +00:00
|
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
2005-09-02 21:18:40 +00:00
|
|
|
uint64_t c2 = N1C->getValue();
|
2005-09-01 00:19:25 +00:00
|
|
|
if (c1 + c2 > OpSizeInBits)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
|
2005-09-06 04:43:02 +00:00
|
|
|
DAG.getConstant(c1 + c2, N1.getValueType()));
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
// fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
|
|
|
|
// (srl (and x, -1 << c1), c1-c2)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N0.getOpcode() == ISD::SRL &&
|
2005-09-01 00:19:25 +00:00
|
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
2005-09-02 21:18:40 +00:00
|
|
|
uint64_t c2 = N1C->getValue();
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(~0ULL << c1, VT));
|
|
|
|
if (c2 > c1)
|
|
|
|
return DAG.getNode(ISD::SHL, VT, Mask,
|
2005-09-06 04:43:02 +00:00
|
|
|
DAG.getConstant(c2-c1, N1.getValueType()));
|
2005-09-01 00:19:25 +00:00
|
|
|
else
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, Mask,
|
|
|
|
DAG.getConstant(c1-c2, N1.getValueType()));
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
// fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
|
2005-09-01 23:24:04 +00:00
|
|
|
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
2005-09-06 04:43:02 +00:00
|
|
|
DAG.getConstant(~0ULL << N1C->getValue(), VT));
|
2006-03-05 19:53:55 +00:00
|
|
|
// fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
return DAG.getNode(ISD::ADD, VT,
|
|
|
|
DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
|
|
|
|
DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSRA(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
|
|
|
|
// fold (sra c1, c2) -> c1>>c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SRA, VT, N0, N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sra 0, x) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N0C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sra -1, x) -> -1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N0C->isAllOnesValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sra x, c >= size(x)) -> undef
|
2006-02-17 19:54:08 +00:00
|
|
|
if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::UNDEF, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sra x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2006-02-17 19:54:08 +00:00
|
|
|
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
|
|
|
|
// sext_inreg.
|
|
|
|
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
|
|
|
|
unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
|
|
|
|
MVT::ValueType EVT;
|
|
|
|
switch (LowBits) {
|
|
|
|
default: EVT = MVT::Other; break;
|
|
|
|
case 1: EVT = MVT::i1; break;
|
|
|
|
case 8: EVT = MVT::i8; break;
|
|
|
|
case 16: EVT = MVT::i16; break;
|
|
|
|
case 32: EVT = MVT::i32; break;
|
|
|
|
}
|
|
|
|
if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
|
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
|
|
|
|
DAG.getValueType(EVT));
|
|
|
|
}
|
2006-02-28 06:23:04 +00:00
|
|
|
|
|
|
|
// fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
|
|
|
|
if (N1C && N0.getOpcode() == ISD::SRA) {
|
|
|
|
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
unsigned Sum = N1C->getValue() + C1->getValue();
|
|
|
|
if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
|
|
|
|
return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(Sum, N1C->getValueType(0)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// If the sign bit is known to be zero, switch this to a SRL.
|
2006-02-17 19:54:08 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, N0, N1);
|
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSRL(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
|
|
|
|
|
|
|
// fold (srl c1, c2) -> c1 >>u c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N1C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, N0, N1);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (srl 0, x) -> 0
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C && N0C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (srl x, c >= size(x)) -> undef
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->getValue() >= OpSizeInBits)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::UNDEF, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (srl x, 0) -> x
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N1C->isNullValue())
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// if (srl x, c) is known to be zero, return 0
|
2006-01-30 04:09:27 +00:00
|
|
|
if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N1C && N0.getOpcode() == ISD::SRL &&
|
2005-09-01 00:19:25 +00:00
|
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
2005-09-02 21:18:40 +00:00
|
|
|
uint64_t c2 = N1C->getValue();
|
2005-09-01 00:19:25 +00:00
|
|
|
if (c1 + c2 > OpSizeInBits)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getConstant(0, VT);
|
2005-09-01 00:19:25 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
|
2005-09-06 04:43:02 +00:00
|
|
|
DAG.getConstant(c1 + c2, N1.getValueType()));
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (ctlz c1) -> c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::CTLZ, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (cttz c1) -> c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::CTTZ, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (ctpop c1) -> c2
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::CTPOP, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
SDOperand DAGCombiner::visitSELECT(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
|
|
SDOperand N2 = N->getOperand(2);
|
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-19 22:34:01 +00:00
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
// fold select C, X, X -> X
|
|
|
|
if (N1 == N2)
|
|
|
|
return N1;
|
|
|
|
// fold select true, X, Y -> X
|
|
|
|
if (N0C && !N0C->isNullValue())
|
|
|
|
return N1;
|
|
|
|
// fold select false, X, Y -> Y
|
|
|
|
if (N0C && N0C->isNullValue())
|
|
|
|
return N2;
|
|
|
|
// fold select C, 1, X -> C | X
|
2005-09-19 22:34:01 +00:00
|
|
|
if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getNode(ISD::OR, VT, N0, N2);
|
|
|
|
// fold select C, 0, X -> ~C & X
|
|
|
|
// FIXME: this should check for C type == X type, not i1?
|
|
|
|
if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
|
|
|
|
SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(XORNode.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getNode(ISD::AND, VT, XORNode, N2);
|
|
|
|
}
|
|
|
|
// fold select C, X, 1 -> ~C | X
|
2005-09-19 22:34:01 +00:00
|
|
|
if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
|
2005-09-16 00:54:12 +00:00
|
|
|
SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(XORNode.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getNode(ISD::OR, VT, XORNode, N1);
|
|
|
|
}
|
|
|
|
// fold select C, X, 0 -> C & X
|
|
|
|
// FIXME: this should check for C type == X type, not i1?
|
|
|
|
if (MVT::i1 == VT && N2C && N2C->isNullValue())
|
|
|
|
return DAG.getNode(ISD::AND, VT, N0, N1);
|
|
|
|
// fold X ? X : Y --> X ? 1 : Y --> X | Y
|
|
|
|
if (MVT::i1 == VT && N0 == N1)
|
|
|
|
return DAG.getNode(ISD::OR, VT, N0, N2);
|
|
|
|
// fold X ? Y : X --> X ? Y : 0 --> X & Y
|
|
|
|
if (MVT::i1 == VT && N0 == N2)
|
|
|
|
return DAG.getNode(ISD::AND, VT, N0, N1);
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
// If we can fold this based on the true/false value, do so.
|
|
|
|
if (SimplifySelectOps(N, N1, N2))
|
|
|
|
return SDOperand();
|
2005-09-19 22:34:01 +00:00
|
|
|
// fold selects based on a setcc into other things, such as min/max/abs
|
|
|
|
if (N0.getOpcode() == ISD::SETCC)
|
2006-02-01 07:19:44 +00:00
|
|
|
// FIXME:
|
|
|
|
// Check against MVT::Other for SELECT_CC, which is a workaround for targets
|
|
|
|
// having to say they don't support SELECT_CC on every type the DAG knows
|
|
|
|
// about, since there is no way to mark an opcode illegal at all value types
|
|
|
|
if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
|
|
|
|
return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
|
|
|
|
N1, N2, N0.getOperand(2));
|
|
|
|
else
|
|
|
|
return SimplifySelect(N0, N1, N2);
|
2005-09-16 00:54:12 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
|
|
SDOperand N2 = N->getOperand(2);
|
|
|
|
SDOperand N3 = N->getOperand(3);
|
|
|
|
SDOperand N4 = N->getOperand(4);
|
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
|
|
|
|
|
|
|
|
// Determine if the condition we're dealing with is constant
|
2005-10-05 21:43:42 +00:00
|
|
|
SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
|
2005-10-05 04:45:43 +00:00
|
|
|
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
// fold select_cc lhs, rhs, x, x, cc -> x
|
|
|
|
if (N2 == N3)
|
|
|
|
return N2;
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
|
|
|
|
// If we can fold this based on the true/false value, do so.
|
|
|
|
if (SimplifySelectOps(N, N2, N3))
|
|
|
|
return SDOperand();
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
// fold select_cc into other things, such as min/max/abs
|
|
|
|
return SimplifySelectCC(N0, N1, N2, N3, CC);
|
2005-09-16 00:54:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitSETCC(SDNode *N) {
|
|
|
|
return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
|
|
|
|
cast<CondCodeSDNode>(N->getOperand(2))->get());
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
// fold (sext c1) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sext (sext x)) -> (sext x)
|
|
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
|
2005-12-07 07:11:03 +00:00
|
|
|
// fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
|
2005-12-07 18:02:05 +00:00
|
|
|
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
|
|
|
|
(!AfterLegalize ||
|
|
|
|
TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
|
2005-12-07 07:11:03 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
|
|
|
|
DAG.getValueType(N0.getValueType()));
|
2005-12-14 02:19:23 +00:00
|
|
|
// fold (sext (load x)) -> (sext (truncate (sextload x)))
|
2005-12-15 19:02:38 +00:00
|
|
|
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
|
|
|
|
(!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
N0.getValueType());
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-10-13 21:52:31 +00:00
|
|
|
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
|
|
|
|
ExtLoad.getValue(1));
|
2005-10-12 23:18:53 +00:00
|
|
|
return SDOperand();
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
}
|
2005-12-14 19:05:06 +00:00
|
|
|
|
|
|
|
// fold (sext (sextload x)) -> (sext (truncate (sextload x)))
|
|
|
|
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
|
|
|
|
if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
|
|
|
|
N0.hasOneUse()) {
|
|
|
|
SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
N0.getOperand(3));
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-12-14 19:05:06 +00:00
|
|
|
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
|
|
|
|
ExtLoad.getValue(1));
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
// fold (zext c1) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (zext (zext x)) -> (zext x)
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
|
2005-12-14 02:19:23 +00:00
|
|
|
// fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
|
|
|
|
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
|
2005-12-14 19:05:06 +00:00
|
|
|
(!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
|
2005-12-14 07:58:38 +00:00
|
|
|
return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
|
2005-12-14 02:19:23 +00:00
|
|
|
// fold (zext (load x)) -> (zext (truncate (zextload x)))
|
2005-12-15 19:02:38 +00:00
|
|
|
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
|
|
|
|
(!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
|
2005-12-14 02:19:23 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
N0.getValueType());
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-12-14 02:19:23 +00:00
|
|
|
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
|
|
|
|
ExtLoad.getValue(1));
|
|
|
|
return SDOperand();
|
|
|
|
}
|
2005-12-14 19:05:06 +00:00
|
|
|
|
|
|
|
// fold (zext (zextload x)) -> (zext (truncate (zextload x)))
|
|
|
|
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
|
|
|
|
if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
|
|
|
|
N0.hasOneUse()) {
|
|
|
|
SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
N0.getOperand(3));
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-12-14 19:05:06 +00:00
|
|
|
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
|
|
|
|
ExtLoad.getValue(1));
|
|
|
|
return SDOperand();
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
|
2005-10-10 21:26:48 +00:00
|
|
|
unsigned EVTBits = MVT::getSizeInBits(EVT);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (sext_in_reg c1) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C) {
|
|
|
|
SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-02 21:18:40 +00:00
|
|
|
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
|
2005-09-01 00:19:25 +00:00
|
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
2005-10-14 01:29:07 +00:00
|
|
|
cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-02 21:18:40 +00:00
|
|
|
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
|
|
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
|
|
|
EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
|
2005-09-02 21:18:40 +00:00
|
|
|
}
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
|
|
|
|
if (N0.getOpcode() == ISD::AssertSext &&
|
|
|
|
cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
// fold (sext_in_reg (sextload x)) -> (sextload x)
|
|
|
|
if (N0.getOpcode() == ISD::SEXTLOAD &&
|
|
|
|
cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-01 23:24:04 +00:00
|
|
|
// fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
|
2005-09-01 00:19:25 +00:00
|
|
|
if (N0.getOpcode() == ISD::SETCC &&
|
|
|
|
TLI.getSetCCResultContents() ==
|
|
|
|
TargetLowering::ZeroOrNegativeOneSetCCResult)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-10-10 21:26:48 +00:00
|
|
|
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
|
2006-01-30 04:09:27 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
|
2006-02-03 22:24:05 +00:00
|
|
|
return DAG.getZeroExtendInReg(N0, EVT);
|
2005-10-10 21:26:48 +00:00
|
|
|
// fold (sext_in_reg (srl x)) -> sra x
|
|
|
|
if (N0.getOpcode() == ISD::SRL &&
|
|
|
|
N0.getOperand(1).getOpcode() == ISD::Constant &&
|
|
|
|
cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
|
|
|
|
return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
|
|
|
|
N0.getOperand(1));
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-10-13 03:11:28 +00:00
|
|
|
// fold (sext_inreg (extload x)) -> (sextload x)
|
|
|
|
if (N0.getOpcode() == ISD::EXTLOAD &&
|
|
|
|
EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
|
2005-10-13 18:34:58 +00:00
|
|
|
(!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
|
2005-10-13 03:11:28 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
EVT);
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-10-13 18:34:58 +00:00
|
|
|
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
|
2005-10-13 03:11:28 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
|
2005-10-13 03:11:28 +00:00
|
|
|
EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
|
2005-10-13 18:34:58 +00:00
|
|
|
(!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
|
2005-10-13 03:11:28 +00:00
|
|
|
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
|
|
|
|
N0.getOperand(1), N0.getOperand(2),
|
|
|
|
EVT);
|
2005-12-14 19:25:30 +00:00
|
|
|
CombineTo(N, ExtLoad);
|
2005-10-13 18:34:58 +00:00
|
|
|
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
|
2005-10-13 03:11:28 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
// noop truncate
|
|
|
|
if (N0.getValueType() == N->getValueType(0))
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0;
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (truncate c1) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::TRUNCATE, VT, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (truncate (truncate x)) -> (truncate x)
|
|
|
|
if (N0.getOpcode() == ISD::TRUNCATE)
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
|
|
|
|
if (N0.getValueType() < VT)
|
|
|
|
// if the source is smaller than the dest, we still need an extend
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
|
2005-09-01 00:19:25 +00:00
|
|
|
else if (N0.getValueType() > VT)
|
|
|
|
// if the source is larger than the dest, than we just need the truncate
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
|
2005-09-01 00:19:25 +00:00
|
|
|
else
|
|
|
|
// if the source and dest are the same type, we can drop both the extend
|
|
|
|
// and the truncate
|
2005-09-06 04:43:02 +00:00
|
|
|
return N0.getOperand(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
// fold (truncate (load x)) -> (smaller load x)
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
|
|
|
|
"Cannot truncate to larger type!");
|
|
|
|
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
|
2005-10-12 23:18:53 +00:00
|
|
|
// For big endian targets, we need to add an offset to the pointer to load
|
|
|
|
// the correct bytes. For little endian systems, we merely need to read
|
|
|
|
// fewer bytes from the same pointer.
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
uint64_t PtrOff =
|
|
|
|
(MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
|
2005-10-12 23:18:53 +00:00
|
|
|
SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
|
|
|
|
DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
|
|
|
|
DAG.getConstant(PtrOff, PtrType));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(NewPtr.Val);
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N);
|
2005-10-13 22:10:05 +00:00
|
|
|
CombineTo(N0.Val, Load, Load.getValue(1));
|
2005-10-12 23:18:53 +00:00
|
|
|
return SDOperand();
|
More cool stuff for the dag combiner. We can now finally handle things
like turning:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
into
_foo:
fctiwz f0,f1
stfd f0,-8(r1)
lhz r3,-2(r1)
blr
Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-12 20:40:40 +00:00
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
constant fold bits_convert in getNode and in the dag combiner for fp<->int
conversions. This allows V8 to compiles this:
void %test() {
call float %test2( float 1.000000e+00, float 2.000000e+00, double 3.000000e+00, double* null )
ret void
}
into:
test:
save -96, %o6, %o6
sethi 0, %o3
sethi 1049088, %o2
sethi 1048576, %o1
sethi 1040384, %o0
or %g0, %o3, %o4
call test2
nop
restore %g0, %g0, %g0
retl
nop
instead of:
test:
save -112, %o6, %o6
sethi 0, %o4
sethi 1049088, %l0
st %o4, [%i6+-12]
st %l0, [%i6+-16]
ld [%i6+-12], %o3
ld [%i6+-16], %o2
sethi 1048576, %o1
sethi 1040384, %o0
call test2
nop
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24980 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:30:37 +00:00
|
|
|
SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
// If the input is a constant, let getNode() fold it.
|
|
|
|
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
|
|
|
|
SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
|
|
|
|
if (Res.Val != N) return Res;
|
|
|
|
}
|
|
|
|
|
Fold bitconv(bitconv(x)) -> x. We now compile this:
void foo(double);
void bar(double X) { foo(X); }
to this:
bar:
save -96, %o6, %o6
or %g0, %i0, %o0
or %g0, %i1, %o1
call foo
nop
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -112, %o6, %o6
st %i1, [%i6+-4]
st %i0, [%i6+-8]
ldd [%i6+-8], %f0
std %f0, [%i6+-16]
ld [%i6+-12], %o1
ld [%i6+-16], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
on V8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24981 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:37:50 +00:00
|
|
|
if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
|
|
|
|
|
fold (conv (load x)) -> (load (conv*)x).
This allows us to compile this:
void foo(double);
void bar(double *X) { foo(*X); }
To this:
bar:
save -96, %o6, %o6
ld [%i0+4], %o1
ld [%i0], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -104, %o6, %o6
ldd [%i0], %f0
std %f0, [%i6+-8]
ld [%i6+-4], %o1
ld [%i6+-8], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
on SparcV8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24982 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:44:41 +00:00
|
|
|
// fold (conv (load x)) -> (load (conv*)x)
|
2006-01-15 18:58:59 +00:00
|
|
|
// FIXME: These xforms need to know that the resultant load doesn't need a
|
|
|
|
// higher alignment than the original!
|
|
|
|
if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
|
fold (conv (load x)) -> (load (conv*)x).
This allows us to compile this:
void foo(double);
void bar(double *X) { foo(*X); }
To this:
bar:
save -96, %o6, %o6
ld [%i0+4], %o1
ld [%i0], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -104, %o6, %o6
ldd [%i0], %f0
std %f0, [%i6+-8]
ld [%i6+-4], %o1
ld [%i6+-8], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
on SparcV8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24982 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:44:41 +00:00
|
|
|
SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
|
|
|
|
N0.getOperand(2));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N);
|
fold (conv (load x)) -> (load (conv*)x).
This allows us to compile this:
void foo(double);
void bar(double *X) { foo(*X); }
To this:
bar:
save -96, %o6, %o6
ld [%i0+4], %o1
ld [%i0], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -104, %o6, %o6
ldd [%i0], %f0
std %f0, [%i6+-8]
ld [%i6+-4], %o1
ld [%i6+-8], %o0
call foo
nop
restore %g0, %g0, %g0
retl
nop
on SparcV8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24982 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:44:41 +00:00
|
|
|
CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
|
|
|
|
Load.getValue(1));
|
|
|
|
return Load;
|
|
|
|
}
|
|
|
|
|
constant fold bits_convert in getNode and in the dag combiner for fp<->int
conversions. This allows V8 to compiles this:
void %test() {
call float %test2( float 1.000000e+00, float 2.000000e+00, double 3.000000e+00, double* null )
ret void
}
into:
test:
save -96, %o6, %o6
sethi 0, %o3
sethi 1049088, %o2
sethi 1048576, %o1
sethi 1040384, %o0
or %g0, %o3, %o4
call test2
nop
restore %g0, %g0, %g0
retl
nop
instead of:
test:
save -112, %o6, %o6
sethi 0, %o4
sethi 1049088, %l0
st %o4, [%i6+-12]
st %l0, [%i6+-16]
ld [%i6+-12], %o3
ld [%i6+-16], %o2
sethi 1048576, %o1
sethi 1040384, %o0
call test2
nop
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24980 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:30:37 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-09-28 22:28:18 +00:00
|
|
|
SDOperand DAGCombiner::visitFADD(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-10-18 00:28:13 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-10-18 00:28:13 +00:00
|
|
|
|
|
|
|
// fold (fadd c1, c2) -> c1+c2
|
|
|
|
if (N0CFP && N1CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FADD, VT, N0, N1);
|
2005-10-18 00:28:13 +00:00
|
|
|
// canonicalize constant to RHS
|
|
|
|
if (N0CFP && !N1CFP)
|
|
|
|
return DAG.getNode(ISD::FADD, VT, N1, N0);
|
2005-09-28 22:28:18 +00:00
|
|
|
// fold (A + (-B)) -> A-B
|
|
|
|
if (N1.getOpcode() == ISD::FNEG)
|
|
|
|
return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
|
|
|
|
// fold ((-A) + B) -> B-A
|
|
|
|
if (N0.getOpcode() == ISD::FNEG)
|
|
|
|
return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitFSUB(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-10-18 00:28:13 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-10-18 00:28:13 +00:00
|
|
|
|
|
|
|
// fold (fsub c1, c2) -> c1-c2
|
|
|
|
if (N0CFP && N1CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FSUB, VT, N0, N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
// fold (A-(-B)) -> A+B
|
|
|
|
if (N1.getOpcode() == ISD::FNEG)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
|
2005-09-28 22:28:18 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitFMUL(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2005-10-17 20:40:11 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
2005-10-17 20:40:11 +00:00
|
|
|
// fold (fmul c1, c2) -> c1*c2
|
|
|
|
if (N0CFP && N1CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FMUL, VT, N0, N1);
|
2005-10-17 20:40:11 +00:00
|
|
|
// canonicalize constant to RHS
|
2005-10-18 00:28:13 +00:00
|
|
|
if (N0CFP && !N1CFP)
|
|
|
|
return DAG.getNode(ISD::FMUL, VT, N1, N0);
|
2005-10-17 20:40:11 +00:00
|
|
|
// fold (fmul X, 2.0) -> (fadd X, X)
|
|
|
|
if (N1CFP && N1CFP->isExactlyValue(+2.0))
|
|
|
|
return DAG.getNode(ISD::FADD, VT, N0, N0);
|
2005-09-28 22:28:18 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitFDIV(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2006-01-18 22:35:16 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
2006-01-18 22:35:16 +00:00
|
|
|
// fold (fdiv c1, c2) -> c1/c2
|
|
|
|
if (N0CFP && N1CFP)
|
|
|
|
return DAG.getNode(ISD::FDIV, VT, N0, N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitFREM(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
2006-01-18 22:35:16 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
2006-01-18 22:35:16 +00:00
|
|
|
// fold (frem c1, c2) -> fmod(c1,c2)
|
|
|
|
if (N0CFP && N1CFP)
|
|
|
|
return DAG.getNode(ISD::FREM, VT, N0, N1);
|
2005-09-28 22:28:18 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-03-05 05:30:57 +00:00
|
|
|
SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
|
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
if (N0CFP && N1CFP) // Constant fold
|
|
|
|
return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
|
|
|
|
|
|
|
|
if (N1CFP) {
|
|
|
|
// copysign(x, c1) -> fabs(x) iff ispos(c1)
|
|
|
|
// copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
int64_t i;
|
|
|
|
} u;
|
|
|
|
u.d = N1CFP->getValue();
|
|
|
|
if (u.i >= 0)
|
|
|
|
return DAG.getNode(ISD::FABS, VT, N0);
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
|
|
|
|
}
|
|
|
|
|
|
|
|
// copysign(fabs(x), y) -> copysign(x, y)
|
|
|
|
// copysign(fneg(x), y) -> copysign(x, y)
|
|
|
|
// copysign(copysign(x,z), y) -> copysign(x, y)
|
|
|
|
if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
|
|
|
|
N0.getOpcode() == ISD::FCOPYSIGN)
|
|
|
|
return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
|
|
|
|
|
|
|
|
// copysign(x, abs(y)) -> abs(x)
|
|
|
|
if (N1.getOpcode() == ISD::FABS)
|
|
|
|
return DAG.getNode(ISD::FABS, VT, N0);
|
|
|
|
|
|
|
|
// copysign(x, copysign(y,z)) -> copysign(x, z)
|
|
|
|
if (N1.getOpcode() == ISD::FCOPYSIGN)
|
|
|
|
return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
|
|
|
|
|
|
|
|
// copysign(x, fp_extend(y)) -> copysign(x, y)
|
|
|
|
// copysign(x, fp_round(y)) -> copysign(x, y)
|
|
|
|
if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
|
|
|
|
return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-09-28 22:28:18 +00:00
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (sint_to_fp c1) -> c1fp
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
|
2006-01-18 22:35:16 +00:00
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (uint_to_fp c1) -> c1fp
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0C)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (fp_to_sint c1fp) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (fp_to_uint c1fp) -> c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (fp_round c1fp) -> c1fp
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FP_ROUND, VT, N0);
|
2006-03-13 06:26:26 +00:00
|
|
|
|
|
|
|
// fold (fp_round (fp_extend x)) -> x
|
|
|
|
if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
|
|
|
|
return N0.getOperand(0);
|
|
|
|
|
|
|
|
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
|
|
|
|
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
|
|
|
|
SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
|
|
|
|
AddToWorkList(Tmp.Val);
|
|
|
|
return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
|
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
|
2005-09-01 00:19:25 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
|
2005-09-02 21:18:40 +00:00
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (fp_round_inreg c1fp) -> c1fp
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP) {
|
|
|
|
SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
|
2005-09-06 04:43:02 +00:00
|
|
|
return DAG.getNode(ISD::FP_EXTEND, VT, Round);
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
|
|
|
|
// fold (fp_extend c1fp) -> c1fp
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FP_EXTEND, VT, N0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFNEG(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
|
|
|
// fold (fneg c1) -> -c1
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FNEG, VT, N0);
|
|
|
|
// fold (fneg (sub x, y)) -> (sub y, x)
|
2006-03-05 05:30:57 +00:00
|
|
|
if (N0.getOpcode() == ISD::SUB)
|
|
|
|
return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
|
2006-01-18 22:35:16 +00:00
|
|
|
// fold (fneg (fneg x)) -> x
|
2006-03-05 05:30:57 +00:00
|
|
|
if (N0.getOpcode() == ISD::FNEG)
|
|
|
|
return N0.getOperand(0);
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
SDOperand DAGCombiner::visitFABS(SDNode *N) {
|
2006-01-18 22:35:16 +00:00
|
|
|
SDOperand N0 = N->getOperand(0);
|
|
|
|
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (fabs c1) -> fabs(c1)
|
2005-09-02 21:18:40 +00:00
|
|
|
if (N0CFP)
|
2006-01-18 22:35:16 +00:00
|
|
|
return DAG.getNode(ISD::FABS, VT, N0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (fabs (fabs x)) -> (fabs x)
|
2006-03-05 05:30:57 +00:00
|
|
|
if (N0.getOpcode() == ISD::FABS)
|
2005-09-06 04:43:02 +00:00
|
|
|
return N->getOperand(0);
|
2005-09-01 00:19:25 +00:00
|
|
|
// fold (fabs (fneg x)) -> (fabs x)
|
2006-03-05 05:30:57 +00:00
|
|
|
// fold (fabs (fcopysign x, y)) -> (fabs x)
|
|
|
|
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
|
|
|
|
return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
|
|
|
|
|
2005-09-06 04:43:02 +00:00
|
|
|
return SDOperand();
|
2005-09-01 00:19:25 +00:00
|
|
|
}
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
|
|
|
|
SDOperand Chain = N->getOperand(0);
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
|
|
SDOperand N2 = N->getOperand(2);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
|
|
|
|
// never taken branch, fold to chain
|
|
|
|
if (N1C && N1C->isNullValue())
|
|
|
|
return Chain;
|
|
|
|
// unconditional branch
|
2005-10-05 21:43:42 +00:00
|
|
|
if (N1C && N1C->getValue() == 1)
|
2005-09-19 22:34:01 +00:00
|
|
|
return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
|
2006-02-01 07:19:44 +00:00
|
|
|
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
|
|
|
|
// on the target.
|
|
|
|
if (N1.getOpcode() == ISD::SETCC &&
|
|
|
|
TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
|
|
|
|
return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
|
|
|
|
N1.getOperand(0), N1.getOperand(1), N2);
|
|
|
|
}
|
2005-09-19 22:34:01 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-10-05 06:47:48 +00:00
|
|
|
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
|
|
|
|
//
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
|
2005-10-05 06:47:48 +00:00
|
|
|
CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
|
|
|
|
SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
|
|
|
|
|
|
|
|
// Use SimplifySetCC to simplify SETCC's.
|
2005-10-05 21:43:42 +00:00
|
|
|
SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
|
|
|
|
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
|
|
|
|
|
|
|
|
// fold br_cc true, dest -> br dest (unconditional branch)
|
|
|
|
if (SCCC && SCCC->getValue())
|
|
|
|
return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
|
|
|
|
N->getOperand(4));
|
|
|
|
// fold br_cc false, dest -> unconditional fall through
|
|
|
|
if (SCCC && SCCC->isNullValue())
|
|
|
|
return N->getOperand(0);
|
|
|
|
// fold to a simpler setcc
|
|
|
|
if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
|
|
|
|
return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
|
|
|
|
Simp.getOperand(2), Simp.getOperand(0),
|
|
|
|
Simp.getOperand(1), N->getOperand(4));
|
2005-09-19 22:34:01 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.
Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll. Though this is the most simple case and
can be extended in the future, it is still useful. For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:
stw r6, lo16(l5_end_of_array)(r2)
addi r2, r5, -4
stwx r5, r4, r2
- lwzx r5, r4, r2
- rlwinm r5, r5, 0, 0, 30
stwx r5, r4, r2
lwz r2, -4(r4)
ori r2, r2, 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-10 22:04:48 +00:00
|
|
|
SDOperand DAGCombiner::visitLOAD(SDNode *N) {
|
|
|
|
SDOperand Chain = N->getOperand(0);
|
|
|
|
SDOperand Ptr = N->getOperand(1);
|
|
|
|
SDOperand SrcValue = N->getOperand(2);
|
|
|
|
|
|
|
|
// If this load is directly stored, replace the load value with the stored
|
|
|
|
// value.
|
|
|
|
// TODO: Handle store large -> read small portion.
|
|
|
|
// TODO: Handle TRUNCSTORE/EXTLOAD
|
|
|
|
if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
|
|
|
|
Chain.getOperand(1).getValueType() == N->getValueType(0))
|
|
|
|
return CombineTo(N, Chain.getOperand(1), Chain);
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-10-10 22:31:19 +00:00
|
|
|
SDOperand DAGCombiner::visitSTORE(SDNode *N) {
|
|
|
|
SDOperand Chain = N->getOperand(0);
|
|
|
|
SDOperand Value = N->getOperand(1);
|
|
|
|
SDOperand Ptr = N->getOperand(2);
|
|
|
|
SDOperand SrcValue = N->getOperand(3);
|
|
|
|
|
|
|
|
// If this is a store that kills a previous store, remove the previous store.
|
2005-10-10 23:00:08 +00:00
|
|
|
if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
|
2005-10-27 07:10:34 +00:00
|
|
|
Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
|
|
|
|
// Make sure that these stores are the same value type:
|
|
|
|
// FIXME: we really care that the second store is >= size of the first.
|
|
|
|
Value.getValueType() == Chain.getOperand(1).getValueType()) {
|
2005-10-10 22:31:19 +00:00
|
|
|
// Create a new store of Value that replaces both stores.
|
|
|
|
SDNode *PrevStore = Chain.Val;
|
2005-10-10 23:00:08 +00:00
|
|
|
if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
|
|
|
|
return Chain;
|
2005-10-10 22:31:19 +00:00
|
|
|
SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
|
|
|
|
PrevStore->getOperand(0), Value, Ptr,
|
|
|
|
SrcValue);
|
2005-10-10 23:00:08 +00:00
|
|
|
CombineTo(N, NewStore); // Nuke this store.
|
2005-10-10 22:31:19 +00:00
|
|
|
CombineTo(PrevStore, NewStore); // Nuke the previous store.
|
2005-10-10 23:00:08 +00:00
|
|
|
return SDOperand(N, 0);
|
2005-10-10 22:31:19 +00:00
|
|
|
}
|
|
|
|
|
Simplify store(bitconv(x)) to store(x). This allows us to compile this:
void bar(double Y, double *X) {
*X = Y;
}
to this:
bar:
save -96, %o6, %o6
st %i1, [%i2+4]
st %i0, [%i2]
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -104, %o6, %o6
st %i1, [%i6+-4]
st %i0, [%i6+-8]
ldd [%i6+-8], %f0
std %f0, [%i2]
restore %g0, %g0, %g0
retl
nop
on sparcv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24983 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:48:07 +00:00
|
|
|
// If this is a store of a bit convert, store the input value.
|
2006-01-15 18:58:59 +00:00
|
|
|
// FIXME: This needs to know that the resultant store does not need a
|
|
|
|
// higher alignment than the original.
|
|
|
|
if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
|
Simplify store(bitconv(x)) to store(x). This allows us to compile this:
void bar(double Y, double *X) {
*X = Y;
}
to this:
bar:
save -96, %o6, %o6
st %i1, [%i2+4]
st %i0, [%i2]
restore %g0, %g0, %g0
retl
nop
instead of this:
bar:
save -104, %o6, %o6
st %i1, [%i6+-4]
st %i0, [%i6+-8]
ldd [%i6+-8], %f0
std %f0, [%i2]
restore %g0, %g0, %g0
retl
nop
on sparcv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24983 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-23 05:48:07 +00:00
|
|
|
return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
|
|
|
|
Ptr, SrcValue);
|
|
|
|
|
2005-10-10 22:31:19 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2006-03-19 01:27:56 +00:00
|
|
|
SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
|
|
|
|
SDOperand InVec = N->getOperand(0);
|
|
|
|
SDOperand InVal = N->getOperand(1);
|
|
|
|
SDOperand EltNo = N->getOperand(2);
|
|
|
|
|
|
|
|
// If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
|
|
|
|
// vector with the inserted element.
|
|
|
|
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
|
|
|
|
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
|
|
|
|
std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
|
|
|
|
if (Elt < Ops.size())
|
|
|
|
Ops[Elt] = InVal;
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
|
|
|
|
SDOperand InVec = N->getOperand(0);
|
|
|
|
SDOperand InVal = N->getOperand(1);
|
|
|
|
SDOperand EltNo = N->getOperand(2);
|
|
|
|
SDOperand NumElts = N->getOperand(3);
|
|
|
|
SDOperand EltType = N->getOperand(4);
|
|
|
|
|
|
|
|
// If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
|
|
|
|
// vector with the inserted element.
|
|
|
|
if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
|
|
|
|
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
|
|
|
|
std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
|
|
|
|
if (Elt < Ops.size()-2)
|
|
|
|
Ops[Elt] = InVal;
|
|
|
|
return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
|
2005-10-08 00:29:44 +00:00
|
|
|
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
|
|
|
|
|
|
|
|
SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
|
|
|
|
cast<CondCodeSDNode>(N0.getOperand(2))->get());
|
|
|
|
// If we got a simplified select_cc node back from SimplifySelectCC, then
|
|
|
|
// break it down into a new SETCC node, and a new SELECT node, and then return
|
|
|
|
// the SELECT node, since we were called with a SELECT node.
|
|
|
|
if (SCC.Val) {
|
|
|
|
// Check to see if we got a select_cc back (to turn into setcc/select).
|
|
|
|
// Otherwise, just return whatever node we got back, like fabs.
|
|
|
|
if (SCC.getOpcode() == ISD::SELECT_CC) {
|
|
|
|
SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
|
|
|
|
SCC.getOperand(0), SCC.getOperand(1),
|
|
|
|
SCC.getOperand(4));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SETCC.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
|
|
|
|
SCC.getOperand(3), SETCC);
|
|
|
|
}
|
|
|
|
return SCC;
|
|
|
|
}
|
2005-09-19 22:34:01 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
Fold (select C, load A, load B) -> load (select C, A, B). This happens quite
a lot throughout many programs. In particular, specfp triggers it a bunch for
constant FP nodes when you have code like cond ? 1.0 : -1.0.
If the PPC ISel exposed the loads implicit in pic references to external globals,
we would be able to eliminate a load in cases like this as well:
%X = external global int
%Y = external global int
int* %test4(bool %C) {
%G = select bool %C, int* %X, int* %Y
ret int* %G
}
Note that this breaks things that use SrcValue's (see the fixme), but since nothing
uses them yet, this is ok.
Also, simplify some code to use hasOneUse() on an SDOperand instead of hasNUsesOfValue directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23781 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18 06:04:22 +00:00
|
|
|
/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
|
|
|
|
/// are the two values being selected between, see if we can simplify the
|
|
|
|
/// select.
|
|
|
|
///
|
|
|
|
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
|
|
|
|
SDOperand RHS) {
|
|
|
|
|
|
|
|
// If this is a select from two identical things, try to pull the operation
|
|
|
|
// through the select.
|
|
|
|
if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
|
|
|
|
#if 0
|
|
|
|
std::cerr << "SELECT: ["; LHS.Val->dump();
|
|
|
|
std::cerr << "] ["; RHS.Val->dump();
|
|
|
|
std::cerr << "]\n";
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// If this is a load and the token chain is identical, replace the select
|
|
|
|
// of two loads with a load through a select of the address to load from.
|
|
|
|
// This triggers in things like "select bool X, 10.0, 123.0" after the FP
|
|
|
|
// constants have been dropped into the constant pool.
|
|
|
|
if ((LHS.getOpcode() == ISD::LOAD ||
|
|
|
|
LHS.getOpcode() == ISD::EXTLOAD ||
|
|
|
|
LHS.getOpcode() == ISD::ZEXTLOAD ||
|
|
|
|
LHS.getOpcode() == ISD::SEXTLOAD) &&
|
|
|
|
// Token chains must be identical.
|
|
|
|
LHS.getOperand(0) == RHS.getOperand(0) &&
|
|
|
|
// If this is an EXTLOAD, the VT's must match.
|
|
|
|
(LHS.getOpcode() == ISD::LOAD ||
|
|
|
|
LHS.getOperand(3) == RHS.getOperand(3))) {
|
|
|
|
// FIXME: this conflates two src values, discarding one. This is not
|
|
|
|
// the right thing to do, but nothing uses srcvalues now. When they do,
|
|
|
|
// turn SrcValue into a list of locations.
|
|
|
|
SDOperand Addr;
|
|
|
|
if (TheSelect->getOpcode() == ISD::SELECT)
|
|
|
|
Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
|
|
|
|
TheSelect->getOperand(0), LHS.getOperand(1),
|
|
|
|
RHS.getOperand(1));
|
|
|
|
else
|
|
|
|
Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
|
|
|
|
TheSelect->getOperand(0),
|
|
|
|
TheSelect->getOperand(1),
|
|
|
|
LHS.getOperand(1), RHS.getOperand(1),
|
|
|
|
TheSelect->getOperand(4));
|
|
|
|
|
|
|
|
SDOperand Load;
|
|
|
|
if (LHS.getOpcode() == ISD::LOAD)
|
|
|
|
Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
|
|
|
|
Addr, LHS.getOperand(2));
|
|
|
|
else
|
|
|
|
Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
|
|
|
|
LHS.getOperand(0), Addr, LHS.getOperand(2),
|
|
|
|
cast<VTSDNode>(LHS.getOperand(3))->getVT());
|
|
|
|
// Users of the select now use the result of the load.
|
|
|
|
CombineTo(TheSelect, Load);
|
|
|
|
|
|
|
|
// Users of the old loads now use the new load's chain. We know the
|
|
|
|
// old-load value is dead now.
|
|
|
|
CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
|
|
|
|
CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
|
|
|
|
SDOperand N2, SDOperand N3,
|
|
|
|
ISD::CondCode CC) {
|
2005-10-08 00:29:44 +00:00
|
|
|
|
|
|
|
MVT::ValueType VT = N2.getValueType();
|
|
|
|
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
|
|
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
|
|
|
|
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
|
|
|
|
|
|
|
|
// Determine if the condition we're dealing with is constant
|
|
|
|
SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
|
|
|
|
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
|
|
|
|
|
|
|
|
// fold select_cc true, x, y -> x
|
|
|
|
if (SCCC && SCCC->getValue())
|
|
|
|
return N2;
|
|
|
|
// fold select_cc false, x, y -> y
|
|
|
|
if (SCCC && SCCC->getValue() == 0)
|
|
|
|
return N3;
|
|
|
|
|
|
|
|
// Check to see if we can simplify the select into an fabs node
|
|
|
|
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
|
|
|
|
// Allow either -0.0 or 0.0
|
|
|
|
if (CFP->getValue() == 0.0) {
|
|
|
|
// select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
|
|
|
|
if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
|
|
|
|
N0 == N2 && N3.getOpcode() == ISD::FNEG &&
|
|
|
|
N2 == N3.getOperand(0))
|
|
|
|
return DAG.getNode(ISD::FABS, VT, N0);
|
|
|
|
|
|
|
|
// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
|
|
|
|
if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
|
|
|
|
N0 == N3 && N2.getOpcode() == ISD::FNEG &&
|
|
|
|
N2.getOperand(0) == N3)
|
|
|
|
return DAG.getNode(ISD::FABS, VT, N3);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check to see if we can perform the "gzip trick", transforming
|
|
|
|
// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
|
|
|
|
if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
|
|
|
|
MVT::isInteger(N0.getValueType()) &&
|
|
|
|
MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
|
|
|
|
MVT::ValueType XType = N0.getValueType();
|
|
|
|
MVT::ValueType AType = N2.getValueType();
|
|
|
|
if (XType >= AType) {
|
|
|
|
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
|
2005-10-10 21:26:48 +00:00
|
|
|
// single-bit constant.
|
2005-10-08 00:29:44 +00:00
|
|
|
if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
|
|
|
|
unsigned ShCtV = Log2_64(N2C->getValue());
|
|
|
|
ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
|
|
|
|
SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
|
|
|
|
SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Shift.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
if (XType > AType) {
|
|
|
|
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Shift.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::AND, AType, Shift, N2);
|
|
|
|
}
|
|
|
|
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(XType)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Shift.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
if (XType > AType) {
|
|
|
|
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Shift.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
}
|
|
|
|
return DAG.getNode(ISD::AND, AType, Shift, N2);
|
|
|
|
}
|
|
|
|
}
|
2005-10-10 21:26:48 +00:00
|
|
|
|
|
|
|
// fold select C, 16, 0 -> shl C, 4
|
|
|
|
if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
|
|
|
|
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
|
|
|
|
// Get a SetCC of the condition
|
|
|
|
// FIXME: Should probably make sure that setcc is legal if we ever have a
|
|
|
|
// target where it isn't.
|
2006-02-18 02:40:58 +00:00
|
|
|
SDOperand Temp, SCC;
|
2005-10-10 21:26:48 +00:00
|
|
|
// cast from setcc result type to select result type
|
2006-02-18 02:40:58 +00:00
|
|
|
if (AfterLegalize) {
|
|
|
|
SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
|
2005-10-10 21:26:48 +00:00
|
|
|
Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
|
2006-02-18 02:40:58 +00:00
|
|
|
} else {
|
|
|
|
SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
|
2005-10-10 21:26:48 +00:00
|
|
|
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
|
2006-02-18 02:40:58 +00:00
|
|
|
}
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SCC.Val);
|
|
|
|
AddToWorkList(Temp.Val);
|
2005-10-10 21:26:48 +00:00
|
|
|
// shl setcc result by log2 n2c
|
|
|
|
return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
|
|
|
|
DAG.getConstant(Log2_64(N2C->getValue()),
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
|
2005-10-08 00:29:44 +00:00
|
|
|
// Check to see if this is the equivalent of setcc
|
|
|
|
// FIXME: Turn all of these into setcc if setcc if setcc is legal
|
|
|
|
// otherwise, go ahead with the folds.
|
|
|
|
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
|
|
|
|
MVT::ValueType XType = N0.getValueType();
|
|
|
|
if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
|
|
|
|
SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
|
|
|
|
if (Res.getValueType() != VT)
|
|
|
|
Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
|
|
|
|
return Res;
|
|
|
|
}
|
|
|
|
|
|
|
|
// seteq X, 0 -> srl (ctlz X, log2(size(X)))
|
|
|
|
if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
|
|
|
|
TLI.isOperationLegal(ISD::CTLZ, XType)) {
|
|
|
|
SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
|
|
|
|
return DAG.getNode(ISD::SRL, XType, Ctlz,
|
|
|
|
DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
// setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
|
|
|
|
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
|
|
|
|
SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
|
|
|
|
N0);
|
|
|
|
SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
|
|
|
|
DAG.getConstant(~0ULL, XType));
|
|
|
|
return DAG.getNode(ISD::SRL, XType,
|
|
|
|
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(XType)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
// setgt X, -1 -> xor (srl (X, size(X)-1), 1)
|
|
|
|
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
|
|
|
|
SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(XType)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
|
|
|
|
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
|
|
|
|
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
|
|
|
|
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
|
|
|
|
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
|
|
|
|
MVT::ValueType XType = N0.getValueType();
|
|
|
|
if (SubC->isNullValue() && MVT::isInteger(XType)) {
|
|
|
|
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
|
|
|
|
DAG.getConstant(MVT::getSizeInBits(XType)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Shift.Val);
|
|
|
|
AddToWorkList(Add.Val);
|
2005-10-08 00:29:44 +00:00
|
|
|
return DAG.getNode(ISD::XOR, XType, Add, Shift);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-19 22:34:01 +00:00
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
|
2005-10-05 21:43:42 +00:00
|
|
|
SDOperand N1, ISD::CondCode Cond,
|
|
|
|
bool foldBooleans) {
|
2005-09-16 00:54:12 +00:00
|
|
|
// These setcc operations always fold.
|
|
|
|
switch (Cond) {
|
|
|
|
default: break;
|
|
|
|
case ISD::SETFALSE:
|
|
|
|
case ISD::SETFALSE2: return DAG.getConstant(0, VT);
|
|
|
|
case ISD::SETTRUE:
|
|
|
|
case ISD::SETTRUE2: return DAG.getConstant(1, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
|
|
|
|
uint64_t C1 = N1C->getValue();
|
|
|
|
if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
|
|
|
|
uint64_t C0 = N0C->getValue();
|
|
|
|
|
|
|
|
// Sign extend the operands if required
|
|
|
|
if (ISD::isSignedIntSetCC(Cond)) {
|
|
|
|
C0 = N0C->getSignExtended();
|
|
|
|
C1 = N1C->getSignExtended();
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (Cond) {
|
|
|
|
default: assert(0 && "Unknown integer setcc!");
|
|
|
|
case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
|
|
|
|
case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
|
|
|
|
case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
|
|
|
|
case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
|
|
|
|
case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
|
|
|
|
case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
|
|
|
|
case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
|
|
|
|
case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
|
|
|
|
case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
|
|
|
|
case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
|
|
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
|
|
|
|
unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
|
|
|
|
|
|
|
|
// If the comparison constant has bits in the upper part, the
|
|
|
|
// zero-extended value could never match.
|
|
|
|
if (C1 & (~0ULL << InSize)) {
|
|
|
|
unsigned VSize = MVT::getSizeInBits(N0.getValueType());
|
|
|
|
switch (Cond) {
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETEQ: return DAG.getConstant(0, VT);
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETNE: return DAG.getConstant(1, VT);
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETGE:
|
|
|
|
// True if the sign bit of C1 is set.
|
|
|
|
return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETLE:
|
|
|
|
// True if the sign bit of C1 isn't set.
|
|
|
|
return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we can perform the comparison with the low bits.
|
|
|
|
switch (Cond) {
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETNE:
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETULE:
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(C1, N0.getOperand(0).getValueType()),
|
|
|
|
Cond);
|
|
|
|
default:
|
|
|
|
break; // todo, be more careful with signed comparisons
|
|
|
|
}
|
|
|
|
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
|
|
|
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
|
|
|
|
MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
|
|
|
|
unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
|
|
|
|
MVT::ValueType ExtDstTy = N0.getValueType();
|
|
|
|
unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
|
|
|
|
|
|
|
|
// If the extended part has any inconsistent bits, it cannot ever
|
|
|
|
// compare equal. In other words, they have to be all ones or all
|
|
|
|
// zeros.
|
|
|
|
uint64_t ExtBits =
|
|
|
|
(~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
|
|
|
|
if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
|
|
|
|
return DAG.getConstant(Cond == ISD::SETNE, VT);
|
|
|
|
|
|
|
|
SDOperand ZextOp;
|
|
|
|
MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
|
|
|
|
if (Op0Ty == ExtSrcTy) {
|
|
|
|
ZextOp = N0.getOperand(0);
|
|
|
|
} else {
|
|
|
|
int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
|
|
|
|
ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
|
|
|
|
DAG.getConstant(Imm, Op0Ty));
|
|
|
|
}
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(ZextOp.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
// Otherwise, make this a use of a zext.
|
|
|
|
return DAG.getSetCC(VT, ZextOp,
|
|
|
|
DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
|
|
|
|
ExtDstTy),
|
|
|
|
Cond);
|
Compile this:
xori r6, r2, 1
rlwinm r6, r6, 0, 31, 31
cmpwi cr0, r6, 0
bne cr0, LBB1_3 ; endif
to this:
rlwinm r6, r2, 0, 31, 31
cmpwi cr0, r6, 0
beq cr0, LBB1_3 ; endif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26047 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-08 02:13:15 +00:00
|
|
|
} else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
|
|
|
|
(Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
|
|
|
(N0.getOpcode() == ISD::XOR ||
|
|
|
|
(N0.getOpcode() == ISD::AND &&
|
|
|
|
N0.getOperand(0).getOpcode() == ISD::XOR &&
|
|
|
|
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
|
|
|
|
isa<ConstantSDNode>(N0.getOperand(1)) &&
|
|
|
|
cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
|
|
|
|
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
|
|
|
|
// only do this if the top bits are known zero.
|
|
|
|
if (TLI.MaskedValueIsZero(N1,
|
|
|
|
MVT::getIntVTBitMask(N0.getValueType())-1)) {
|
|
|
|
// Okay, get the un-inverted input value.
|
|
|
|
SDOperand Val;
|
|
|
|
if (N0.getOpcode() == ISD::XOR)
|
|
|
|
Val = N0.getOperand(0);
|
|
|
|
else {
|
|
|
|
assert(N0.getOpcode() == ISD::AND &&
|
|
|
|
N0.getOperand(0).getOpcode() == ISD::XOR);
|
|
|
|
// ((X^1)&1)^1 -> X & 1
|
|
|
|
Val = DAG.getNode(ISD::AND, N0.getValueType(),
|
|
|
|
N0.getOperand(0).getOperand(0), N0.getOperand(1));
|
|
|
|
}
|
|
|
|
return DAG.getSetCC(VT, Val, N1,
|
|
|
|
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
|
|
|
|
}
|
2005-09-16 00:54:12 +00:00
|
|
|
}
|
2005-10-05 06:11:08 +00:00
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
uint64_t MinVal, MaxVal;
|
|
|
|
unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
|
|
|
|
if (ISD::isSignedIntSetCC(Cond)) {
|
|
|
|
MinVal = 1ULL << (OperandBitSize-1);
|
|
|
|
if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
|
|
|
|
MaxVal = ~0ULL >> (65-OperandBitSize);
|
|
|
|
else
|
|
|
|
MaxVal = 0;
|
|
|
|
} else {
|
|
|
|
MinVal = 0;
|
|
|
|
MaxVal = ~0ULL >> (64-OperandBitSize);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
|
|
|
|
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
|
|
|
|
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
|
|
|
|
--C1; // X >= C0 --> X > (C0-1)
|
|
|
|
return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
|
|
|
|
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
|
|
|
|
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
|
|
|
|
++C1; // X <= C0 --> X < (C0+1)
|
|
|
|
return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
|
|
|
|
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
|
|
|
|
return DAG.getConstant(0, VT); // X < MIN --> false
|
|
|
|
|
|
|
|
// Canonicalize setgt X, Min --> setne X, Min
|
|
|
|
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
|
|
|
|
return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
|
2005-10-21 21:23:25 +00:00
|
|
|
// Canonicalize setlt X, Max --> setne X, Max
|
|
|
|
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
|
|
|
|
return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
|
2005-09-16 00:54:12 +00:00
|
|
|
|
|
|
|
// If we have setult X, 1, turn it into seteq X, 0
|
|
|
|
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
|
|
|
|
return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
|
|
|
|
ISD::SETEQ);
|
|
|
|
// If we have setugt X, Max-1, turn it into seteq X, Max
|
|
|
|
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
|
|
|
|
return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
|
|
|
|
ISD::SETEQ);
|
|
|
|
|
|
|
|
// If we have "setcc X, C0", check to see if we can shrink the immediate
|
|
|
|
// by changing cc.
|
|
|
|
|
|
|
|
// SETUGT X, SINTMAX -> SETLT X, 0
|
|
|
|
if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
|
|
|
|
C1 == (~0ULL >> (65-OperandBitSize)))
|
|
|
|
return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
|
|
|
|
ISD::SETLT);
|
|
|
|
|
|
|
|
// FIXME: Implement the rest of these.
|
|
|
|
|
|
|
|
// Fold bit comparisons when we can.
|
|
|
|
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
|
|
|
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
|
|
|
|
if (ConstantSDNode *AndRHS =
|
|
|
|
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
|
|
|
|
// Perform the xform if the AND RHS is a single bit.
|
|
|
|
if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
|
|
|
|
return DAG.getNode(ISD::SRL, VT, N0,
|
|
|
|
DAG.getConstant(Log2_64(AndRHS->getValue()),
|
|
|
|
TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
|
|
|
|
// (X & 8) == 8 --> (X & 8) >> 3
|
|
|
|
// Perform the xform if C1 is a single bit.
|
|
|
|
if ((C1 & (C1-1)) == 0) {
|
|
|
|
return DAG.getNode(ISD::SRL, VT, N0,
|
|
|
|
DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (isa<ConstantSDNode>(N0.Val)) {
|
|
|
|
// Ensure that the constant occurs on the RHS.
|
|
|
|
return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
|
|
|
|
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
|
|
|
|
double C0 = N0C->getValue(), C1 = N1C->getValue();
|
|
|
|
|
|
|
|
switch (Cond) {
|
|
|
|
default: break; // FIXME: Implement the rest of these!
|
|
|
|
case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
|
|
|
|
case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
|
|
|
|
case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
|
|
|
|
case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
|
|
|
|
case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
|
|
|
|
case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Ensure that the constant occurs on the RHS.
|
|
|
|
return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (N0 == N1) {
|
|
|
|
// We can always fold X == Y for integer setcc's.
|
|
|
|
if (MVT::isInteger(N0.getValueType()))
|
|
|
|
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
|
|
|
|
unsigned UOF = ISD::getUnorderedFlavor(Cond);
|
|
|
|
if (UOF == 2) // FP operators that are undefined on NaNs.
|
|
|
|
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
|
|
|
|
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
|
|
|
|
return DAG.getConstant(UOF, VT);
|
|
|
|
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
|
|
|
|
// if it is not already.
|
2006-01-18 19:13:41 +00:00
|
|
|
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
|
2005-09-16 00:54:12 +00:00
|
|
|
if (NewCond != Cond)
|
|
|
|
return DAG.getSetCC(VT, N0, N1, NewCond);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
|
|
|
MVT::isInteger(N0.getValueType())) {
|
|
|
|
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
|
|
|
|
N0.getOpcode() == ISD::XOR) {
|
|
|
|
// Simplify (X+Y) == (X+Z) --> Y == Z
|
|
|
|
if (N0.getOpcode() == N1.getOpcode()) {
|
|
|
|
if (N0.getOperand(0) == N1.getOperand(0))
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
|
|
|
|
if (N0.getOperand(1) == N1.getOperand(1))
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
|
|
|
|
if (isCommutativeBinOp(N0.getOpcode())) {
|
|
|
|
// If X op Y == Y op X, try other combinations.
|
|
|
|
if (N0.getOperand(0) == N1.getOperand(1))
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
|
|
|
|
if (N0.getOperand(1) == N1.getOperand(0))
|
2005-10-25 18:57:30 +00:00
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
|
2005-09-16 00:54:12 +00:00
|
|
|
}
|
|
|
|
}
|
add two dag combines:
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:36:13 +00:00
|
|
|
|
|
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
|
|
|
|
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
|
|
|
// Turn (X+C1) == C2 --> X == C2-C1
|
|
|
|
if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
|
|
|
|
N0.getValueType()), Cond);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
|
|
|
|
if (N0.getOpcode() == ISD::XOR)
|
2005-10-05 06:11:08 +00:00
|
|
|
// If we know that all of the inverted bits are zero, don't bother
|
|
|
|
// performing the inversion.
|
add two dag combines:
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:36:13 +00:00
|
|
|
if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
|
2005-10-05 06:11:08 +00:00
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0),
|
add two dag combines:
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:36:13 +00:00
|
|
|
DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
|
2005-10-05 06:11:08 +00:00
|
|
|
N0.getValueType()), Cond);
|
add two dag combines:
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:36:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Turn (C1-X) == C2 --> X == C1-C2
|
|
|
|
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
|
|
|
|
if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(1),
|
|
|
|
DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
|
|
|
|
N0.getValueType()), Cond);
|
2005-10-05 06:11:08 +00:00
|
|
|
}
|
add two dag combines:
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25898 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:36:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-16 00:54:12 +00:00
|
|
|
// Simplify (X+Z) == X --> Z == 0
|
|
|
|
if (N0.getOperand(0) == N1)
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(1),
|
|
|
|
DAG.getConstant(0, N0.getValueType()), Cond);
|
|
|
|
if (N0.getOperand(1) == N1) {
|
|
|
|
if (isCommutativeBinOp(N0.getOpcode()))
|
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0),
|
|
|
|
DAG.getConstant(0, N0.getValueType()), Cond);
|
|
|
|
else {
|
|
|
|
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
|
|
|
|
// (Z-X) == X --> Z == X<<1
|
|
|
|
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
|
|
|
|
N1,
|
|
|
|
DAG.getConstant(1,TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SH.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
|
|
|
|
N1.getOpcode() == ISD::XOR) {
|
|
|
|
// Simplify X == (X+Z) --> Z == 0
|
|
|
|
if (N1.getOperand(0) == N0) {
|
|
|
|
return DAG.getSetCC(VT, N1.getOperand(1),
|
|
|
|
DAG.getConstant(0, N1.getValueType()), Cond);
|
|
|
|
} else if (N1.getOperand(1) == N0) {
|
|
|
|
if (isCommutativeBinOp(N1.getOpcode())) {
|
|
|
|
return DAG.getSetCC(VT, N1.getOperand(0),
|
|
|
|
DAG.getConstant(0, N1.getValueType()), Cond);
|
|
|
|
} else {
|
|
|
|
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
|
|
|
|
// X == (Z-X) --> X<<1 == Z
|
|
|
|
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
|
|
|
|
DAG.getConstant(1,TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(SH.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fold away ALL boolean setcc's.
|
|
|
|
SDOperand Temp;
|
2005-10-05 21:43:42 +00:00
|
|
|
if (N0.getValueType() == MVT::i1 && foldBooleans) {
|
2005-09-16 00:54:12 +00:00
|
|
|
switch (Cond) {
|
|
|
|
default: assert(0 && "Unknown integer setcc!");
|
|
|
|
case ISD::SETEQ: // X == Y -> (X^Y)^1
|
|
|
|
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
|
|
|
N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Temp.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
break;
|
|
|
|
case ISD::SETNE: // X != Y --> (X^Y)
|
|
|
|
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
|
|
|
|
break;
|
|
|
|
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
|
|
|
|
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
|
|
|
|
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
|
|
|
|
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Temp.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
break;
|
|
|
|
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
|
|
|
|
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
|
|
|
|
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
|
|
|
|
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Temp.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
break;
|
|
|
|
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
|
|
|
|
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
|
|
|
|
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
|
|
|
|
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Temp.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
break;
|
|
|
|
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
|
|
|
|
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
|
|
|
|
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
|
|
|
|
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (VT != MVT::i1) {
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(N0.Val);
|
2005-09-16 00:54:12 +00:00
|
|
|
// FIXME: If running after legalize, we probably can't do this.
|
|
|
|
N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
|
|
|
|
}
|
|
|
|
return N0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Could not fold it.
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-10-20 02:15:44 +00:00
|
|
|
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
|
|
|
SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-10-22 18:50:15 +00:00
|
|
|
|
|
|
|
// Check to see if we can do this.
|
|
|
|
if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
|
|
|
|
return SDOperand(); // BuildSDIV only operates on i32 or i64
|
|
|
|
if (!TLI.isOperationLegal(ISD::MULHS, VT))
|
|
|
|
return SDOperand(); // Make sure the target supports MULHS.
|
2005-10-20 02:15:44 +00:00
|
|
|
|
2005-10-20 17:45:03 +00:00
|
|
|
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
|
2005-10-20 02:15:44 +00:00
|
|
|
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
|
|
|
|
|
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
|
|
|
SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
|
|
|
|
DAG.getConstant(magics.m, VT));
|
|
|
|
// If d > 0 and m < 0, add the numerator
|
|
|
|
if (d > 0 && magics.m < 0) {
|
|
|
|
Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Q.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
}
|
|
|
|
// If d < 0 and m > 0, subtract the numerator.
|
|
|
|
if (d < 0 && magics.m > 0) {
|
|
|
|
Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Q.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
}
|
|
|
|
// Shift right algebraic if shift value is nonzero
|
|
|
|
if (magics.s > 0) {
|
|
|
|
Q = DAG.getNode(ISD::SRA, VT, Q,
|
|
|
|
DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Q.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
}
|
|
|
|
// Extract the sign bit and add it to the quotient
|
|
|
|
SDOperand T =
|
2005-10-21 01:51:45 +00:00
|
|
|
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
|
|
|
|
TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(T.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
return DAG.getNode(ISD::ADD, VT, Q, T);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
|
|
|
|
/// return a DAG expression to select that will generate the same value by
|
|
|
|
/// multiplying by a magic number. See:
|
|
|
|
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
|
|
|
SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
|
|
|
|
MVT::ValueType VT = N->getValueType(0);
|
2005-10-22 18:50:15 +00:00
|
|
|
|
|
|
|
// Check to see if we can do this.
|
|
|
|
if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
|
|
|
|
return SDOperand(); // BuildUDIV only operates on i32 or i64
|
|
|
|
if (!TLI.isOperationLegal(ISD::MULHU, VT))
|
|
|
|
return SDOperand(); // Make sure the target supports MULHU.
|
2005-10-20 02:15:44 +00:00
|
|
|
|
|
|
|
uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
|
|
mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
|
|
|
|
|
|
|
|
// Multiply the numerator (operand 0) by the magic value
|
|
|
|
SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
|
|
|
|
DAG.getConstant(magics.m, VT));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(Q.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
|
|
|
|
if (magics.a == 0) {
|
|
|
|
return DAG.getNode(ISD::SRL, VT, Q,
|
|
|
|
DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
|
|
|
|
} else {
|
|
|
|
SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(NPQ.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
|
|
|
|
DAG.getConstant(1, TLI.getShiftAmountTy()));
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(NPQ.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
|
2006-03-01 04:03:14 +00:00
|
|
|
AddToWorkList(NPQ.Val);
|
2005-10-20 02:15:44 +00:00
|
|
|
return DAG.getNode(ISD::SRL, VT, NPQ,
|
|
|
|
DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-01 00:19:25 +00:00
|
|
|
// SelectionDAG::Combine - This is the entry point for the file.
|
|
|
|
//
|
2005-09-01 23:24:04 +00:00
|
|
|
void SelectionDAG::Combine(bool RunningAfterLegalize) {
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2005-09-01 00:19:25 +00:00
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/// run - This is the main entry point to this class.
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///
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2005-09-01 23:24:04 +00:00
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DAGCombiner(*this).Run(RunningAfterLegalize);
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2005-09-01 00:19:25 +00:00
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}
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