2007-10-12 21:30:57 +00:00
|
|
|
//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
|
2003-10-21 15:17:13 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2003-10-21 15:17:13 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
2003-08-03 15:47:25 +00:00
|
|
|
//
|
|
|
|
// This file describes the X86 Register file, defining the registers themselves,
|
|
|
|
// aliases between the registers, and the register classes built out of the
|
|
|
|
// registers.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register definitions...
|
|
|
|
//
|
2003-08-04 04:59:56 +00:00
|
|
|
let Namespace = "X86" in {
|
2004-09-14 04:17:02 +00:00
|
|
|
|
2010-05-24 14:48:12 +00:00
|
|
|
// Subregister indices.
|
2010-05-25 19:49:33 +00:00
|
|
|
def sub_8bit : SubRegIndex;
|
|
|
|
def sub_8bit_hi : SubRegIndex;
|
|
|
|
def sub_16bit : SubRegIndex;
|
|
|
|
def sub_32bit : SubRegIndex;
|
|
|
|
|
|
|
|
def sub_ss : SubRegIndex;
|
|
|
|
def sub_sd : SubRegIndex;
|
|
|
|
def sub_xmm : SubRegIndex;
|
2010-05-24 14:48:12 +00:00
|
|
|
|
|
|
|
|
2004-09-14 04:17:02 +00:00
|
|
|
// In the register alias definitions below, we define which registers alias
|
|
|
|
// which others. We only specify which registers the small registers alias,
|
|
|
|
// because the register file generator is smart enough to figure out that
|
|
|
|
// AL aliases AX if we tell it that AX aliased AL (for example).
|
|
|
|
|
2007-11-11 19:50:10 +00:00
|
|
|
// Dwarf numbering is different for 32-bit and 64-bit, and there are
|
|
|
|
// variations by target as well. Currently the first entry is for X86-64,
|
2008-01-25 00:34:13 +00:00
|
|
|
// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
|
|
|
|
// and debug information on X86-32/Darwin)
|
2007-11-07 21:48:35 +00:00
|
|
|
|
2007-04-20 21:15:21 +00:00
|
|
|
// 8-bit registers
|
|
|
|
// Low registers
|
2008-07-07 22:21:06 +00:00
|
|
|
def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
|
|
|
|
def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
|
|
|
|
def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
|
|
|
|
def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
|
2006-09-08 06:48:29 +00:00
|
|
|
|
|
|
|
// X86-64 only
|
2008-07-07 22:21:06 +00:00
|
|
|
def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
|
|
|
|
def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
|
|
|
|
def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
|
|
|
|
def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
|
|
|
|
def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
|
|
|
|
def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
|
|
|
|
def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
|
|
|
|
def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
|
|
|
|
def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
|
|
|
|
def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
|
|
|
|
def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
|
|
|
|
def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
|
2007-04-20 21:15:21 +00:00
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// High registers. On x86-64, these cannot be used in any instruction
|
|
|
|
// with a REX prefix.
|
2008-07-07 22:21:06 +00:00
|
|
|
def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
|
|
|
|
def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
|
|
|
|
def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
|
|
|
|
def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
|
2006-09-08 06:48:29 +00:00
|
|
|
|
2003-08-03 15:47:25 +00:00
|
|
|
// 16-bit registers
|
2010-05-26 17:27:12 +00:00
|
|
|
let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
|
2009-04-13 15:18:42 +00:00
|
|
|
def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
|
|
|
|
def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
|
|
|
|
def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
|
|
|
|
def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
|
|
|
let SubRegIndices = [sub_8bit] in {
|
2008-07-07 22:21:06 +00:00
|
|
|
def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
|
|
|
|
def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
|
|
|
|
def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
|
|
|
|
def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2008-07-07 22:21:06 +00:00
|
|
|
def IP : Register<"ip">, DwarfRegNum<[16]>;
|
2003-08-03 15:47:25 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
// X86-64 only
|
2010-05-26 17:27:12 +00:00
|
|
|
let SubRegIndices = [sub_8bit] in {
|
2008-07-07 22:21:06 +00:00
|
|
|
def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
|
|
|
|
def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
|
|
|
|
def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
|
|
|
|
def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
|
|
|
|
def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
|
|
|
|
def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
|
|
|
|
def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
|
|
|
|
def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2007-04-20 21:15:21 +00:00
|
|
|
// 32-bit registers
|
2010-05-26 17:27:12 +00:00
|
|
|
let SubRegIndices = [sub_16bit] in {
|
2008-07-07 22:21:06 +00:00
|
|
|
def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
|
|
|
|
def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
|
|
|
|
def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
|
|
|
|
def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
|
|
|
|
def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
|
|
|
|
def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
|
|
|
|
def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
|
|
|
|
def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
|
|
|
|
def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
|
2007-04-20 21:15:21 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
// X86-64 only
|
2008-07-07 22:21:06 +00:00
|
|
|
def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
|
|
|
|
def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
|
|
|
|
def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
|
|
|
|
def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
|
|
|
|
def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
|
|
|
|
def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
|
|
|
|
def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
|
|
|
|
def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2006-09-08 06:48:29 +00:00
|
|
|
|
2007-04-20 21:15:21 +00:00
|
|
|
// 64-bit registers, X86-64 only
|
2010-05-26 17:27:12 +00:00
|
|
|
let SubRegIndices = [sub_32bit] in {
|
2008-07-07 22:21:06 +00:00
|
|
|
def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
|
|
|
|
def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
|
|
|
|
def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
|
|
|
|
def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
|
|
|
|
def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
|
|
|
|
def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
|
|
|
|
def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
|
|
|
|
def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
|
|
|
|
|
|
|
|
def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
|
|
|
|
def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
|
|
|
|
def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
|
|
|
|
def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
|
|
|
|
def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
|
|
|
|
def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
|
|
|
|
def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
|
|
|
|
def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
|
|
|
|
def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2006-02-20 22:34:53 +00:00
|
|
|
|
|
|
|
// MMX Registers. These are actually aliased to ST0 .. ST7
|
2008-07-07 22:21:06 +00:00
|
|
|
def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
|
|
|
|
def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
|
|
|
|
def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
|
|
|
|
def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
|
|
|
|
def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
|
|
|
|
def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
|
|
|
|
def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
|
|
|
|
def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
|
2010-07-09 18:27:43 +00:00
|
|
|
|
2003-08-03 15:47:25 +00:00
|
|
|
// Pseudo Floating Point registers
|
2008-07-07 22:21:06 +00:00
|
|
|
def FP0 : Register<"fp0">;
|
|
|
|
def FP1 : Register<"fp1">;
|
|
|
|
def FP2 : Register<"fp2">;
|
|
|
|
def FP3 : Register<"fp3">;
|
|
|
|
def FP4 : Register<"fp4">;
|
|
|
|
def FP5 : Register<"fp5">;
|
2010-07-09 18:27:43 +00:00
|
|
|
def FP6 : Register<"fp6">;
|
2003-08-03 15:47:25 +00:00
|
|
|
|
2010-05-26 17:27:12 +00:00
|
|
|
// XMM Registers, used by the various SSE instruction set extensions.
|
|
|
|
// The sub_ss and sub_sd subregs are the same registers with another regclass.
|
|
|
|
let CompositeIndices = [(sub_ss), (sub_sd)] in {
|
2008-07-07 22:21:06 +00:00
|
|
|
def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
|
|
|
|
def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
|
|
|
|
def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
|
|
|
|
def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
|
|
|
|
def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
|
|
|
|
def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
|
|
|
|
def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
|
|
|
|
def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
|
2006-09-08 06:48:29 +00:00
|
|
|
|
|
|
|
// X86-64 only
|
2008-07-07 22:21:06 +00:00
|
|
|
def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
|
|
|
|
def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
|
|
|
|
def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
|
|
|
|
def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
|
|
|
|
def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
|
|
|
|
def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
|
|
|
|
def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
|
|
|
|
def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2005-06-27 21:20:31 +00:00
|
|
|
|
2009-06-29 22:50:51 +00:00
|
|
|
// YMM Registers, used by AVX instructions
|
2010-07-09 21:46:19 +00:00
|
|
|
let SubRegIndices = [sub_xmm] in {
|
2010-02-28 00:17:42 +00:00
|
|
|
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
|
|
|
|
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
|
|
|
|
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
|
|
|
|
def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
|
|
|
|
def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
|
|
|
|
def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
|
|
|
|
def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
|
|
|
|
def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
|
|
|
|
def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
|
|
|
|
def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
|
|
|
|
def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
|
|
|
|
def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
|
|
|
|
def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
|
|
|
|
def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
|
|
|
|
def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
|
|
|
|
def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
|
2010-05-26 17:27:12 +00:00
|
|
|
}
|
2009-06-29 22:50:51 +00:00
|
|
|
|
2003-08-03 15:47:25 +00:00
|
|
|
// Floating point stack registers
|
2008-07-07 22:21:06 +00:00
|
|
|
def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
|
|
|
|
def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
|
|
|
|
def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
|
|
|
|
def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
|
|
|
|
def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
|
|
|
|
def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
|
|
|
|
def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
|
|
|
|
def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
|
2007-09-11 19:53:28 +00:00
|
|
|
|
|
|
|
// Status flags register
|
2009-03-04 01:41:49 +00:00
|
|
|
def EFLAGS : Register<"flags">;
|
2009-04-08 21:14:34 +00:00
|
|
|
|
|
|
|
// Segment registers
|
|
|
|
def CS : Register<"cs">;
|
|
|
|
def DS : Register<"ds">;
|
|
|
|
def SS : Register<"ss">;
|
|
|
|
def ES : Register<"es">;
|
|
|
|
def FS : Register<"fs">;
|
|
|
|
def GS : Register<"gs">;
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
|
|
|
|
// Debug registers
|
|
|
|
def DR0 : Register<"dr0">;
|
|
|
|
def DR1 : Register<"dr1">;
|
|
|
|
def DR2 : Register<"dr2">;
|
|
|
|
def DR3 : Register<"dr3">;
|
|
|
|
def DR4 : Register<"dr4">;
|
|
|
|
def DR5 : Register<"dr5">;
|
|
|
|
def DR6 : Register<"dr6">;
|
|
|
|
def DR7 : Register<"dr7">;
|
|
|
|
|
|
|
|
// Condition registers
|
2010-05-06 20:59:00 +00:00
|
|
|
def CR0 : Register<"cr0">;
|
|
|
|
def CR1 : Register<"cr1">;
|
|
|
|
def CR2 : Register<"cr2">;
|
|
|
|
def CR3 : Register<"cr3">;
|
|
|
|
def CR4 : Register<"cr4">;
|
|
|
|
def CR5 : Register<"cr5">;
|
|
|
|
def CR6 : Register<"cr6">;
|
|
|
|
def CR7 : Register<"cr7">;
|
|
|
|
def CR8 : Register<"cr8">;
|
2003-08-03 15:47:25 +00:00
|
|
|
}
|
|
|
|
|
2007-07-28 19:03:30 +00:00
|
|
|
|
2003-08-03 15:47:25 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register Class Definitions... now that we have all of the pieces, define the
|
|
|
|
// top-level register classes. The order specified in the register list is
|
|
|
|
// implicitly defined to be the register allocation order.
|
|
|
|
//
|
2005-01-05 16:09:16 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
// List call-clobbered registers before callee-save registers. RBX, RBP, (and
|
|
|
|
// R12, R13, R14, and R15 for X86-64) are callee-save registers.
|
|
|
|
// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
|
|
|
|
// R8B, ... R15B.
|
2008-11-19 17:19:35 +00:00
|
|
|
// Allocate R12 and R13 last, as these require an extra byte when
|
|
|
|
// encoded in x86_64 instructions.
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
|
|
|
|
// 64-bit mode. The main complication is that they cannot be encoded in an
|
|
|
|
// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
|
|
|
|
// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
|
|
|
|
// cannot be encoded.
|
2006-09-08 06:48:29 +00:00
|
|
|
def GR8 : RegisterClass<"X86", [i8], 8,
|
2009-07-30 00:40:42 +00:00
|
|
|
[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
|
2008-11-19 17:19:35 +00:00
|
|
|
R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
|
2006-09-08 06:48:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 19:25:38 +00:00
|
|
|
static const unsigned X86_GR8_AO_64[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
|
|
|
|
X86::R8B, X86::R9B, X86::R10B, X86::R11B,
|
|
|
|
X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
|
|
|
|
};
|
2006-09-08 06:48:29 +00:00
|
|
|
|
|
|
|
GR8Class::iterator
|
|
|
|
GR8Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2009-07-30 00:40:42 +00:00
|
|
|
if (Subtarget.is64Bit())
|
2006-09-08 06:48:29 +00:00
|
|
|
return X86_GR8_AO_64;
|
2009-07-30 00:40:42 +00:00
|
|
|
else
|
|
|
|
return begin();
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
2005-01-05 16:09:16 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
GR8Class::iterator
|
|
|
|
GR8Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 06:48:29 +00:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
2006-09-08 06:48:29 +00:00
|
|
|
if (!Subtarget.is64Bit())
|
2009-07-30 00:40:42 +00:00
|
|
|
// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
|
|
|
|
return begin() + 8;
|
2010-04-06 20:26:37 +00:00
|
|
|
else if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate SPL or BPL.
|
|
|
|
return array_endof(X86_GR8_AO_64) - 1;
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate SPL.
|
2009-07-30 00:10:18 +00:00
|
|
|
return array_endof(X86_GR8_AO_64);
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
def GR16 : RegisterClass<"X86", [i16], 16,
|
|
|
|
[AX, CX, DX, SI, DI, BX, BP, SP,
|
2008-11-19 17:19:35 +00:00
|
|
|
R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
|
2005-08-19 19:13:20 +00:00
|
|
|
let MethodProtos = [{
|
2006-09-08 06:48:29 +00:00
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
2006-08-17 22:00:08 +00:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 19:13:20 +00:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 19:25:38 +00:00
|
|
|
static const unsigned X86_GR16_AO_64[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
|
|
|
|
X86::R8W, X86::R9W, X86::R10W, X86::R11W,
|
|
|
|
X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
|
|
|
|
};
|
2006-09-08 06:48:29 +00:00
|
|
|
|
|
|
|
GR16Class::iterator
|
|
|
|
GR16Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2009-07-30 00:40:42 +00:00
|
|
|
if (Subtarget.is64Bit())
|
|
|
|
return X86_GR16_AO_64;
|
|
|
|
else
|
|
|
|
return begin();
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
|
|
|
|
2006-05-16 07:21:53 +00:00
|
|
|
GR16Class::iterator
|
2006-08-17 22:00:08 +00:00
|
|
|
GR16Class::allocation_order_end(const MachineFunction &MF) const {
|
2006-09-08 06:48:29 +00:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 06:48:29 +00:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2006-09-08 06:48:29 +00:00
|
|
|
if (Subtarget.is64Bit()) {
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate SP or BP.
|
|
|
|
return array_endof(X86_GR16_AO_64) - 1;
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate SP.
|
2009-07-30 00:10:18 +00:00
|
|
|
return array_endof(X86_GR16_AO_64);
|
2006-09-08 06:48:29 +00:00
|
|
|
} else {
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate EBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate SP or BP.
|
|
|
|
return begin() + 6;
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate SP.
|
|
|
|
return begin() + 7;
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
2003-08-03 15:47:25 +00:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2010-07-09 18:27:43 +00:00
|
|
|
def GR32 : RegisterClass<"X86", [i32], 32,
|
2006-09-08 06:48:29 +00:00
|
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
|
2008-11-19 17:19:35 +00:00
|
|
|
R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
|
2005-08-19 19:13:20 +00:00
|
|
|
let MethodProtos = [{
|
2006-09-08 06:48:29 +00:00
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
2006-08-17 22:00:08 +00:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 19:13:20 +00:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 19:25:38 +00:00
|
|
|
static const unsigned X86_GR32_AO_64[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
|
|
|
|
X86::R8D, X86::R9D, X86::R10D, X86::R11D,
|
|
|
|
X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
|
|
|
|
};
|
2006-09-08 06:48:29 +00:00
|
|
|
|
|
|
|
GR32Class::iterator
|
|
|
|
GR32Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2009-07-30 00:40:42 +00:00
|
|
|
if (Subtarget.is64Bit())
|
|
|
|
return X86_GR32_AO_64;
|
|
|
|
else
|
|
|
|
return begin();
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
|
|
|
|
2006-05-16 07:21:53 +00:00
|
|
|
GR32Class::iterator
|
2006-08-17 22:00:08 +00:00
|
|
|
GR32Class::allocation_order_end(const MachineFunction &MF) const {
|
2006-09-08 06:48:29 +00:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 06:48:29 +00:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2006-09-08 06:48:29 +00:00
|
|
|
if (Subtarget.is64Bit()) {
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate ESP or EBP.
|
|
|
|
return array_endof(X86_GR32_AO_64) - 1;
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate ESP.
|
2009-07-30 00:10:18 +00:00
|
|
|
return array_endof(X86_GR32_AO_64);
|
2006-09-08 06:48:29 +00:00
|
|
|
} else {
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate EBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate ESP or EBP.
|
|
|
|
return begin() + 6;
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate ESP.
|
|
|
|
return begin() + 7;
|
2006-09-08 06:48:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2009-07-30 01:56:29 +00:00
|
|
|
// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
|
|
|
|
// RIP isn't really a register and it can't be used anywhere except in an
|
|
|
|
// address, but it doesn't cause trouble.
|
2010-07-09 18:27:43 +00:00
|
|
|
def GR64 : RegisterClass<"X86", [i64], 64,
|
2006-09-08 06:48:29 +00:00
|
|
|
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
|
2009-06-26 21:25:00 +00:00
|
|
|
RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16 sub_16bit),
|
|
|
|
(GR32 sub_32bit)];
|
2006-09-08 06:48:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR64Class::iterator
|
|
|
|
GR64Class::allocation_order_end(const MachineFunction &MF) const {
|
2007-01-23 00:57:47 +00:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2008-03-11 07:16:00 +00:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2008-03-11 07:16:00 +00:00
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return begin(); // None of these are allocatable in 32-bit.
|
2010-04-06 20:26:37 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-06-26 21:25:00 +00:00
|
|
|
return end()-3; // If so, don't allocate RIP, RSP or RBP
|
2003-08-03 15:47:25 +00:00
|
|
|
else
|
2009-06-26 21:25:00 +00:00
|
|
|
return end()-2; // If not, just don't allocate RIP or RSP
|
2003-08-03 15:47:25 +00:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2009-09-15 18:47:29 +00:00
|
|
|
// Segment registers for use by MOV instructions (and others) that have a
|
|
|
|
// segment register as one operand. Always contain a 16-bit segment
|
|
|
|
// descriptor.
|
|
|
|
def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
|
|
|
|
}
|
2006-09-08 06:48:29 +00:00
|
|
|
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
// Debug registers.
|
2010-07-09 18:27:43 +00:00
|
|
|
def DEBUG_REG : RegisterClass<"X86", [i32], 32,
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
[DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
|
|
|
|
}
|
|
|
|
|
|
|
|
// Control registers.
|
2010-05-06 20:59:00 +00:00
|
|
|
def CONTROL_REG : RegisterClass<"X86", [i64], 64,
|
|
|
|
[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
}
|
|
|
|
|
2009-04-27 16:41:36 +00:00
|
|
|
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
|
|
|
|
// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
|
|
|
|
// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
|
|
|
|
// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
|
|
|
|
// and GR64_ABCD are classes for registers that support 8-bit h-register
|
|
|
|
// operations.
|
|
|
|
def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
|
|
|
|
}
|
|
|
|
def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
2009-04-27 16:33:14 +00:00
|
|
|
def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
|
2007-07-28 19:03:30 +00:00
|
|
|
}
|
2009-04-27 16:33:14 +00:00
|
|
|
def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
|
|
|
|
(GR8_ABCD_H sub_8bit_hi),
|
|
|
|
(GR16_ABCD sub_16bit)];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
2009-04-27 16:33:14 +00:00
|
|
|
def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
|
|
|
|
(GR8_ABCD_H sub_8bit_hi),
|
|
|
|
(GR16_ABCD sub_16bit),
|
|
|
|
(GR32_ABCD sub_32bit)];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
2010-03-14 03:48:46 +00:00
|
|
|
def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
|
2010-03-14 03:48:46 +00:00
|
|
|
}
|
|
|
|
def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
|
|
|
|
R8, R9, R11]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16 sub_16bit),
|
|
|
|
(GR32_TC sub_32bit)];
|
2010-03-14 03:48:46 +00:00
|
|
|
}
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
|
2010-01-26 18:14:22 +00:00
|
|
|
// GR8_NOREX - GR8 registers which do not require a REX prefix.
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
def GR8_NOREX : RegisterClass<"X86", [i8], 8,
|
2010-01-26 18:14:22 +00:00
|
|
|
[AL, CL, DL, AH, CH, DH, BL, BH]> {
|
2009-04-14 16:57:43 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2010-01-26 18:30:24 +00:00
|
|
|
// In 64-bit mode, it's not safe to blindly allocate H registers.
|
2009-04-14 16:57:43 +00:00
|
|
|
static const unsigned X86_GR8_NOREX_AO_64[] = {
|
2010-01-26 18:30:24 +00:00
|
|
|
X86::AL, X86::CL, X86::DL, X86::BL
|
2009-04-14 16:57:43 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
GR8_NOREXClass::iterator
|
|
|
|
GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2009-07-30 00:40:42 +00:00
|
|
|
if (Subtarget.is64Bit())
|
2009-04-14 16:57:43 +00:00
|
|
|
return X86_GR8_NOREX_AO_64;
|
2009-07-30 00:40:42 +00:00
|
|
|
else
|
|
|
|
return begin();
|
2009-04-14 16:57:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
GR8_NOREXClass::iterator
|
|
|
|
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-01-26 18:30:24 +00:00
|
|
|
if (Subtarget.is64Bit())
|
2009-07-30 00:10:18 +00:00
|
|
|
return array_endof(X86_GR8_NOREX_AO_64);
|
2010-01-26 18:30:24 +00:00
|
|
|
else
|
|
|
|
return end();
|
2009-04-14 16:57:43 +00:00
|
|
|
}
|
|
|
|
}];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
2010-01-26 18:14:22 +00:00
|
|
|
// GR16_NOREX - GR16 registers which do not require a REX prefix.
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
def GR16_NOREX : RegisterClass<"X86", [i16], 16,
|
|
|
|
[AX, CX, DX, SI, DI, BX, BP, SP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
|
2009-04-15 00:10:16 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR16_NOREXClass::iterator
|
|
|
|
GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate SP or BP.
|
|
|
|
return end() - 2;
|
2009-04-15 00:10:16 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate SP.
|
|
|
|
return end() - 1;
|
2009-04-15 00:10:16 +00:00
|
|
|
}
|
|
|
|
}];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
|
|
|
// GR32_NOREX - GR32 registers which do not require a REX prefix.
|
|
|
|
def GR32_NOREX : RegisterClass<"X86", [i32], 32,
|
|
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16_NOREX sub_16bit)];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR32_NOREXClass::iterator
|
|
|
|
GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 00:40:42 +00:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 00:40:42 +00:00
|
|
|
// If so, don't allocate ESP or EBP.
|
|
|
|
return end() - 2;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
else
|
2009-07-30 00:40:42 +00:00
|
|
|
// If not, just don't allocate ESP.
|
|
|
|
return end() - 1;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
// GR64_NOREX - GR64 registers which do not require a REX prefix.
|
|
|
|
def GR64_NOREX : RegisterClass<"X86", [i64], 64,
|
2009-10-05 15:42:08 +00:00
|
|
|
[RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16_NOREX sub_16bit),
|
|
|
|
(GR32_NOREX sub_32bit)];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR64_NOREXClass::iterator
|
|
|
|
GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 01:56:29 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-10-05 15:42:08 +00:00
|
|
|
// If so, don't allocate RIP, RSP or RBP.
|
|
|
|
return end() - 3;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
else
|
2009-10-05 15:42:08 +00:00
|
|
|
// If not, just don't allocate RIP or RSP.
|
|
|
|
return end() - 2;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
}
|
|
|
|
}];
|
2007-07-28 19:03:30 +00:00
|
|
|
}
|
2006-05-08 08:01:26 +00:00
|
|
|
|
2009-07-30 01:56:29 +00:00
|
|
|
// GR32_NOSP - GR32 registers except ESP.
|
|
|
|
def GR32_NOSP : RegisterClass<"X86", [i32], 32,
|
|
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP,
|
|
|
|
R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
|
2009-07-30 01:56:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
static const unsigned X86_GR32_NOSP_AO_64[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
|
|
|
|
X86::R8D, X86::R9D, X86::R10D, X86::R11D,
|
|
|
|
X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
|
|
|
|
};
|
|
|
|
|
|
|
|
GR32_NOSPClass::iterator
|
|
|
|
GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget.is64Bit())
|
|
|
|
return X86_GR32_NOSP_AO_64;
|
|
|
|
else
|
|
|
|
return begin();
|
|
|
|
}
|
|
|
|
|
|
|
|
GR32_NOSPClass::iterator
|
|
|
|
GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 01:56:29 +00:00
|
|
|
if (Subtarget.is64Bit()) {
|
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 01:56:29 +00:00
|
|
|
// If so, don't allocate EBP.
|
|
|
|
return array_endof(X86_GR32_NOSP_AO_64) - 1;
|
|
|
|
else
|
|
|
|
// If not, any reg in this class is ok.
|
|
|
|
return array_endof(X86_GR32_NOSP_AO_64);
|
|
|
|
} else {
|
|
|
|
// Does the function dedicate EBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 01:56:29 +00:00
|
|
|
// If so, don't allocate EBP.
|
|
|
|
return begin() + 6;
|
|
|
|
else
|
|
|
|
// If not, any reg in this class is ok.
|
|
|
|
return begin() + 7;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
// GR64_NOSP - GR64 registers except RSP (and RIP).
|
|
|
|
def GR64_NOSP : RegisterClass<"X86", [i64], 64,
|
|
|
|
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
|
|
|
|
RBX, R14, R15, R12, R13, RBP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16 sub_16bit),
|
|
|
|
(GR32_NOSP sub_32bit)];
|
2009-07-30 01:56:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR64_NOSPClass::iterator
|
|
|
|
GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 01:56:29 +00:00
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return begin(); // None of these are allocatable in 32-bit.
|
2010-04-06 20:26:37 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 01:56:29 +00:00
|
|
|
return end()-1; // If so, don't allocate RBP
|
|
|
|
else
|
|
|
|
return end(); // If not, any reg in this class is ok.
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
// GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
|
|
|
|
def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
|
|
|
|
[RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
|
|
(GR16_NOREX sub_16bit),
|
|
|
|
(GR32_NOREX sub_32bit)];
|
2009-07-30 01:56:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR64_NOREX_NOSPClass::iterator
|
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 00:01:26 +00:00
|
|
|
GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
|
|
|
|
{
|
2009-07-30 01:56:29 +00:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2010-04-06 20:26:37 +00:00
|
|
|
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
|
2009-07-30 01:56:29 +00:00
|
|
|
// Does the function dedicate RBP to being a frame ptr?
|
2010-04-06 20:26:37 +00:00
|
|
|
if (RI->hasFP(MF) || MFI->getReserveFP())
|
2009-07-30 01:56:29 +00:00
|
|
|
// If so, don't allocate RBP.
|
|
|
|
return end() - 1;
|
|
|
|
else
|
|
|
|
// If not, any reg in this class is ok.
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2008-11-13 21:52:36 +00:00
|
|
|
// A class to support the 'A' assembler constraint: EAX then EDX.
|
2009-07-30 17:02:08 +00:00
|
|
|
def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
|
|
|
|
(GR8_ABCD_H sub_8bit_hi),
|
|
|
|
(GR16_ABCD sub_16bit)];
|
2009-07-30 17:02:08 +00:00
|
|
|
}
|
2008-11-13 21:52:36 +00:00
|
|
|
|
2005-12-20 22:59:51 +00:00
|
|
|
// Scalar SSE2 floating point registers.
|
|
|
|
def FR32 : RegisterClass<"X86", [f32], 32,
|
2006-09-08 06:48:29 +00:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
FR32Class::iterator
|
|
|
|
FR32Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2005-12-20 22:59:51 +00:00
|
|
|
def FR64 : RegisterClass<"X86", [f64], 64,
|
2006-09-08 06:48:29 +00:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
FR64Class::iterator
|
|
|
|
FR64Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2005-06-27 21:20:31 +00:00
|
|
|
|
2004-12-02 18:17:31 +00:00
|
|
|
// FIXME: This sets up the floating point register files as though they are f64
|
|
|
|
// values, though they really are f80 values. This will cause us to spill
|
|
|
|
// values as 64-bit quantities instead of 80-bit quantities, which is much much
|
|
|
|
// faster on common hardware. In reality, this should be controlled by a
|
|
|
|
// command line option or something.
|
|
|
|
|
2008-03-10 21:08:41 +00:00
|
|
|
def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
|
|
def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
|
|
def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
2003-08-03 15:47:25 +00:00
|
|
|
|
2004-09-21 21:22:11 +00:00
|
|
|
// Floating point stack registers (these are not allocatable by the
|
|
|
|
// register allocator - the floating point stackifier is responsible
|
|
|
|
// for transforming FPn allocations to STn registers)
|
2008-03-10 21:08:41 +00:00
|
|
|
def RST : RegisterClass<"X86", [f80, f64, f32], 32,
|
2005-08-19 18:51:57 +00:00
|
|
|
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
|
2005-08-19 19:13:20 +00:00
|
|
|
let MethodProtos = [{
|
2006-08-17 22:00:08 +00:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 19:13:20 +00:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
RSTClass::iterator
|
2006-08-17 22:00:08 +00:00
|
|
|
RSTClass::allocation_order_end(const MachineFunction &MF) const {
|
2004-09-21 21:22:11 +00:00
|
|
|
return begin();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
2006-02-20 22:34:53 +00:00
|
|
|
|
2006-02-21 01:38:21 +00:00
|
|
|
// Generic vector registers: VR64 and VR128.
|
2010-07-05 04:38:33 +00:00
|
|
|
def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
|
2006-02-21 01:38:21 +00:00
|
|
|
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
|
|
|
|
def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
|
2006-09-08 06:48:29 +00:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
|
2010-07-09 18:27:43 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
VR128Class::iterator
|
|
|
|
VR128Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
2010-07-09 18:27:43 +00:00
|
|
|
|
|
|
|
def VR256 : RegisterClass<"X86", [v8i32, v4i64, v8f32, v4f64], 256,
|
2009-06-29 22:50:51 +00:00
|
|
|
[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
|
|
|
YMM8, YMM9, YMM10, YMM11,
|
2010-02-28 00:17:42 +00:00
|
|
|
YMM12, YMM13, YMM14, YMM15]> {
|
2010-05-24 21:46:58 +00:00
|
|
|
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
|
2010-07-09 18:27:43 +00:00
|
|
|
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
VR256Class::iterator
|
|
|
|
VR256Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
2010-02-28 00:17:42 +00:00
|
|
|
}
|
2007-09-11 19:53:28 +00:00
|
|
|
|
|
|
|
// Status flags registers.
|
2007-09-19 01:36:39 +00:00
|
|
|
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
|
|
|
|
let CopyCost = -1; // Don't allow copying of status registers.
|
|
|
|
}
|