2005-10-16 05:39:50 +00:00
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//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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//===----------------------------------------------------------------------===//
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//
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2005-10-16 05:39:50 +00:00
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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2004-08-17 04:55:41 +00:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2005-10-14 23:45:43 +00:00
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#include "PPCInstrBuilder.h"
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2005-10-14 23:59:06 +00:00
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#include "PPCRegisterInfo.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2006-04-07 16:34:46 +00:00
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#include "llvm/CodeGen/MachineDebugInfo.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-03-23 18:12:57 +00:00
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#include "llvm/CodeGen/MachineLocation.h"
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2006-04-07 16:34:46 +00:00
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/Target/TargetFrameInfo.h"
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2006-04-17 21:48:13 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2005-11-06 09:00:38 +00:00
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#include "llvm/Support/MathExtras.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/STLExtras.h"
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2004-08-17 04:55:41 +00:00
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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2006-04-17 21:07:20 +00:00
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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switch (RegEnum) {
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case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
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case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
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case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
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case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
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case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
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case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
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case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
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case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
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case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
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case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
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case PPC::R10: case PPC::F10: case PPC::V10: return 10;
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case PPC::R11: case PPC::F11: case PPC::V11: return 11;
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case PPC::R12: case PPC::F12: case PPC::V12: return 12;
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case PPC::R13: case PPC::F13: case PPC::V13: return 13;
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case PPC::R14: case PPC::F14: case PPC::V14: return 14;
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case PPC::R15: case PPC::F15: case PPC::V15: return 15;
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case PPC::R16: case PPC::F16: case PPC::V16: return 16;
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case PPC::R17: case PPC::F17: case PPC::V17: return 17;
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case PPC::R18: case PPC::F18: case PPC::V18: return 18;
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case PPC::R19: case PPC::F19: case PPC::V19: return 19;
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case PPC::R20: case PPC::F20: case PPC::V20: return 20;
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case PPC::R21: case PPC::F21: case PPC::V21: return 21;
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case PPC::R22: case PPC::F22: case PPC::V22: return 22;
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case PPC::R23: case PPC::F23: case PPC::V23: return 23;
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case PPC::R24: case PPC::F24: case PPC::V24: return 24;
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case PPC::R25: case PPC::F25: case PPC::V25: return 25;
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case PPC::R26: case PPC::F26: case PPC::V26: return 26;
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case PPC::R27: case PPC::F27: case PPC::V27: return 27;
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case PPC::R28: case PPC::F28: case PPC::V28: return 28;
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case PPC::R29: case PPC::F29: case PPC::V29: return 29;
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case PPC::R30: case PPC::F30: case PPC::V30: return 30;
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case PPC::R31: case PPC::F31: case PPC::V31: return 31;
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default:
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std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
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abort();
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}
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}
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2005-10-16 05:39:50 +00:00
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PPCRegisterInfo::PPCRegisterInfo()
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2005-10-14 23:37:35 +00:00
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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2005-04-21 23:30:14 +00:00
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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2004-08-17 04:55:41 +00:00
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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2005-10-18 00:28:58 +00:00
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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2004-08-17 04:55:41 +00:00
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}
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2005-04-21 23:30:14 +00:00
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void
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2005-10-16 05:39:50 +00:00
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PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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2004-08-17 04:55:41 +00:00
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if (SrcReg == PPC::LR) {
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2006-03-16 22:24:02 +00:00
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// FIXME: this spills LR immediately to memory in one step. To do this, we
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// use R11, which we know cannot be used in the prolog/epilog. This is a
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// hack.
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2005-08-18 23:24:50 +00:00
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::CRRCRegisterClass) {
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2006-06-12 23:59:16 +00:00
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// FIXME: We use R0 here, because it isn't available for RA.
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2006-06-12 21:50:57 +00:00
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// We need to store the CR in the low 4-bits of the saved value. First,
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// issue a MFCR to save all of the CRBits.
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2006-06-12 23:59:16 +00:00
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BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
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2006-06-12 21:50:57 +00:00
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// If the saved register wasn't CR0, shift the bits left so that they are in
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// CR0's slot.
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if (SrcReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
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2006-06-12 23:59:16 +00:00
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// rlwinm r0, r0, ShiftBits, 0, 31.
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BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
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.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
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2006-06-12 21:50:57 +00:00
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}
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2006-06-12 23:59:16 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::GPRCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::F4RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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2006-03-16 22:24:02 +00:00
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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2006-05-04 16:56:45 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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2006-03-16 22:24:02 +00:00
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BuildMI(MBB, MI, PPC::STVX, 3)
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.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
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2004-08-17 04:55:41 +00:00
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} else {
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2005-10-01 01:35:02 +00:00
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assert(0 && "Unknown regclass!");
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abort();
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2004-08-17 04:55:41 +00:00
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}
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}
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void
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2005-10-16 05:39:50 +00:00
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PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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2004-08-17 04:55:41 +00:00
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MachineBasicBlock::iterator MI,
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2005-09-30 01:31:52 +00:00
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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2004-08-17 04:55:41 +00:00
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if (DestReg == PPC::LR) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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2004-08-17 04:55:41 +00:00
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::CRRCRegisterClass) {
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2006-06-12 23:59:16 +00:00
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
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2006-06-12 21:50:57 +00:00
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// If the reloaded register isn't CR0, shift the bits right so that they are
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// in the right CR's slot.
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if (DestReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
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// rlwinm r11, r11, 32-ShiftBits, 0, 31.
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2006-06-12 23:59:16 +00:00
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BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
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.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
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2006-06-12 21:50:57 +00:00
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}
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2006-06-12 23:59:16 +00:00
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BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::GPRCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::F4RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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2006-03-16 22:24:02 +00:00
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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2006-05-04 16:56:45 +00:00
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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2006-03-16 22:24:02 +00:00
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BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
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2004-08-17 04:55:41 +00:00
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} else {
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2005-10-01 01:35:02 +00:00
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assert(0 && "Unknown regclass!");
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abort();
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2004-08-17 04:55:41 +00:00
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}
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}
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2005-10-16 05:39:50 +00:00
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void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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2005-10-18 00:28:58 +00:00
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if (RC == PPC::GPRCRegisterClass) {
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2006-06-20 23:18:58 +00:00
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BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::G8RCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC::F4RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::F8RCRegisterClass) {
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2005-10-01 01:35:02 +00:00
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BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
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2005-10-18 00:28:58 +00:00
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} else if (RC == PPC::CRRCRegisterClass) {
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2005-04-12 07:04:16 +00:00
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BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
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2006-03-16 20:03:58 +00:00
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} else if (RC == PPC::VRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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2005-04-12 07:04:16 +00:00
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} else {
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2004-08-17 04:55:41 +00:00
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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2006-05-18 00:12:58 +00:00
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const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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PPC::R1, PPC::R13,
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PPC::R14, PPC::R15,
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PPC::R16, PPC::R17,
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PPC::R18, PPC::R19,
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PPC::R20, PPC::R21,
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PPC::R22, PPC::R23,
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PPC::R24, PPC::R25,
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PPC::R26, PPC::R27,
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PPC::R28, PPC::R29,
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PPC::R30, PPC::R31,
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PPC::F14, PPC::F15,
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PPC::F16, PPC::F17,
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PPC::F18, PPC::F19,
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PPC::F20, PPC::F21,
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PPC::F22, PPC::F23,
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PPC::F24, PPC::F25,
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|
|
PPC::F26, PPC::F27,
|
|
|
|
PPC::F28, PPC::F29,
|
|
|
|
PPC::F30, PPC::F31,
|
|
|
|
PPC::CR2, PPC::CR3,
|
|
|
|
PPC::CR4, PPC::V20,
|
|
|
|
PPC::V21, PPC::V22,
|
|
|
|
PPC::V23, PPC::V24,
|
|
|
|
PPC::V25, PPC::V26,
|
|
|
|
PPC::V27, PPC::V28,
|
|
|
|
PPC::V29, PPC::V30,
|
|
|
|
PPC::V31, PPC::LR, 0
|
|
|
|
};
|
|
|
|
return CalleeSaveRegs;
|
|
|
|
}
|
|
|
|
|
|
|
|
const TargetRegisterClass* const*
|
|
|
|
PPCRegisterInfo::getCalleeSaveRegClasses() const {
|
|
|
|
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
|
|
|
|
&PPC::CRRCRegClass, &PPC::CRRCRegClass,
|
|
|
|
&PPC::CRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
|
|
|
|
};
|
|
|
|
return CalleeSaveRegClasses;
|
|
|
|
}
|
|
|
|
|
2005-09-09 21:46:49 +00:00
|
|
|
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
|
|
|
|
/// copy instructions, turning them into load/store instructions.
|
2005-10-16 05:39:50 +00:00
|
|
|
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
|
|
|
unsigned OpNum,
|
|
|
|
int FrameIndex) const {
|
2005-09-09 21:46:49 +00:00
|
|
|
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
|
|
|
|
// it takes more than one instruction to store it.
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
|
2006-06-20 23:18:58 +00:00
|
|
|
if ((Opc == PPC::OR &&
|
2005-09-09 21:46:49 +00:00
|
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
|
|
|
if (OpNum == 0) { // move -> store
|
|
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::STW,
|
|
|
|
3).addReg(InReg), FrameIndex);
|
2005-09-09 21:59:44 +00:00
|
|
|
} else { // move -> load
|
2005-09-09 21:46:49 +00:00
|
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
|
|
|
|
}
|
2005-10-18 00:28:58 +00:00
|
|
|
} else if ((Opc == PPC::OR8 &&
|
|
|
|
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
|
|
|
|
if (OpNum == 0) { // move -> store
|
|
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::STD,
|
|
|
|
3).addReg(InReg), FrameIndex);
|
|
|
|
} else { // move -> load
|
|
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
|
|
|
|
}
|
2005-10-01 01:35:02 +00:00
|
|
|
} else if (Opc == PPC::FMRD) {
|
2005-09-09 21:59:44 +00:00
|
|
|
if (OpNum == 0) { // move -> store
|
|
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::STFD,
|
|
|
|
3).addReg(InReg), FrameIndex);
|
|
|
|
} else { // move -> load
|
|
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
|
|
|
|
}
|
2005-10-01 01:35:02 +00:00
|
|
|
} else if (Opc == PPC::FMRS) {
|
|
|
|
if (OpNum == 0) { // move -> store
|
|
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::STFS,
|
|
|
|
3).addReg(InReg), FrameIndex);
|
|
|
|
} else { // move -> load
|
|
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
|
|
return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
|
|
|
|
}
|
2005-09-09 21:46:49 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Stack Frame Processing methods
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// hasFP - Return true if the specified function should have a dedicated frame
|
|
|
|
// pointer register. This is true if the function has variable sized allocas or
|
|
|
|
// if frame pointer elimination is disabled.
|
|
|
|
//
|
2006-04-03 22:03:29 +00:00
|
|
|
static bool hasFP(const MachineFunction &MF) {
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
|
2006-04-11 19:29:21 +00:00
|
|
|
// If frame pointers are forced, or if there are variable sized stack objects,
|
|
|
|
// use a frame pointer.
|
2006-04-03 22:03:29 +00:00
|
|
|
//
|
2006-04-11 19:29:21 +00:00
|
|
|
return NoFramePointerElim || MFI->hasVarSizedObjects();
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
|
2005-10-16 05:39:50 +00:00
|
|
|
void PPCRegisterInfo::
|
2004-08-17 04:55:41 +00:00
|
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const {
|
|
|
|
if (hasFP(MF)) {
|
|
|
|
// If we have a frame pointer, convert as follows:
|
|
|
|
// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
|
|
|
|
// ADJCALLSTACKUP -> addi, r1, r1, amount
|
|
|
|
MachineInstr *Old = I;
|
|
|
|
unsigned Amount = Old->getOperand(0).getImmedValue();
|
|
|
|
if (Amount != 0) {
|
|
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
|
|
// alignment boundary.
|
|
|
|
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
Amount = (Amount+Align-1)/Align*Align;
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
// Replace the pseudo instruction with a new instruction...
|
|
|
|
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
|
2004-08-17 04:55:41 +00:00
|
|
|
} else {
|
|
|
|
assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MBB.erase(I);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2005-10-16 05:39:50 +00:00
|
|
|
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
|
2004-08-17 04:55:41 +00:00
|
|
|
unsigned i = 0;
|
|
|
|
MachineInstr &MI = *II;
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
while (!MI.getOperand(i).isFrameIndex()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
|
|
|
|
int FrameIndex = MI.getOperand(i).getFrameIndex();
|
|
|
|
|
|
|
|
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
2006-05-04 17:52:23 +00:00
|
|
|
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
// Take into account whether it's an add or mem instruction
|
|
|
|
unsigned OffIdx = (i == 2) ? 1 : 2;
|
|
|
|
|
2006-06-27 18:55:49 +00:00
|
|
|
// Figure out if the offset in the instruction is shifted right two bits. This
|
|
|
|
// is true for instructions like "STD", which the machine implicitly adds two
|
|
|
|
// low zeros to.
|
|
|
|
bool isIXAddr = false;
|
|
|
|
switch (MI.getOpcode()) {
|
|
|
|
case PPC::LWA:
|
|
|
|
case PPC::LD:
|
|
|
|
case PPC::STD:
|
|
|
|
case PPC::STD_32:
|
|
|
|
isIXAddr = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
// Now add the frame object offset to the offset from r1.
|
2006-06-27 18:55:49 +00:00
|
|
|
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
|
|
|
|
|
|
|
|
if (!isIXAddr)
|
|
|
|
Offset += MI.getOperand(OffIdx).getImmedValue();
|
|
|
|
else
|
|
|
|
Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
// If we're not using a Frame Pointer that has been set to the value of the
|
|
|
|
// SP before having the stack size subtracted from it, then add the stack size
|
|
|
|
// to Offset to get the correct offset.
|
|
|
|
Offset += MF.getFrameInfo()->getStackSize();
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
if (Offset > 32767 || Offset < -32768) {
|
|
|
|
// Insert a set of r0 with the full offset value before the ld, st, or add
|
|
|
|
MachineBasicBlock *MBB = MI.getParent();
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
|
2006-01-11 23:07:57 +00:00
|
|
|
BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
// convert into indexed form of the instruction
|
|
|
|
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
|
|
|
|
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
|
2005-09-09 20:51:08 +00:00
|
|
|
assert(ImmToIdxMap.count(MI.getOpcode()) &&
|
|
|
|
"No indexed form of load or store available!");
|
|
|
|
unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
|
2004-08-17 04:55:41 +00:00
|
|
|
MI.setOpcode(NewOpcode);
|
2006-05-04 17:52:23 +00:00
|
|
|
MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
|
|
|
|
MI.getOperand(2).ChangeToRegister(PPC::R0);
|
2004-08-17 04:55:41 +00:00
|
|
|
} else {
|
2006-06-27 18:55:49 +00:00
|
|
|
if (isIXAddr) {
|
2005-10-18 16:51:22 +00:00
|
|
|
assert((Offset & 3) == 0 && "Invalid frame offset!");
|
|
|
|
Offset >>= 2; // The actual encoded value has the low two bits zero.
|
|
|
|
}
|
2006-05-04 17:52:23 +00:00
|
|
|
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-17 20:59:25 +00:00
|
|
|
/// VRRegNo - Map from a numbered VR register to its enum value.
|
|
|
|
///
|
|
|
|
static const unsigned short VRRegNo[] = {
|
2006-06-12 21:50:57 +00:00
|
|
|
PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
|
|
|
|
PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
|
2006-04-17 20:59:25 +00:00
|
|
|
PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
|
|
|
|
PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
|
|
|
|
};
|
|
|
|
|
2006-04-17 21:48:13 +00:00
|
|
|
/// RemoveVRSaveCode - We have found that this function does not need any code
|
|
|
|
/// to manipulate the VRSAVE register, even though it uses vector registers.
|
|
|
|
/// This can happen when the only registers used are known to be live in or out
|
|
|
|
/// of the function. Remove all of the VRSAVE related code from the function.
|
|
|
|
static void RemoveVRSaveCode(MachineInstr *MI) {
|
|
|
|
MachineBasicBlock *Entry = MI->getParent();
|
|
|
|
MachineFunction *MF = Entry->getParent();
|
|
|
|
|
|
|
|
// We know that the MTVRSAVE instruction immediately follows MI. Remove it.
|
|
|
|
MachineBasicBlock::iterator MBBI = MI;
|
|
|
|
++MBBI;
|
|
|
|
assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
|
|
|
|
MBBI->eraseFromParent();
|
|
|
|
|
|
|
|
bool RemovedAllMTVRSAVEs = true;
|
|
|
|
// See if we can find and remove the MTVRSAVE instruction from all of the
|
|
|
|
// epilog blocks.
|
|
|
|
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
|
|
|
|
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
|
|
|
|
// If last instruction is a return instruction, add an epilogue
|
|
|
|
if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
|
|
|
|
bool FoundIt = false;
|
|
|
|
for (MBBI = I->end(); MBBI != I->begin(); ) {
|
|
|
|
--MBBI;
|
|
|
|
if (MBBI->getOpcode() == PPC::MTVRSAVE) {
|
|
|
|
MBBI->eraseFromParent(); // remove it.
|
|
|
|
FoundIt = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
RemovedAllMTVRSAVEs &= FoundIt;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we found and removed all MTVRSAVE instructions, remove the read of
|
|
|
|
// VRSAVE as well.
|
|
|
|
if (RemovedAllMTVRSAVEs) {
|
|
|
|
MBBI = MI;
|
|
|
|
assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
|
|
|
|
--MBBI;
|
|
|
|
assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
|
|
|
|
MBBI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, nuke the UPDATE_VRSAVE.
|
|
|
|
MI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
|
|
|
|
// instruction selector. Based on the vector registers that have been used,
|
|
|
|
// transform this into the appropriate ORI instruction.
|
|
|
|
static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
|
|
|
|
unsigned UsedRegMask = 0;
|
2006-04-17 20:59:25 +00:00
|
|
|
for (unsigned i = 0; i != 32; ++i)
|
|
|
|
if (UsedRegs[VRRegNo[i]])
|
|
|
|
UsedRegMask |= 1 << (31-i);
|
|
|
|
|
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27772 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-17 21:22:06 +00:00
|
|
|
// Live in and live out values already must be in the mask, so don't bother
|
|
|
|
// marking them.
|
|
|
|
MachineFunction *MF = MI->getParent()->getParent();
|
|
|
|
for (MachineFunction::livein_iterator I =
|
|
|
|
MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
|
|
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
|
|
|
|
if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
|
|
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
|
|
}
|
|
|
|
for (MachineFunction::liveout_iterator I =
|
|
|
|
MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
|
|
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
|
|
|
|
if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
|
|
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
|
|
}
|
|
|
|
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
// If no registers are used, turn this into a copy.
|
|
|
|
if (UsedRegMask == 0) {
|
2006-04-17 21:48:13 +00:00
|
|
|
// Remove all VRSAVE code.
|
|
|
|
RemoveVRSaveCode(MI);
|
|
|
|
return;
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
} else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
|
|
|
|
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
|
|
|
|
.addReg(SrcReg).addImm(UsedRegMask);
|
|
|
|
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
|
|
|
|
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
|
|
|
|
.addReg(SrcReg).addImm(UsedRegMask >> 16);
|
|
|
|
} else {
|
|
|
|
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
|
|
|
|
.addReg(SrcReg).addImm(UsedRegMask >> 16);
|
|
|
|
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
|
|
|
|
.addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove the old UPDATE_VRSAVE instruction.
|
2006-04-17 21:48:13 +00:00
|
|
|
MI->eraseFromParent();
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
}
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2005-10-16 05:39:50 +00:00
|
|
|
void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
2004-08-17 04:55:41 +00:00
|
|
|
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2006-04-07 16:34:46 +00:00
|
|
|
MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
|
2006-04-03 22:03:29 +00:00
|
|
|
|
|
|
|
// Do we have a frame pointer for this function?
|
|
|
|
bool HasFP = hasFP(MF);
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2006-04-03 22:03:29 +00:00
|
|
|
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
|
|
|
|
// process it.
|
2006-03-16 21:31:45 +00:00
|
|
|
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 21:52:10 +00:00
|
|
|
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
|
|
|
|
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move MBBI back to the beginning of the function.
|
|
|
|
MBBI = MBB.begin();
|
|
|
|
|
2004-08-17 04:55:41 +00:00
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
|
|
unsigned NumBytes = MFI->getStackSize();
|
2005-11-06 09:00:38 +00:00
|
|
|
|
|
|
|
// Get the alignments provided by the target, and the maximum alignment
|
|
|
|
// (if any) of the fixed frame objects.
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
// If we have calls, we cannot use the red zone to store callee save registers
|
|
|
|
// and we must set up a stack frame, so calculate the necessary size here.
|
|
|
|
if (MFI->hasCalls()) {
|
2005-04-21 23:30:14 +00:00
|
|
|
// We reserve argument space for call sites in the function immediately on
|
|
|
|
// entry to the current function. This eliminates the need for add/sub
|
2004-08-17 04:55:41 +00:00
|
|
|
// brackets around call sites.
|
|
|
|
NumBytes += MFI->getMaxCallFrameSize();
|
|
|
|
}
|
|
|
|
|
2005-07-30 18:33:25 +00:00
|
|
|
// If we are a leaf function, and use up to 224 bytes of stack space,
|
2005-07-27 06:06:29 +00:00
|
|
|
// and don't have a frame pointer, then we do not need to adjust the stack
|
|
|
|
// pointer (we fit in the Red Zone).
|
2006-04-03 22:03:29 +00:00
|
|
|
if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
|
2005-11-06 09:00:38 +00:00
|
|
|
MaxAlign <= TargetAlign)) {
|
2005-07-27 06:06:29 +00:00
|
|
|
MFI->setStackSize(0);
|
|
|
|
return;
|
|
|
|
}
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2005-04-21 23:30:14 +00:00
|
|
|
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
|
2004-08-17 04:55:41 +00:00
|
|
|
// of the stack and round the size to a multiple of the alignment.
|
2005-11-06 09:00:38 +00:00
|
|
|
unsigned Align = std::max(TargetAlign, MaxAlign);
|
2005-09-30 17:16:59 +00:00
|
|
|
unsigned GPRSize = 4;
|
2006-04-03 22:03:29 +00:00
|
|
|
unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
|
2004-08-17 04:55:41 +00:00
|
|
|
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
|
|
|
|
|
|
|
|
// Update frame info to pretend that this is part of the stack...
|
|
|
|
MFI->setStackSize(NumBytes);
|
2006-04-07 16:34:46 +00:00
|
|
|
int NegNumbytes = -NumBytes;
|
2004-08-17 04:55:41 +00:00
|
|
|
|
2005-07-27 23:11:27 +00:00
|
|
|
// Adjust stack pointer: r1 -= numbytes.
|
2006-04-11 19:29:21 +00:00
|
|
|
// If there is a preferred stack alignment, align R1 now
|
|
|
|
if (MaxAlign > TargetAlign) {
|
|
|
|
assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
|
2006-05-10 06:38:32 +00:00
|
|
|
assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
|
2006-04-11 19:29:21 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
|
|
|
|
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
|
2006-04-11 19:44:43 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
|
2006-05-10 06:38:32 +00:00
|
|
|
.addImm(0-NumBytes);
|
2006-04-11 19:29:21 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::STWUX, 3)
|
|
|
|
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
|
|
|
|
} else if (NumBytes <= 32768) {
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
|
2006-04-11 19:29:21 +00:00
|
|
|
.addReg(PPC::R1);
|
2004-08-17 04:55:41 +00:00
|
|
|
} else {
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
|
2006-04-11 19:29:21 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
|
|
|
|
.addImm(NegNumbytes & 0xFFFF);
|
|
|
|
BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
|
|
|
|
.addReg(PPC::R0);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
2005-11-06 09:00:38 +00:00
|
|
|
|
2006-04-11 08:11:53 +00:00
|
|
|
if (DebugInfo && DebugInfo->hasInfo()) {
|
2006-04-07 16:34:46 +00:00
|
|
|
std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
|
|
|
|
unsigned LabelID = DebugInfo->NextLabelID();
|
|
|
|
|
|
|
|
// Show update of SP.
|
|
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
|
|
MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
|
|
|
|
Moves.push_back(new MachineMove(LabelID, Dst, Src));
|
|
|
|
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
|
2006-04-07 16:34:46 +00:00
|
|
|
}
|
|
|
|
|
2005-11-06 09:00:38 +00:00
|
|
|
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
|
2006-04-03 22:03:29 +00:00
|
|
|
if (HasFP) {
|
2006-01-11 23:07:57 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::STW, 3)
|
2006-05-04 17:21:20 +00:00
|
|
|
.addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
|
2006-06-20 23:18:58 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-10-16 05:39:50 +00:00
|
|
|
void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB) const {
|
2004-08-17 04:55:41 +00:00
|
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
2006-01-09 18:28:21 +00:00
|
|
|
assert(MBBI->getOpcode() == PPC::BLR &&
|
2004-08-17 04:55:41 +00:00
|
|
|
"Can only insert epilog into returning blocks");
|
2005-04-21 23:30:14 +00:00
|
|
|
|
2006-04-11 19:29:21 +00:00
|
|
|
// Get alignment info so we know how to restore r1
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
|
2006-01-11 23:03:54 +00:00
|
|
|
// Get the number of bytes allocated from the FrameInfo.
|
2006-04-11 19:29:21 +00:00
|
|
|
unsigned NumBytes = MFI->getStackSize();
|
2006-01-11 23:03:54 +00:00
|
|
|
unsigned GPRSize = 4;
|
2004-08-17 04:55:41 +00:00
|
|
|
|
|
|
|
if (NumBytes != 0) {
|
2006-01-11 23:03:54 +00:00
|
|
|
// If this function has a frame pointer, load the saved stack pointer from
|
|
|
|
// its stack slot.
|
2004-08-17 04:55:41 +00:00
|
|
|
if (hasFP(MF)) {
|
2006-01-11 23:03:54 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
|
2006-05-04 17:21:20 +00:00
|
|
|
.addImm(GPRSize).addReg(PPC::R31);
|
2006-01-11 23:03:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
|
|
|
|
// on entry to the function. Add this offset back now.
|
2006-04-11 19:29:21 +00:00
|
|
|
if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
|
2006-01-11 23:03:54 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
|
2006-05-04 17:21:20 +00:00
|
|
|
.addReg(PPC::R1).addImm(NumBytes);
|
2006-01-11 23:03:54 +00:00
|
|
|
} else {
|
2006-05-04 17:21:20 +00:00
|
|
|
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
|
2004-08-17 04:55:41 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-07 16:34:46 +00:00
|
|
|
unsigned PPCRegisterInfo::getRARegister() const {
|
|
|
|
return PPC::LR;
|
|
|
|
}
|
|
|
|
|
2006-03-28 13:48:33 +00:00
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
2006-04-07 16:34:46 +00:00
|
|
|
return hasFP(MF) ? PPC::R31 : PPC::R1;
|
|
|
|
}
|
|
|
|
|
|
|
|
void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
|
|
|
|
const {
|
|
|
|
// Initial state is the frame pointer is R1.
|
|
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
|
|
MachineLocation Src(PPC::R1, 0);
|
|
|
|
Moves.push_back(new MachineMove(0, Dst, Src));
|
2006-03-23 18:12:57 +00:00
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}
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2005-10-14 23:37:35 +00:00
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#include "PPCGenRegisterInfo.inc"
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2004-08-17 04:55:41 +00:00
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