2005-01-07 07:47:53 +00:00
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//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
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2005-04-21 22:36:52 +00:00
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//
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2005-01-07 07:47:53 +00:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 22:36:52 +00:00
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//
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2005-01-07 07:47:53 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This implements the SelectionDAGISel class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2006-01-21 02:32:06 +00:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2005-05-13 18:50:42 +00:00
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#include "llvm/CallingConv.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2005-11-29 06:21:05 +00:00
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#include "llvm/GlobalVariable.h"
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2006-01-26 22:24:51 +00:00
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#include "llvm/InlineAsm.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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2005-11-16 07:22:30 +00:00
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#include "llvm/CodeGen/IntrinsicLowering.h"
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2006-01-04 22:28:25 +00:00
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#include "llvm/CodeGen/MachineDebugInfo.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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2005-09-13 19:30:54 +00:00
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#include "llvm/Target/MRegisterInfo.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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2005-08-17 06:37:43 +00:00
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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2005-01-12 03:41:21 +00:00
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#include "llvm/Support/CommandLine.h"
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2005-11-09 04:45:33 +00:00
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#include "llvm/Support/MathExtras.h"
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2005-01-07 07:47:53 +00:00
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#include "llvm/Support/Debug.h"
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#include <map>
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Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
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#include <set>
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2005-01-07 07:47:53 +00:00
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#include <iostream>
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2006-02-24 02:52:40 +00:00
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#include <algorithm>
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2005-01-07 07:47:53 +00:00
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using namespace llvm;
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2005-09-01 18:44:10 +00:00
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#ifndef NDEBUG
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2005-01-12 03:41:21 +00:00
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static cl::opt<bool>
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2006-01-21 02:32:06 +00:00
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ViewISelDAGs("view-isel-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags as they are selected"));
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static cl::opt<bool>
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ViewSchedDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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2005-01-12 03:41:21 +00:00
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#else
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2006-01-21 02:32:06 +00:00
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static const bool ViewISelDAGs = 0;
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static const bool ViewSchedDAGs = 0;
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2005-01-12 03:41:21 +00:00
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#endif
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2006-03-10 07:49:12 +00:00
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// Scheduling heuristics
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enum SchedHeuristics {
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defaultScheduling, // Let the target specify its preference.
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noScheduling, // No scheduling, emit breadth first sequence.
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simpleScheduling, // Two pass, min. critical path, max. utilization.
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simpleNoItinScheduling, // Same as above exact using generic latency.
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listSchedulingBURR, // Bottom up reg reduction list scheduling.
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listSchedulingTD // Top-down list scheduler.
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};
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2006-01-23 07:01:07 +00:00
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namespace {
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cl::opt<SchedHeuristics>
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ISHeuristic(
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"sched",
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cl::desc("Choose scheduling style"),
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2006-01-25 09:12:57 +00:00
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cl::init(defaultScheduling),
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2006-01-23 07:01:07 +00:00
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cl::values(
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2006-01-25 09:12:57 +00:00
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clEnumValN(defaultScheduling, "default",
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"Target preferred scheduling style"),
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2006-01-23 07:01:07 +00:00
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clEnumValN(noScheduling, "none",
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2006-01-23 13:34:04 +00:00
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"No scheduling: breadth first sequencing"),
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2006-01-23 07:01:07 +00:00
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clEnumValN(simpleScheduling, "simple",
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"Simple two pass scheduling: minimize critical path "
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"and maximize processor utilization"),
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clEnumValN(simpleNoItinScheduling, "simple-noitin",
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"Simple two pass scheduling: Same as simple "
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"except using generic latency"),
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2006-01-25 09:12:57 +00:00
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clEnumValN(listSchedulingBURR, "list-burr",
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2006-01-23 08:26:10 +00:00
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"Bottom up register reduction list scheduling"),
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2006-03-06 00:22:00 +00:00
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clEnumValN(listSchedulingTD, "list-td",
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"Top-down list scheduler"),
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2006-01-23 07:01:07 +00:00
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clEnumValEnd));
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} // namespace
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2006-02-22 22:37:12 +00:00
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namespace {
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/// RegsForValue - This struct represents the physical registers that a
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/// particular value is assigned and the type information about the value.
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/// This is needed because values can be promoted into larger registers and
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/// expanded into multiple smaller registers than the value.
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struct RegsForValue {
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/// Regs - This list hold the register (for legal and promoted values)
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/// or register set (for expanded values) that the value should be assigned
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/// to.
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std::vector<unsigned> Regs;
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/// RegVT - The value type of each register.
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///
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MVT::ValueType RegVT;
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/// ValueVT - The value type of the LLVM value, which may be promoted from
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/// RegVT or made from merging the two expanded parts.
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MVT::ValueType ValueVT;
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RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
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RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
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: RegVT(regvt), ValueVT(valuevt) {
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Regs.push_back(Reg);
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}
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RegsForValue(const std::vector<unsigned> ®s,
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MVT::ValueType regvt, MVT::ValueType valuevt)
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: Regs(regs), RegVT(regvt), ValueVT(valuevt) {
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}
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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/// this value and returns the result as a ValueVT value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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SDOperand getCopyFromRegs(SelectionDAG &DAG,
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2006-02-23 20:06:57 +00:00
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SDOperand &Chain, SDOperand &Flag) const;
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2006-02-23 19:21:04 +00:00
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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2006-02-23 20:06:57 +00:00
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SDOperand &Chain, SDOperand &Flag) const;
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2006-02-23 19:21:04 +00:00
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker and includes the number of
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/// values added into it.
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void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
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2006-02-23 20:06:57 +00:00
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std::vector<SDOperand> &Ops) const;
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2006-02-22 22:37:12 +00:00
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};
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}
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2006-01-23 07:01:07 +00:00
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2005-01-07 07:47:53 +00:00
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namespace llvm {
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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2005-01-08 19:52:31 +00:00
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class FunctionLoweringInfo {
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public:
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2005-01-07 07:47:53 +00:00
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TargetLowering &TLI;
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Function &Fn;
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MachineFunction &MF;
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SSARegMap *RegMap;
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FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
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/// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
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std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
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/// ValueMap - Since we emit code for the function a basic block at a time,
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/// we must remember which virtual registers hold the values for
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/// cross-basic-block values.
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std::map<const Value*, unsigned> ValueMap;
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/// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
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/// the entry block. This allows the allocas to be efficiently referenced
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/// anywhere in the function.
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std::map<const AllocaInst*, int> StaticAllocaMap;
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unsigned MakeReg(MVT::ValueType VT) {
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return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
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}
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2005-04-21 22:36:52 +00:00
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2006-03-16 19:51:18 +00:00
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unsigned CreateRegForValue(const Value *V);
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2005-01-07 07:47:53 +00:00
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unsigned InitializeRegForValue(const Value *V) {
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unsigned &R = ValueMap[V];
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assert(R == 0 && "Already initialized this value register!");
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return R = CreateRegForValue(V);
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}
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};
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}
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/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
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/// PHI nodes or outside of the basic block that defines it.
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static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
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if (isa<PHINode>(I)) return true;
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BasicBlock *BB = I->getParent();
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for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
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if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
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return true;
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return false;
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}
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Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
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/// entry block, return true.
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static bool isOnlyUsedInEntryBlock(Argument *A) {
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BasicBlock *Entry = A->getParent()->begin();
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for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
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if (cast<Instruction>(*UI)->getParent() != Entry)
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return false; // Use not in entry block.
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return true;
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}
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2005-01-07 07:47:53 +00:00
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FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
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2005-04-21 22:36:52 +00:00
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Function &fn, MachineFunction &mf)
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2005-01-07 07:47:53 +00:00
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: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
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|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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// Create a vreg for each argument register that is not dead and is used
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// outside of the entry block for the function.
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2005-05-11 18:57:06 +00:00
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for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
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AI != E; ++AI)
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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if (!isOnlyUsedInEntryBlock(AI))
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InitializeRegForValue(AI);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
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// Initialize the mapping of values to registers. This is only set up for
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// instruction values that are used outside of the block that defines
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// them.
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2005-10-01 03:57:14 +00:00
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Function::iterator BB = Fn.begin(), EB = Fn.end();
|
2005-01-07 07:47:53 +00:00
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
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if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
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if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
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const Type *Ty = AI->getAllocatedType();
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uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
|
2005-11-06 09:00:38 +00:00
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unsigned Align =
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|
|
std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
|
|
|
|
AI->getAlignment());
|
2005-05-13 23:14:17 +00:00
|
|
|
|
|
|
|
// If the alignment of the value is smaller than the size of the value,
|
|
|
|
// and if the size of the value is particularly small (<= 8 bytes),
|
|
|
|
// round up to the size of the value for potentially better performance.
|
|
|
|
//
|
|
|
|
// FIXME: This could be made better with a preferred alignment hook in
|
|
|
|
// TargetData. It serves primarily to 8-byte align doubles for X86.
|
|
|
|
if (Align < TySize && TySize <= 8) Align = TySize;
|
2005-10-18 22:11:42 +00:00
|
|
|
TySize *= CUI->getValue(); // Get total allocated size.
|
2005-10-18 22:14:06 +00:00
|
|
|
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
|
2005-01-07 07:47:53 +00:00
|
|
|
StaticAllocaMap[AI] =
|
2005-01-08 19:52:31 +00:00
|
|
|
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-10-01 03:57:14 +00:00
|
|
|
for (; BB != EB; ++BB)
|
|
|
|
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
|
2005-01-07 07:47:53 +00:00
|
|
|
if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
|
|
|
|
if (!isa<AllocaInst>(I) ||
|
|
|
|
!StaticAllocaMap.count(cast<AllocaInst>(I)))
|
|
|
|
InitializeRegForValue(I);
|
|
|
|
|
|
|
|
// Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
|
|
|
|
// also creates the initial PHI MachineInstrs, though none of the input
|
|
|
|
// operands are populated.
|
2005-10-01 03:57:14 +00:00
|
|
|
for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
|
2005-01-07 07:47:53 +00:00
|
|
|
MachineBasicBlock *MBB = new MachineBasicBlock(BB);
|
|
|
|
MBBMap[BB] = MBB;
|
|
|
|
MF.getBasicBlockList().push_back(MBB);
|
|
|
|
|
|
|
|
// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
|
|
|
|
// appropriate.
|
|
|
|
PHINode *PN;
|
|
|
|
for (BasicBlock::iterator I = BB->begin();
|
2005-01-07 21:34:19 +00:00
|
|
|
(PN = dyn_cast<PHINode>(I)); ++I)
|
|
|
|
if (!PN->use_empty()) {
|
|
|
|
unsigned NumElements =
|
|
|
|
TLI.getNumElements(TLI.getValueType(PN->getType()));
|
|
|
|
unsigned PHIReg = ValueMap[PN];
|
|
|
|
assert(PHIReg &&"PHI node does not have an assigned virtual register!");
|
|
|
|
for (unsigned i = 0; i != NumElements; ++i)
|
|
|
|
BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-16 19:51:18 +00:00
|
|
|
/// CreateRegForValue - Allocate the appropriate number of virtual registers of
|
|
|
|
/// the correctly promoted or expanded types. Assign these registers
|
|
|
|
/// consecutive vreg numbers and return the first assigned number.
|
|
|
|
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
|
|
|
|
MVT::ValueType VT = TLI.getValueType(V->getType());
|
|
|
|
|
|
|
|
// The number of multiples of registers that we need, to, e.g., split up
|
|
|
|
// a <2 x int64> -> 4 x i32 registers.
|
|
|
|
unsigned NumVectorRegs = 1;
|
|
|
|
|
|
|
|
// If this is a packed type, figure out what type it will decompose into
|
|
|
|
// and how many of the elements it will use.
|
|
|
|
if (VT == MVT::Vector) {
|
|
|
|
const PackedType *PTy = cast<PackedType>(V->getType());
|
|
|
|
unsigned NumElts = PTy->getNumElements();
|
|
|
|
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
|
|
|
// Divide the input until we get to a supported size. This will always
|
|
|
|
// end with a scalar if the target doesn't support vectors.
|
|
|
|
while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
|
|
|
|
NumElts >>= 1;
|
|
|
|
NumVectorRegs <<= 1;
|
|
|
|
}
|
2006-03-16 23:05:19 +00:00
|
|
|
if (NumElts == 1)
|
|
|
|
VT = EltTy;
|
|
|
|
else
|
|
|
|
VT = getVectorType(EltTy, NumElts);
|
2006-03-16 19:51:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// The common case is that we will only create one register for this
|
|
|
|
// value. If we have that case, create and return the virtual register.
|
|
|
|
unsigned NV = TLI.getNumElements(VT);
|
|
|
|
if (NV == 1) {
|
|
|
|
// If we are promoting this value, pick the next largest supported type.
|
|
|
|
MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
|
|
|
|
unsigned Reg = MakeReg(PromotedType);
|
|
|
|
// If this is a vector of supported or promoted types (e.g. 4 x i16),
|
|
|
|
// create all of the registers.
|
|
|
|
for (unsigned i = 1; i != NumVectorRegs; ++i)
|
|
|
|
MakeReg(PromotedType);
|
|
|
|
return Reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If this value is represented with multiple target registers, make sure
|
|
|
|
// to create enough consecutive registers of the right (smaller) type.
|
|
|
|
unsigned NT = VT-1; // Find the type to use.
|
|
|
|
while (TLI.getNumElements((MVT::ValueType)NT) != 1)
|
|
|
|
--NT;
|
|
|
|
|
|
|
|
unsigned R = MakeReg((MVT::ValueType)NT);
|
|
|
|
for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
|
|
|
|
MakeReg((MVT::ValueType)NT);
|
|
|
|
return R;
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SelectionDAGLowering - This is the common target-independent lowering
|
|
|
|
/// implementation that is parameterized by a TargetLowering object.
|
|
|
|
/// Also, targets can overload any lowering method.
|
|
|
|
///
|
|
|
|
namespace llvm {
|
|
|
|
class SelectionDAGLowering {
|
|
|
|
MachineBasicBlock *CurMBB;
|
|
|
|
|
|
|
|
std::map<const Value*, SDOperand> NodeMap;
|
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
/// PendingLoads - Loads are not emitted to the program immediately. We bunch
|
|
|
|
/// them up and then emit token factor nodes when possible. This allows us to
|
|
|
|
/// get simple disambiguation between loads without worrying about alias
|
|
|
|
/// analysis.
|
|
|
|
std::vector<SDOperand> PendingLoads;
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
public:
|
|
|
|
// TLI - This is information that describes the available target features we
|
|
|
|
// need for lowering. This indicates when operations are unavailable,
|
|
|
|
// implemented with a libcall, etc.
|
|
|
|
TargetLowering &TLI;
|
|
|
|
SelectionDAG &DAG;
|
|
|
|
const TargetData &TD;
|
|
|
|
|
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
|
|
///
|
|
|
|
FunctionLoweringInfo &FuncInfo;
|
|
|
|
|
|
|
|
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
|
2005-04-21 22:36:52 +00:00
|
|
|
FunctionLoweringInfo &funcinfo)
|
2005-01-07 07:47:53 +00:00
|
|
|
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
|
|
|
|
FuncInfo(funcinfo) {
|
|
|
|
}
|
|
|
|
|
2005-01-17 19:43:36 +00:00
|
|
|
/// getRoot - Return the current virtual root of the Selection DAG.
|
|
|
|
///
|
|
|
|
SDOperand getRoot() {
|
2005-01-17 22:19:26 +00:00
|
|
|
if (PendingLoads.empty())
|
|
|
|
return DAG.getRoot();
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
if (PendingLoads.size() == 1) {
|
|
|
|
SDOperand Root = PendingLoads[0];
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
PendingLoads.clear();
|
|
|
|
return Root;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we have to make a token factor node.
|
|
|
|
SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
|
|
|
|
PendingLoads.clear();
|
|
|
|
DAG.setRoot(Root);
|
|
|
|
return Root;
|
2005-01-17 19:43:36 +00:00
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void visit(Instruction &I) { visit(I.getOpcode(), I); }
|
|
|
|
|
|
|
|
void visit(unsigned Opcode, User &I) {
|
|
|
|
switch (Opcode) {
|
|
|
|
default: assert(0 && "Unknown instruction type encountered!");
|
|
|
|
abort();
|
|
|
|
// Build the switch statement using the Instruction.def file.
|
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
|
|
|
case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
|
|
|
|
#include "llvm/Instruction.def"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
|
|
|
|
|
2006-03-15 22:19:46 +00:00
|
|
|
SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
|
|
|
|
SDOperand SrcValue, SDOperand Root,
|
|
|
|
bool isVolatile);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
SDOperand getIntPtrConstant(uint64_t Val) {
|
|
|
|
return DAG.getConstant(Val, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
2006-03-16 19:57:50 +00:00
|
|
|
SDOperand getValue(const Value *V);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
const SDOperand &setValue(const Value *V, SDOperand NewN) {
|
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
assert(N.Val == 0 && "Already set a value for this node!");
|
|
|
|
return N = NewN;
|
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue GetRegistersForValue(const std::string &ConstrCode,
|
|
|
|
MVT::ValueType VT,
|
|
|
|
bool OutReg, bool InReg,
|
|
|
|
std::set<unsigned> &OutputRegs,
|
|
|
|
std::set<unsigned> &InputRegs);
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Terminator instructions.
|
|
|
|
void visitRet(ReturnInst &I);
|
|
|
|
void visitBr(BranchInst &I);
|
|
|
|
void visitUnreachable(UnreachableInst &I) { /* noop */ }
|
|
|
|
|
|
|
|
// These all get lowered before this pass.
|
|
|
|
void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
|
|
|
|
void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
|
|
|
|
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
|
|
|
|
|
|
|
|
//
|
2005-11-19 00:36:38 +00:00
|
|
|
void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
|
2005-11-18 07:42:56 +00:00
|
|
|
void visitShift(User &I, unsigned Opcode);
|
2005-11-19 00:36:38 +00:00
|
|
|
void visitAdd(User &I) {
|
|
|
|
visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
|
2005-09-28 22:28:18 +00:00
|
|
|
}
|
2005-04-02 05:04:50 +00:00
|
|
|
void visitSub(User &I);
|
2005-11-19 00:36:38 +00:00
|
|
|
void visitMul(User &I) {
|
|
|
|
visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
|
2005-09-28 22:28:18 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
void visitDiv(User &I) {
|
2005-09-28 22:28:18 +00:00
|
|
|
const Type *Ty = I.getType();
|
2006-03-03 07:01:07 +00:00
|
|
|
visitBinary(I,
|
|
|
|
Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
|
|
|
|
Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
void visitRem(User &I) {
|
2005-09-28 22:28:18 +00:00
|
|
|
const Type *Ty = I.getType();
|
2005-11-19 00:36:38 +00:00
|
|
|
visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-03-03 07:01:07 +00:00
|
|
|
void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
|
|
|
|
void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
|
|
|
|
void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
|
2005-11-18 07:42:56 +00:00
|
|
|
void visitShl(User &I) { visitShift(I, ISD::SHL); }
|
|
|
|
void visitShr(User &I) {
|
|
|
|
visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
|
|
|
|
void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
|
|
|
|
void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
|
|
|
|
void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
|
|
|
|
void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
|
|
|
|
void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
|
|
|
|
void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
|
|
|
|
|
2006-03-18 01:44:44 +00:00
|
|
|
void visitExtractElement(ExtractElementInst &I) { assert(0 && "TODO"); }
|
|
|
|
void visitInsertElement(InsertElementInst &I);
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void visitGetElementPtr(User &I);
|
|
|
|
void visitCast(User &I);
|
|
|
|
void visitSelect(User &I);
|
|
|
|
//
|
|
|
|
|
|
|
|
void visitMalloc(MallocInst &I);
|
|
|
|
void visitFree(FreeInst &I);
|
|
|
|
void visitAlloca(AllocaInst &I);
|
|
|
|
void visitLoad(LoadInst &I);
|
|
|
|
void visitStore(StoreInst &I);
|
|
|
|
void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
|
|
|
|
void visitCall(CallInst &I);
|
2006-01-26 22:24:51 +00:00
|
|
|
void visitInlineAsm(CallInst &I);
|
2005-11-09 19:44:01 +00:00
|
|
|
const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
void visitVAStart(CallInst &I);
|
|
|
|
void visitVAArg(VAArgInst &I);
|
|
|
|
void visitVAEnd(CallInst &I);
|
|
|
|
void visitVACopy(CallInst &I);
|
2005-01-09 00:00:49 +00:00
|
|
|
void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
void visitMemIntrinsic(CallInst &I, unsigned Op);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
void visitUserOp1(Instruction &I) {
|
|
|
|
assert(0 && "UserOp1 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
void visitUserOp2(Instruction &I) {
|
|
|
|
assert(0 && "UserOp2 should not exist at instruction selection time!");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
|
2006-03-16 19:57:50 +00:00
|
|
|
SDOperand SelectionDAGLowering::getValue(const Value *V) {
|
|
|
|
SDOperand &N = NodeMap[V];
|
|
|
|
if (N.Val) return N;
|
|
|
|
|
|
|
|
const Type *VTy = V->getType();
|
|
|
|
MVT::ValueType VT = TLI.getValueType(VTy);
|
|
|
|
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
|
|
|
|
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
|
|
|
|
visit(CE->getOpcode(), *CE);
|
|
|
|
assert(N.Val && "visit didn't populate the ValueMap!");
|
|
|
|
return N;
|
|
|
|
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
|
|
|
|
return N = DAG.getGlobalAddress(GV, VT);
|
|
|
|
} else if (isa<ConstantPointerNull>(C)) {
|
|
|
|
return N = DAG.getConstant(0, TLI.getPointerTy());
|
|
|
|
} else if (isa<UndefValue>(C)) {
|
2006-03-19 00:20:20 +00:00
|
|
|
if (!isa<PackedType>(VTy))
|
|
|
|
return N = DAG.getNode(ISD::UNDEF, VT);
|
|
|
|
|
2006-03-19 00:52:58 +00:00
|
|
|
// Create a VBUILD_VECTOR of undef nodes.
|
2006-03-19 00:20:20 +00:00
|
|
|
const PackedType *PTy = cast<PackedType>(VTy);
|
|
|
|
unsigned NumElements = PTy->getNumElements();
|
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
|
|
|
|
|
|
|
|
// Create a VConstant node with generic Vector type.
|
|
|
|
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
|
|
|
|
Ops.push_back(DAG.getValueType(PVT));
|
2006-03-19 00:52:58 +00:00
|
|
|
return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
|
2006-03-16 19:57:50 +00:00
|
|
|
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
|
|
|
|
return N = DAG.getConstantFP(CFP->getValue(), VT);
|
|
|
|
} else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
|
|
|
|
unsigned NumElements = PTy->getNumElements();
|
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
|
|
|
|
// Now that we know the number and type of the elements, push a
|
|
|
|
// Constant or ConstantFP node onto the ops list for each element of
|
|
|
|
// the packed constant.
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
|
|
|
|
if (MVT::isFloatingPoint(PVT)) {
|
|
|
|
for (unsigned i = 0; i != NumElements; ++i) {
|
|
|
|
const ConstantFP *El = cast<ConstantFP>(CP->getOperand(i));
|
|
|
|
Ops.push_back(DAG.getConstantFP(El->getValue(), PVT));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (unsigned i = 0; i != NumElements; ++i) {
|
|
|
|
const ConstantIntegral *El =
|
|
|
|
cast<ConstantIntegral>(CP->getOperand(i));
|
|
|
|
Ops.push_back(DAG.getConstant(El->getRawValue(), PVT));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
|
|
|
|
SDOperand Op;
|
|
|
|
if (MVT::isFloatingPoint(PVT))
|
|
|
|
Op = DAG.getConstantFP(0, PVT);
|
|
|
|
else
|
|
|
|
Op = DAG.getConstant(0, PVT);
|
|
|
|
Ops.assign(NumElements, Op);
|
|
|
|
}
|
|
|
|
|
2006-03-19 00:52:58 +00:00
|
|
|
// Create a VBUILD_VECTOR node with generic Vector type.
|
2006-03-19 00:20:20 +00:00
|
|
|
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
|
|
|
|
Ops.push_back(DAG.getValueType(PVT));
|
2006-03-19 00:52:58 +00:00
|
|
|
return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
|
2006-03-16 19:57:50 +00:00
|
|
|
} else {
|
|
|
|
// Canonicalize all constant ints to be unsigned.
|
|
|
|
return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
|
|
|
|
std::map<const AllocaInst*, int>::iterator SI =
|
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end())
|
|
|
|
return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
|
|
|
|
}
|
|
|
|
|
|
|
|
std::map<const Value*, unsigned>::const_iterator VMI =
|
|
|
|
FuncInfo.ValueMap.find(V);
|
|
|
|
assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
|
|
|
|
|
|
|
|
unsigned InReg = VMI->second;
|
|
|
|
|
|
|
|
// If this type is not legal, make it so now.
|
|
|
|
if (VT == MVT::Vector) {
|
|
|
|
// FIXME: We only handle legal vectors right now. We need a VBUILD_VECTOR
|
|
|
|
const PackedType *PTy = cast<PackedType>(VTy);
|
|
|
|
unsigned NumElements = PTy->getNumElements();
|
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
|
|
|
MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
|
|
|
|
assert(TLI.isTypeLegal(TVT) &&
|
|
|
|
"FIXME: Cannot handle illegal vector types here yet!");
|
|
|
|
VT = TVT;
|
|
|
|
}
|
|
|
|
|
|
|
|
MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
|
|
|
|
|
|
|
|
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
|
|
|
|
if (DestVT < VT) {
|
|
|
|
// Source must be expanded. This input value is actually coming from the
|
|
|
|
// register pair VMI->second and VMI->second+1.
|
|
|
|
N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
|
|
|
|
DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
|
|
|
|
} else {
|
|
|
|
if (DestVT > VT) { // Promotion case
|
|
|
|
if (MVT::isFloatingPoint(VT))
|
|
|
|
N = DAG.getNode(ISD::FP_ROUND, VT, N);
|
|
|
|
else
|
|
|
|
N = DAG.getNode(ISD::TRUNCATE, VT, N);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return N;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitRet(ReturnInst &I) {
|
|
|
|
if (I.getNumOperands() == 0) {
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
|
2005-01-07 07:47:53 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-01-27 21:09:22 +00:00
|
|
|
std::vector<SDOperand> NewValues;
|
|
|
|
NewValues.push_back(getRoot());
|
|
|
|
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
SDOperand RetOp = getValue(I.getOperand(i));
|
|
|
|
|
|
|
|
// If this is an integer return value, we need to promote it ourselves to
|
|
|
|
// the full width of a register, since LegalizeOp will use ANY_EXTEND rather
|
|
|
|
// than sign/zero.
|
|
|
|
if (MVT::isInteger(RetOp.getValueType()) &&
|
|
|
|
RetOp.getValueType() < MVT::i64) {
|
|
|
|
MVT::ValueType TmpVT;
|
|
|
|
if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
|
|
|
|
TmpVT = TLI.getTypeToTransformTo(MVT::i32);
|
|
|
|
else
|
|
|
|
TmpVT = MVT::i32;
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-01-27 21:09:22 +00:00
|
|
|
if (I.getOperand(i)->getType()->isSigned())
|
|
|
|
RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
|
|
|
|
else
|
|
|
|
RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
|
|
|
|
}
|
|
|
|
NewValues.push_back(RetOp);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-01-27 21:09:22 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitBr(BranchInst &I) {
|
|
|
|
// Update machine-CFG edges.
|
|
|
|
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
|
|
|
|
|
|
|
|
// Figure out which block is immediately after the current one.
|
|
|
|
MachineBasicBlock *NextBlock = 0;
|
|
|
|
MachineFunction::iterator BBI = CurMBB;
|
|
|
|
if (++BBI != CurMBB->getParent()->end())
|
|
|
|
NextBlock = BBI;
|
|
|
|
|
|
|
|
if (I.isUnconditional()) {
|
|
|
|
// If this is not a fall-through branch, emit the branch.
|
|
|
|
if (Succ0MBB != NextBlock)
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
|
2005-04-22 04:01:18 +00:00
|
|
|
DAG.getBasicBlock(Succ0MBB)));
|
2005-01-07 07:47:53 +00:00
|
|
|
} else {
|
|
|
|
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
|
|
|
|
|
|
|
|
SDOperand Cond = getValue(I.getCondition());
|
|
|
|
if (Succ1MBB == NextBlock) {
|
|
|
|
// If the condition is false, fall through. This means we should branch
|
|
|
|
// if the condition is true to Succ #0.
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
|
2005-04-22 04:01:18 +00:00
|
|
|
Cond, DAG.getBasicBlock(Succ0MBB)));
|
2005-01-07 07:47:53 +00:00
|
|
|
} else if (Succ0MBB == NextBlock) {
|
|
|
|
// If the condition is true, fall through. This means we should branch if
|
|
|
|
// the condition is false to Succ #1. Invert the condition first.
|
|
|
|
SDOperand True = DAG.getConstant(1, Cond.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
|
2005-01-17 19:43:36 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
|
2005-04-22 04:01:18 +00:00
|
|
|
Cond, DAG.getBasicBlock(Succ1MBB)));
|
2005-01-07 07:47:53 +00:00
|
|
|
} else {
|
2005-04-09 03:30:29 +00:00
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(getRoot());
|
2006-02-16 08:27:56 +00:00
|
|
|
// If the false case is the current basic block, then this is a self
|
|
|
|
// loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
|
|
|
|
// adds an extra instruction in the loop. Instead, invert the
|
|
|
|
// condition and emit "Loop: ... br!cond Loop; br Out.
|
|
|
|
if (CurMBB == Succ1MBB) {
|
|
|
|
std::swap(Succ0MBB, Succ1MBB);
|
|
|
|
SDOperand True = DAG.getConstant(1, Cond.getValueType());
|
|
|
|
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
|
|
|
|
}
|
2006-03-17 01:40:33 +00:00
|
|
|
SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
|
|
|
|
DAG.getBasicBlock(Succ0MBB));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
|
|
|
|
DAG.getBasicBlock(Succ1MBB)));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-04-02 05:04:50 +00:00
|
|
|
void SelectionDAGLowering::visitSub(User &I) {
|
|
|
|
// -0.0 - X --> fneg
|
2005-09-28 22:28:18 +00:00
|
|
|
if (I.getType()->isFloatingPoint()) {
|
|
|
|
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
|
|
|
|
if (CFP->isExactlyValue(-0.0)) {
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2005-11-19 00:36:38 +00:00
|
|
|
visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
|
2005-04-02 05:04:50 +00:00
|
|
|
}
|
|
|
|
|
2005-11-19 00:36:38 +00:00
|
|
|
void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
|
|
|
|
unsigned VecOp) {
|
|
|
|
const Type *Ty = I.getType();
|
2005-01-07 07:47:53 +00:00
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
2005-01-19 22:31:21 +00:00
|
|
|
|
2005-11-19 18:40:42 +00:00
|
|
|
if (Ty->isIntegral()) {
|
2005-11-19 00:36:38 +00:00
|
|
|
setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
|
|
|
|
} else if (Ty->isFloatingPoint()) {
|
|
|
|
setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
|
|
|
|
} else {
|
|
|
|
const PackedType *PTy = cast<PackedType>(Ty);
|
2006-03-18 01:44:44 +00:00
|
|
|
SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
|
|
|
|
SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
|
|
|
|
setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
|
2005-11-19 00:36:38 +00:00
|
|
|
}
|
2005-11-18 07:42:56 +00:00
|
|
|
}
|
2005-01-19 22:31:21 +00:00
|
|
|
|
2005-11-18 07:42:56 +00:00
|
|
|
void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
|
|
|
|
Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
|
|
|
|
ISD::CondCode UnsignedOpcode) {
|
|
|
|
SDOperand Op1 = getValue(I.getOperand(0));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(1));
|
|
|
|
ISD::CondCode Opcode = SignedOpcode;
|
|
|
|
if (I.getOperand(0)->getType()->isUnsigned())
|
|
|
|
Opcode = UnsignedOpcode;
|
2005-08-09 20:20:18 +00:00
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitSelect(User &I) {
|
|
|
|
SDOperand Cond = getValue(I.getOperand(0));
|
|
|
|
SDOperand TrueVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand FalseVal = getValue(I.getOperand(2));
|
|
|
|
setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
|
|
|
|
TrueVal, FalseVal));
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitCast(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
2006-03-15 22:19:46 +00:00
|
|
|
MVT::ValueType SrcVT = TLI.getValueType(I.getOperand(0)->getType());
|
|
|
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-03-15 22:19:46 +00:00
|
|
|
if (N.getValueType() == DestVT) {
|
2005-01-07 07:47:53 +00:00
|
|
|
setValue(&I, N); // noop cast.
|
2006-03-15 22:19:46 +00:00
|
|
|
} else if (DestVT == MVT::i1) {
|
2005-05-09 22:17:13 +00:00
|
|
|
// Cast to bool is a comparison against zero, not truncation to zero.
|
2006-03-15 22:19:46 +00:00
|
|
|
SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
|
2005-05-09 22:17:13 +00:00
|
|
|
DAG.getConstantFP(0.0, N.getValueType());
|
2005-08-09 20:20:18 +00:00
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
|
2006-03-15 22:19:46 +00:00
|
|
|
} else if (isInteger(SrcVT)) {
|
|
|
|
if (isInteger(DestVT)) { // Int -> Int cast
|
|
|
|
if (DestVT < SrcVT) // Truncating cast?
|
|
|
|
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
else if (I.getOperand(0)->getType()->isSigned())
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
else
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
} else { // Int -> FP cast
|
|
|
|
if (I.getOperand(0)->getType()->isSigned())
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
else
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
}
|
2006-03-15 22:19:46 +00:00
|
|
|
} else if (isFloatingPoint(SrcVT)) {
|
|
|
|
if (isFloatingPoint(DestVT)) { // FP -> FP cast
|
|
|
|
if (DestVT < SrcVT) // Rounding cast?
|
|
|
|
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
else
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
} else { // FP -> Int cast.
|
|
|
|
if (I.getType()->isSigned())
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
|
2005-01-08 08:08:56 +00:00
|
|
|
else
|
2006-03-15 22:19:46 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
|
|
|
|
}
|
|
|
|
} else {
|
2006-03-18 01:44:44 +00:00
|
|
|
assert(0 && "Cannot bitconvert vectors yet!");
|
|
|
|
#if 0
|
2006-03-15 22:19:46 +00:00
|
|
|
const PackedType *SrcTy = cast<PackedType>(I.getOperand(0)->getType());
|
|
|
|
const PackedType *DstTy = cast<PackedType>(I.getType());
|
|
|
|
|
|
|
|
unsigned SrcNumElements = SrcTy->getNumElements();
|
|
|
|
MVT::ValueType SrcPVT = TLI.getValueType(SrcTy->getElementType());
|
|
|
|
MVT::ValueType SrcTVT = MVT::getVectorType(SrcPVT, SrcNumElements);
|
|
|
|
|
|
|
|
unsigned DstNumElements = DstTy->getNumElements();
|
|
|
|
MVT::ValueType DstPVT = TLI.getValueType(DstTy->getElementType());
|
|
|
|
MVT::ValueType DstTVT = MVT::getVectorType(DstPVT, DstNumElements);
|
|
|
|
|
|
|
|
// If the input and output type are legal, convert this to a bit convert of
|
|
|
|
// the SrcTVT/DstTVT types.
|
|
|
|
if (SrcTVT != MVT::Other && DstTVT != MVT::Other &&
|
|
|
|
TLI.isTypeLegal(SrcTVT) && TLI.isTypeLegal(DstTVT)) {
|
|
|
|
assert(N.getValueType() == SrcTVT);
|
|
|
|
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DstTVT, N));
|
|
|
|
} else {
|
|
|
|
// Otherwise, convert this directly into a store/load.
|
|
|
|
// FIXME: add a VBIT_CONVERT node that we could use to automatically turn
|
|
|
|
// 8xFloat -> 8xInt casts into two 4xFloat -> 4xInt casts.
|
|
|
|
// Create the stack frame object.
|
|
|
|
uint64_t ByteSize = TD.getTypeSize(SrcTy);
|
|
|
|
assert(ByteSize == TD.getTypeSize(DstTy) && "Not a bit_convert!");
|
|
|
|
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
|
|
|
|
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
|
|
|
|
|
|
|
|
// Emit a store to the stack slot.
|
|
|
|
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
|
|
|
|
N, FIPtr, DAG.getSrcValue(NULL));
|
|
|
|
// Result is a load from the stack slot.
|
|
|
|
SDOperand Val =
|
|
|
|
getLoadFrom(DstTy, FIPtr, DAG.getSrcValue(NULL), Store, false);
|
|
|
|
setValue(&I, Val);
|
2005-01-08 08:08:56 +00:00
|
|
|
}
|
2006-03-18 01:44:44 +00:00
|
|
|
#endif
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-18 01:44:44 +00:00
|
|
|
void SelectionDAGLowering::visitInsertElement(InsertElementInst &I) {
|
|
|
|
SDOperand InVec = getValue(I.getOperand(0));
|
|
|
|
SDOperand InVal = getValue(I.getOperand(1));
|
|
|
|
SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
|
|
|
|
getValue(I.getOperand(2)));
|
|
|
|
|
2006-03-19 01:17:20 +00:00
|
|
|
SDOperand Num = *(InVec.Val->op_end()-2);
|
|
|
|
SDOperand Typ = *(InVec.Val->op_end()-1);
|
|
|
|
setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
|
|
|
|
InVec, InVal, InIdx, Num, Typ));
|
2006-03-18 01:44:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
|
|
|
SDOperand N = getValue(I.getOperand(0));
|
|
|
|
const Type *Ty = I.getOperand(0)->getType();
|
|
|
|
const Type *UIntPtrTy = TD.getIntPtrType();
|
|
|
|
|
|
|
|
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
|
|
|
|
OI != E; ++OI) {
|
|
|
|
Value *Idx = *OI;
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
|
2005-01-07 07:47:53 +00:00
|
|
|
unsigned Field = cast<ConstantUInt>(Idx)->getValue();
|
|
|
|
if (Field) {
|
|
|
|
// N = N + Offset
|
|
|
|
uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
|
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
2005-04-22 04:01:18 +00:00
|
|
|
getIntPtrConstant(Offset));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
Ty = StTy->getElementType(Field);
|
|
|
|
} else {
|
|
|
|
Ty = cast<SequentialType>(Ty)->getElementType();
|
2005-11-09 04:45:33 +00:00
|
|
|
|
|
|
|
// If this is a constant subscript, handle it quickly.
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
|
|
|
|
if (CI->getRawValue() == 0) continue;
|
|
|
|
|
|
|
|
uint64_t Offs;
|
|
|
|
if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
|
|
|
|
Offs = (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
|
|
|
|
else
|
|
|
|
Offs = TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
|
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// N = N + Idx * ElementSize;
|
|
|
|
uint64_t ElementSize = TD.getTypeSize(Ty);
|
|
|
|
SDOperand IdxN = getValue(Idx);
|
|
|
|
|
|
|
|
// If the index is smaller or larger than intptr_t, truncate or extend
|
|
|
|
// it.
|
|
|
|
if (IdxN.getValueType() < N.getValueType()) {
|
|
|
|
if (Idx->getType()->isSigned())
|
|
|
|
IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
|
|
|
|
else
|
|
|
|
IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
|
|
|
|
} else if (IdxN.getValueType() > N.getValueType())
|
|
|
|
IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
|
|
|
|
|
|
|
|
// If this is a multiply by a power of two, turn it into a shl
|
|
|
|
// immediately. This is a very common case.
|
|
|
|
if (isPowerOf2_64(ElementSize)) {
|
|
|
|
unsigned Amt = Log2_64(ElementSize);
|
|
|
|
IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
|
2005-11-09 16:50:40 +00:00
|
|
|
DAG.getConstant(Amt, TLI.getShiftAmountTy()));
|
2005-01-07 07:47:53 +00:00
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-11-09 04:45:33 +00:00
|
|
|
continue;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2005-11-09 04:45:33 +00:00
|
|
|
|
|
|
|
SDOperand Scale = getIntPtrConstant(ElementSize);
|
|
|
|
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
|
|
|
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
setValue(&I, N);
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
|
|
|
// If this is a fixed sized alloca in the entry block of the function,
|
|
|
|
// allocate it statically on the stack.
|
|
|
|
if (FuncInfo.StaticAllocaMap.count(&I))
|
|
|
|
return; // getValue will auto-populate this.
|
|
|
|
|
|
|
|
const Type *Ty = I.getAllocatedType();
|
|
|
|
uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
|
2005-11-06 09:00:38 +00:00
|
|
|
unsigned Align = std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
|
|
|
|
I.getAlignment());
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
SDOperand AllocSize = getValue(I.getArraySize());
|
2005-01-22 23:04:37 +00:00
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
|
|
|
if (IntPtr < AllocSize.getValueType())
|
|
|
|
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
|
|
|
|
else if (IntPtr > AllocSize.getValueType())
|
|
|
|
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2005-01-22 23:04:37 +00:00
|
|
|
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
|
2005-01-07 07:47:53 +00:00
|
|
|
getIntPtrConstant(TySize));
|
|
|
|
|
|
|
|
// Handle alignment. If the requested alignment is less than or equal to the
|
|
|
|
// stack alignment, ignore it and round the size of the allocation up to the
|
|
|
|
// stack alignment size. If the size is greater than the stack alignment, we
|
|
|
|
// note this in the DYNAMIC_STACKALLOC node.
|
|
|
|
unsigned StackAlign =
|
|
|
|
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
|
|
|
|
if (Align <= StackAlign) {
|
|
|
|
Align = 0;
|
|
|
|
// Add SA-1 to the size.
|
|
|
|
AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
|
|
|
|
getIntPtrConstant(StackAlign-1));
|
|
|
|
// Mask out the low bits for alignment purposes.
|
|
|
|
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
|
|
|
|
getIntPtrConstant(~(uint64_t)(StackAlign-1)));
|
|
|
|
}
|
|
|
|
|
2005-05-14 07:29:57 +00:00
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
VTs.push_back(AllocSize.getValueType());
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
Ops.push_back(AllocSize);
|
|
|
|
Ops.push_back(getIntPtrConstant(Align));
|
|
|
|
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
|
2005-01-07 07:47:53 +00:00
|
|
|
DAG.setRoot(setValue(&I, DSA).getValue(1));
|
|
|
|
|
|
|
|
// Inform the Frame Information that we have just allocated a variable-sized
|
|
|
|
// object.
|
|
|
|
CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
|
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitLoad(LoadInst &I) {
|
|
|
|
SDOperand Ptr = getValue(I.getOperand(0));
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-17 22:19:26 +00:00
|
|
|
SDOperand Root;
|
|
|
|
if (I.isVolatile())
|
|
|
|
Root = getRoot();
|
|
|
|
else {
|
|
|
|
// Do not serialize non-volatile loads against each other.
|
|
|
|
Root = DAG.getRoot();
|
|
|
|
}
|
2006-03-15 22:19:46 +00:00
|
|
|
|
|
|
|
setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
|
|
|
|
Root, I.isVolatile()));
|
|
|
|
}
|
|
|
|
|
|
|
|
SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
|
|
|
|
SDOperand SrcValue, SDOperand Root,
|
|
|
|
bool isVolatile) {
|
2005-11-19 00:36:38 +00:00
|
|
|
SDOperand L;
|
Teach the SelectionDAG ISel how to turn ConstantPacked values into
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24616 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-06 06:18:55 +00:00
|
|
|
if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
|
2005-11-22 01:29:36 +00:00
|
|
|
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
|
2006-03-18 01:44:44 +00:00
|
|
|
L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
|
2005-11-19 00:36:38 +00:00
|
|
|
} else {
|
2006-03-15 22:19:46 +00:00
|
|
|
L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
|
2005-11-19 00:36:38 +00:00
|
|
|
}
|
2005-01-17 22:19:26 +00:00
|
|
|
|
2006-03-15 22:19:46 +00:00
|
|
|
if (isVolatile)
|
2005-01-17 22:19:26 +00:00
|
|
|
DAG.setRoot(L.getValue(1));
|
|
|
|
else
|
|
|
|
PendingLoads.push_back(L.getValue(1));
|
2006-03-15 22:19:46 +00:00
|
|
|
|
|
|
|
return L;
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitStore(StoreInst &I) {
|
|
|
|
Value *SrcV = I.getOperand(0);
|
|
|
|
SDOperand Src = getValue(SrcV);
|
|
|
|
SDOperand Ptr = getValue(I.getOperand(1));
|
2005-05-09 04:08:33 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
|
2005-06-29 18:54:02 +00:00
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-11-09 19:44:01 +00:00
|
|
|
/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
|
|
|
|
/// we want to emit this as a call to a named external function, return the name
|
|
|
|
/// otherwise lower it and return null.
|
|
|
|
const char *
|
|
|
|
SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
|
|
|
|
switch (Intrinsic) {
|
|
|
|
case Intrinsic::vastart: visitVAStart(I); return 0;
|
|
|
|
case Intrinsic::vaend: visitVAEnd(I); return 0;
|
|
|
|
case Intrinsic::vacopy: visitVACopy(I); return 0;
|
|
|
|
case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
|
|
|
|
case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
|
|
|
|
case Intrinsic::setjmp:
|
|
|
|
return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
|
|
|
|
break;
|
|
|
|
case Intrinsic::longjmp:
|
|
|
|
return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
|
|
|
|
break;
|
2006-03-03 00:00:25 +00:00
|
|
|
case Intrinsic::memcpy_i32:
|
|
|
|
case Intrinsic::memcpy_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMCPY);
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::memset_i32:
|
|
|
|
case Intrinsic::memset_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMSET);
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::memmove_i32:
|
|
|
|
case Intrinsic::memmove_i64:
|
|
|
|
visitMemIntrinsic(I, ISD::MEMMOVE);
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
|
2005-12-13 17:40:33 +00:00
|
|
|
case Intrinsic::dbg_stoppoint: {
|
2006-02-11 01:01:30 +00:00
|
|
|
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
|
2006-03-13 13:07:37 +00:00
|
|
|
if (DebugInfo && DebugInfo->Verify(I.getOperand(3))) {
|
2006-02-11 01:01:30 +00:00
|
|
|
std::vector<SDOperand> Ops;
|
2005-11-29 06:21:05 +00:00
|
|
|
|
2006-02-11 01:01:30 +00:00
|
|
|
// Input Chain
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
|
|
|
|
// line number
|
2006-03-13 13:07:37 +00:00
|
|
|
Ops.push_back(getValue(I.getOperand(1)));
|
2006-02-11 01:01:30 +00:00
|
|
|
|
|
|
|
// column
|
2006-03-13 13:07:37 +00:00
|
|
|
Ops.push_back(getValue(I.getOperand(2)));
|
2006-02-11 01:01:30 +00:00
|
|
|
|
2006-03-13 13:07:37 +00:00
|
|
|
DebugInfoDesc *DD = DebugInfo->getDescFor(I.getOperand(3));
|
2006-02-11 01:01:30 +00:00
|
|
|
assert(DD && "Not a debug information descriptor");
|
|
|
|
CompileUnitDesc *CompileUnit = dyn_cast<CompileUnitDesc>(DD);
|
|
|
|
assert(CompileUnit && "Not a compile unit");
|
|
|
|
Ops.push_back(DAG.getString(CompileUnit->getFileName()));
|
|
|
|
Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
|
|
|
|
|
|
|
|
if (Ops.size() == 5) // Found filename/workingdir.
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
|
2005-12-13 17:40:33 +00:00
|
|
|
}
|
|
|
|
|
2005-12-03 18:50:48 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
|
2005-11-16 07:22:30 +00:00
|
|
|
return 0;
|
2005-11-29 06:21:05 +00:00
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::dbg_region_start:
|
2005-11-16 07:22:30 +00:00
|
|
|
if (I.getType() != Type::VoidTy)
|
|
|
|
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::dbg_region_end:
|
2005-11-16 07:22:30 +00:00
|
|
|
if (I.getType() != Type::VoidTy)
|
|
|
|
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
case Intrinsic::dbg_func_start:
|
2005-11-16 07:22:30 +00:00
|
|
|
if (I.getType() != Type::VoidTy)
|
|
|
|
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::isunordered_f32:
|
|
|
|
case Intrinsic::isunordered_f64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2)), ISD::SETUO));
|
|
|
|
return 0;
|
|
|
|
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::sqrt_f32:
|
|
|
|
case Intrinsic::sqrt_f64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FSQRT,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
|
|
|
case Intrinsic::pcmarker: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
|
|
|
|
return 0;
|
|
|
|
}
|
2005-11-11 22:48:54 +00:00
|
|
|
case Intrinsic::readcyclecounter: {
|
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
VTs.push_back(MVT::i64);
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
|
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
2005-11-11 16:47:30 +00:00
|
|
|
return 0;
|
2005-11-11 22:48:54 +00:00
|
|
|
}
|
2006-01-14 03:14:10 +00:00
|
|
|
case Intrinsic::bswap_i16:
|
|
|
|
case Intrinsic::bswap_i32:
|
|
|
|
case Intrinsic::bswap_i64:
|
|
|
|
setValue(&I, DAG.getNode(ISD::BSWAP,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::cttz_i8:
|
|
|
|
case Intrinsic::cttz_i16:
|
|
|
|
case Intrinsic::cttz_i32:
|
|
|
|
case Intrinsic::cttz_i64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::CTTZ,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::ctlz_i8:
|
|
|
|
case Intrinsic::ctlz_i16:
|
|
|
|
case Intrinsic::ctlz_i32:
|
|
|
|
case Intrinsic::ctlz_i64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::CTLZ,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
For PR411:
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-16 21:12:35 +00:00
|
|
|
case Intrinsic::ctpop_i8:
|
|
|
|
case Intrinsic::ctpop_i16:
|
|
|
|
case Intrinsic::ctpop_i32:
|
|
|
|
case Intrinsic::ctpop_i64:
|
2005-11-09 19:44:01 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::CTPOP,
|
|
|
|
getValue(I.getOperand(1)).getValueType(),
|
|
|
|
getValue(I.getOperand(1))));
|
|
|
|
return 0;
|
2006-01-13 02:50:02 +00:00
|
|
|
case Intrinsic::stacksave: {
|
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
VTs.push_back(TLI.getPointerTy());
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
Ops.push_back(getRoot());
|
|
|
|
SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
|
|
|
|
setValue(&I, Tmp);
|
|
|
|
DAG.setRoot(Tmp.getValue(1));
|
|
|
|
return 0;
|
|
|
|
}
|
2006-01-23 05:22:07 +00:00
|
|
|
case Intrinsic::stackrestore: {
|
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
|
2006-01-13 02:50:02 +00:00
|
|
|
return 0;
|
2006-01-23 05:22:07 +00:00
|
|
|
}
|
2005-12-12 22:51:16 +00:00
|
|
|
case Intrinsic::prefetch:
|
|
|
|
// FIXME: Currently discarding prefetches.
|
|
|
|
return 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
default:
|
|
|
|
std::cerr << I;
|
|
|
|
assert(0 && "This intrinsic is not implemented yet!");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitCall(CallInst &I) {
|
2005-01-08 22:48:57 +00:00
|
|
|
const char *RenameFn = 0;
|
2005-11-09 19:44:01 +00:00
|
|
|
if (Function *F = I.getCalledFunction()) {
|
2005-04-02 05:26:53 +00:00
|
|
|
if (F->isExternal())
|
2005-11-09 19:44:01 +00:00
|
|
|
if (unsigned IID = F->getIntrinsicID()) {
|
|
|
|
RenameFn = visitIntrinsicCall(I, IID);
|
|
|
|
if (!RenameFn)
|
|
|
|
return;
|
|
|
|
} else { // Not an LLVM intrinsic.
|
|
|
|
const std::string &Name = F->getName();
|
2006-03-05 05:09:38 +00:00
|
|
|
if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
|
|
|
|
if (I.getNumOperands() == 3 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType() &&
|
|
|
|
I.getType() == I.getOperand(2)->getType()) {
|
|
|
|
SDOperand LHS = getValue(I.getOperand(1));
|
|
|
|
SDOperand RHS = getValue(I.getOperand(2));
|
|
|
|
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
|
|
|
|
LHS, RHS));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
|
2005-04-02 05:26:53 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-02 05:26:53 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
} else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
|
2005-04-30 04:43:14 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
2006-02-14 05:39:35 +00:00
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-30 04:43:14 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
} else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
|
2005-04-30 04:43:14 +00:00
|
|
|
if (I.getNumOperands() == 2 && // Basic sanity checks.
|
|
|
|
I.getOperand(1)->getType()->isFloatingPoint() &&
|
2006-02-14 05:39:35 +00:00
|
|
|
I.getType() == I.getOperand(1)->getType()) {
|
2005-11-09 19:44:01 +00:00
|
|
|
SDOperand Tmp = getValue(I.getOperand(1));
|
2005-04-30 04:43:14 +00:00
|
|
|
setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2005-04-02 05:26:53 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
} else if (isa<InlineAsm>(I.getOperand(0))) {
|
|
|
|
visitInlineAsm(I);
|
|
|
|
return;
|
2005-11-09 19:44:01 +00:00
|
|
|
}
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-08 22:48:57 +00:00
|
|
|
SDOperand Callee;
|
|
|
|
if (!RenameFn)
|
|
|
|
Callee = getValue(I.getOperand(0));
|
|
|
|
else
|
|
|
|
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
|
2005-01-07 07:47:53 +00:00
|
|
|
std::vector<std::pair<SDOperand, const Type*> > Args;
|
2005-11-09 19:44:01 +00:00
|
|
|
Args.reserve(I.getNumOperands());
|
2005-01-07 07:47:53 +00:00
|
|
|
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
|
|
|
|
Value *Arg = I.getOperand(i);
|
|
|
|
SDOperand ArgNode = getValue(Arg);
|
|
|
|
Args.push_back(std::make_pair(ArgNode, Arg->getType()));
|
|
|
|
}
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-03-26 01:29:23 +00:00
|
|
|
const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
|
|
|
|
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-08 19:26:18 +00:00
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2005-05-12 19:56:57 +00:00
|
|
|
TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
|
2005-05-13 18:50:42 +00:00
|
|
|
I.isTailCall(), Callee, Args, DAG);
|
2005-01-07 07:47:53 +00:00
|
|
|
if (I.getType() != Type::VoidTy)
|
2005-01-08 19:26:18 +00:00
|
|
|
setValue(&I, Result.first);
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
|
2006-02-23 20:06:57 +00:00
|
|
|
SDOperand &Chain, SDOperand &Flag)const{
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
|
|
|
|
Chain = Val.getValue(1);
|
|
|
|
Flag = Val.getValue(2);
|
|
|
|
|
|
|
|
// If the result was expanded, copy from the top part.
|
|
|
|
if (Regs.size() > 1) {
|
|
|
|
assert(Regs.size() == 2 &&
|
|
|
|
"Cannot expand to more than 2 elts yet!");
|
|
|
|
SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
|
|
|
|
Chain = Val.getValue(1);
|
|
|
|
Flag = Val.getValue(2);
|
2006-02-23 20:06:57 +00:00
|
|
|
if (DAG.getTargetLoweringInfo().isLittleEndian())
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, if the return value was promoted, truncate it to the
|
|
|
|
// appropriate type.
|
|
|
|
if (RegVT == ValueVT)
|
|
|
|
return Val;
|
|
|
|
|
|
|
|
if (MVT::isInteger(RegVT))
|
|
|
|
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
|
|
|
|
else
|
|
|
|
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
|
|
|
|
}
|
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
|
|
|
|
/// specified value into the registers specified by this object. This uses
|
|
|
|
/// Chain/Flag as the input and updates them for the output Chain/Flag.
|
|
|
|
void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
|
2006-02-23 20:06:57 +00:00
|
|
|
SDOperand &Chain, SDOperand &Flag) const {
|
2006-02-23 19:21:04 +00:00
|
|
|
if (Regs.size() == 1) {
|
|
|
|
// If there is a single register and the types differ, this must be
|
|
|
|
// a promotion.
|
|
|
|
if (RegVT != ValueVT) {
|
|
|
|
if (MVT::isInteger(RegVT))
|
|
|
|
Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
|
|
|
|
else
|
|
|
|
Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
|
|
|
|
}
|
|
|
|
Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
} else {
|
2006-02-23 20:06:57 +00:00
|
|
|
std::vector<unsigned> R(Regs);
|
|
|
|
if (!DAG.getTargetLoweringInfo().isLittleEndian())
|
|
|
|
std::reverse(R.begin(), R.end());
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = R.size(); i != e; ++i) {
|
2006-02-23 19:21:04 +00:00
|
|
|
SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
|
|
|
|
DAG.getConstant(i, MVT::i32));
|
2006-02-23 20:06:57 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
|
2006-02-23 19:21:04 +00:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
|
|
|
/// operand list. This adds the code marker and includes the number of
|
|
|
|
/// values added into it.
|
|
|
|
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
|
2006-02-23 20:06:57 +00:00
|
|
|
std::vector<SDOperand> &Ops) const {
|
2006-02-23 19:21:04 +00:00
|
|
|
Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
|
|
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(Regs[i], RegVT));
|
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
|
|
|
/// isAllocatableRegister - If the specified register is safe to allocate,
|
|
|
|
/// i.e. it isn't a stack pointer or some other special register, return the
|
|
|
|
/// register class for the register. Otherwise, return null.
|
|
|
|
static const TargetRegisterClass *
|
2006-02-22 23:09:03 +00:00
|
|
|
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
|
|
|
|
const TargetLowering &TLI, const MRegisterInfo *MRI) {
|
|
|
|
for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
|
|
|
|
E = MRI->regclass_end(); RCI != E; ++RCI) {
|
|
|
|
const TargetRegisterClass *RC = *RCI;
|
|
|
|
// If none of the the value types for this register class are valid, we
|
|
|
|
// can't use it. For example, 64-bit reg classes on 32-bit targets.
|
|
|
|
bool isLegal = false;
|
|
|
|
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
|
|
|
|
I != E; ++I) {
|
|
|
|
if (TLI.isTypeLegal(*I)) {
|
|
|
|
isLegal = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!isLegal) continue;
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// NOTE: This isn't ideal. In particular, this might allocate the
|
|
|
|
// frame pointer in functions that need it (due to them not being taken
|
|
|
|
// out of allocation, because a variable sized allocation hasn't been seen
|
|
|
|
// yet). This is a slight code pessimization, but should still work.
|
2006-02-22 23:09:03 +00:00
|
|
|
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
|
|
|
|
E = RC->allocation_order_end(MF); I != E; ++I)
|
2006-02-22 22:37:12 +00:00
|
|
|
if (*I == Reg)
|
2006-02-22 23:09:03 +00:00
|
|
|
return RC;
|
2006-02-22 22:37:12 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
RegsForValue SelectionDAGLowering::
|
|
|
|
GetRegistersForValue(const std::string &ConstrCode,
|
|
|
|
MVT::ValueType VT, bool isOutReg, bool isInReg,
|
|
|
|
std::set<unsigned> &OutputRegs,
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
std::set<unsigned> &InputRegs) {
|
2006-02-22 22:37:12 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
|
|
|
|
TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
|
|
|
|
std::vector<unsigned> Regs;
|
|
|
|
|
|
|
|
unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
|
|
|
|
MVT::ValueType RegVT;
|
|
|
|
MVT::ValueType ValueVT = VT;
|
|
|
|
|
|
|
|
if (PhysReg.first) {
|
|
|
|
if (VT == MVT::Other)
|
|
|
|
ValueVT = *PhysReg.second->vt_begin();
|
|
|
|
RegVT = VT;
|
|
|
|
|
|
|
|
// This is a explicit reference to a physical register.
|
|
|
|
Regs.push_back(PhysReg.first);
|
|
|
|
|
|
|
|
// If this is an expanded reference, add the rest of the regs to Regs.
|
|
|
|
if (NumRegs != 1) {
|
|
|
|
RegVT = *PhysReg.second->vt_begin();
|
|
|
|
TargetRegisterClass::iterator I = PhysReg.second->begin();
|
|
|
|
TargetRegisterClass::iterator E = PhysReg.second->end();
|
|
|
|
for (; *I != PhysReg.first; ++I)
|
|
|
|
assert(I != E && "Didn't find reg!");
|
|
|
|
|
|
|
|
// Already added the first reg.
|
|
|
|
--NumRegs; ++I;
|
|
|
|
for (; NumRegs; --NumRegs, ++I) {
|
|
|
|
assert(I != E && "Ran out of registers to allocate!");
|
|
|
|
Regs.push_back(*I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return RegsForValue(Regs, RegVT, ValueVT);
|
|
|
|
}
|
|
|
|
|
|
|
|
// This is a reference to a register class. Allocate NumRegs consecutive,
|
|
|
|
// available, registers from the class.
|
|
|
|
std::vector<unsigned> RegClassRegs =
|
|
|
|
TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
|
|
|
|
MachineFunction &MF = *CurMBB->getParent();
|
2006-02-22 22:37:12 +00:00
|
|
|
unsigned NumAllocated = 0;
|
|
|
|
for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = RegClassRegs[i];
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// See if this register is available.
|
2006-02-22 22:37:12 +00:00
|
|
|
if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
|
|
|
|
(isInReg && InputRegs.count(Reg))) { // Already used.
|
|
|
|
// Make sure we find consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// Check to see if this register is allocatable (i.e. don't give out the
|
|
|
|
// stack pointer).
|
2006-02-22 23:09:03 +00:00
|
|
|
const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
|
2006-02-22 22:37:12 +00:00
|
|
|
if (!RC) {
|
|
|
|
// Make sure we find consecutive registers.
|
|
|
|
NumAllocated = 0;
|
|
|
|
continue;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Okay, this register is good, we can use it.
|
|
|
|
++NumAllocated;
|
|
|
|
|
|
|
|
// If we allocated enough consecutive
|
|
|
|
if (NumAllocated == NumRegs) {
|
|
|
|
unsigned RegStart = (i-NumAllocated)+1;
|
|
|
|
unsigned RegEnd = i+1;
|
|
|
|
// Mark all of the allocated registers used.
|
|
|
|
for (unsigned i = RegStart; i != RegEnd; ++i) {
|
|
|
|
unsigned Reg = RegClassRegs[i];
|
|
|
|
Regs.push_back(Reg);
|
|
|
|
if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
|
|
|
|
if (isInReg) InputRegs.insert(Reg); // Mark reg used.
|
|
|
|
}
|
|
|
|
|
|
|
|
return RegsForValue(Regs, *RC->vt_begin(), VT);
|
|
|
|
}
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
2006-02-22 22:37:12 +00:00
|
|
|
|
|
|
|
// Otherwise, we couldn't allocate enough registers for this.
|
|
|
|
return RegsForValue();
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
}
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
|
2006-01-26 22:24:51 +00:00
|
|
|
/// visitInlineAsm - Handle a call to an InlineAsm object.
|
|
|
|
///
|
|
|
|
void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
|
|
|
|
InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
|
|
|
|
|
|
|
|
SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
|
|
|
|
MVT::Other);
|
|
|
|
|
|
|
|
// Note, we treat inline asms both with and without side-effects as the same.
|
|
|
|
// If an inline asm doesn't have side effects and doesn't access memory, we
|
|
|
|
// could not choose to not chain it.
|
|
|
|
bool hasSideEffects = IA->hasSideEffects();
|
|
|
|
|
2006-02-01 01:28:23 +00:00
|
|
|
std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
|
2006-02-22 00:56:39 +00:00
|
|
|
std::vector<MVT::ValueType> ConstraintVTs;
|
2006-01-26 22:24:51 +00:00
|
|
|
|
|
|
|
/// AsmNodeOperands - A list of pairs. The first element is a register, the
|
|
|
|
/// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
|
|
|
|
/// if it is a def of that register.
|
|
|
|
std::vector<SDOperand> AsmNodeOperands;
|
|
|
|
AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
|
|
|
|
AsmNodeOperands.push_back(AsmStr);
|
|
|
|
|
|
|
|
SDOperand Chain = getRoot();
|
|
|
|
SDOperand Flag;
|
|
|
|
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// We fully assign registers here at isel time. This is not optimal, but
|
|
|
|
// should work. For register classes that correspond to LLVM classes, we
|
|
|
|
// could let the LLVM RA do its thing, but we currently don't. Do a prepass
|
|
|
|
// over the constraints, collecting fixed registers that we know we can't use.
|
|
|
|
std::set<unsigned> OutputRegs, InputRegs;
|
2006-02-22 00:56:39 +00:00
|
|
|
unsigned OpNum = 1;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
|
|
|
|
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
|
|
|
|
std::string &ConstraintCode = Constraints[i].Codes[0];
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
|
2006-02-22 00:56:39 +00:00
|
|
|
MVT::ValueType OpVT;
|
|
|
|
|
|
|
|
// Compute the value type for each operand and add it to ConstraintVTs.
|
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput:
|
|
|
|
if (!Constraints[i].isIndirectOutput) {
|
|
|
|
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
|
|
|
|
OpVT = TLI.getValueType(I.getType());
|
|
|
|
} else {
|
2006-02-27 23:45:39 +00:00
|
|
|
const Type *OpTy = I.getOperand(OpNum)->getType();
|
2006-02-22 00:56:39 +00:00
|
|
|
OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case InlineAsm::isInput:
|
|
|
|
OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
break;
|
|
|
|
case InlineAsm::isClobber:
|
|
|
|
OpVT = MVT::Other;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ConstraintVTs.push_back(OpVT);
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
|
|
|
|
continue; // Not assigned a fixed reg.
|
2006-02-22 00:56:39 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Build a list of regs that this operand uses. This always has a single
|
|
|
|
// element for promoted/expanded operands.
|
|
|
|
RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
|
|
|
|
false, false,
|
|
|
|
OutputRegs, InputRegs);
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
|
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput:
|
|
|
|
// We can't assign any other output to this register.
|
2006-02-22 22:37:12 +00:00
|
|
|
OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
// If this is an early-clobber output, it cannot be assigned to the same
|
|
|
|
// value as the input reg.
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
break;
|
2006-02-22 00:56:39 +00:00
|
|
|
case InlineAsm::isInput:
|
|
|
|
// We can't assign any other input to this register.
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
2006-02-22 00:56:39 +00:00
|
|
|
break;
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
case InlineAsm::isClobber:
|
|
|
|
// Clobbered regs cannot be used as inputs or outputs.
|
2006-02-22 22:37:12 +00:00
|
|
|
InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
|
|
|
OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2006-02-01 01:28:23 +00:00
|
|
|
|
2006-02-21 23:12:12 +00:00
|
|
|
// Loop over all of the inputs, copying the operand values into the
|
|
|
|
// appropriate registers and processing the output regs.
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue RetValRegs;
|
|
|
|
std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
|
2006-02-22 00:56:39 +00:00
|
|
|
OpNum = 1;
|
2006-02-21 23:12:12 +00:00
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
|
2006-02-01 01:28:23 +00:00
|
|
|
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
|
|
|
|
std::string &ConstraintCode = Constraints[i].Codes[0];
|
2006-02-22 00:56:39 +00:00
|
|
|
|
2006-02-01 01:28:23 +00:00
|
|
|
switch (Constraints[i].Type) {
|
|
|
|
case InlineAsm::isOutput: {
|
2006-02-27 23:45:39 +00:00
|
|
|
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
|
|
|
|
if (ConstraintCode.size() == 1) // not a physreg name.
|
|
|
|
CTy = TLI.getConstraintType(ConstraintCode[0]);
|
|
|
|
|
|
|
|
if (CTy == TargetLowering::C_Memory) {
|
|
|
|
// Memory output.
|
|
|
|
SDOperand InOperandVal = getValue(I.getOperand(OpNum));
|
|
|
|
|
|
|
|
// Check that the operand (the address to store to) isn't a float.
|
|
|
|
if (!MVT::isInteger(InOperandVal.getValueType()))
|
|
|
|
assert(0 && "MATCH FAIL!");
|
|
|
|
|
|
|
|
if (!Constraints[i].isIndirectOutput)
|
|
|
|
assert(0 && "MATCH FAIL!");
|
|
|
|
|
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
|
|
|
|
// Extend/truncate to the right pointer type if needed.
|
|
|
|
MVT::ValueType PtrType = TLI.getPointerTy();
|
|
|
|
if (InOperandVal.getValueType() < PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
|
|
|
|
else if (InOperandVal.getValueType() > PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
|
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know about this output.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, this is a register output.
|
|
|
|
assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
|
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// If this is an early-clobber output, or if there is an input
|
|
|
|
// constraint that matches this, we need to reserve the input register
|
|
|
|
// so no other inputs allocate to it.
|
|
|
|
bool UsesInputRegister = false;
|
|
|
|
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
|
|
|
|
UsesInputRegister = true;
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
|
2006-02-22 22:37:12 +00:00
|
|
|
// Copy the output from the appropriate register. Find a register that
|
|
|
|
// we can use.
|
|
|
|
RegsForValue Regs =
|
|
|
|
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
|
|
|
|
true, UsesInputRegister,
|
|
|
|
OutputRegs, InputRegs);
|
|
|
|
assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
|
2006-02-01 01:28:23 +00:00
|
|
|
|
|
|
|
if (!Constraints[i].isIndirectOutput) {
|
2006-02-22 22:37:12 +00:00
|
|
|
assert(RetValRegs.Regs.empty() &&
|
2006-02-01 01:28:23 +00:00
|
|
|
"Cannot have multiple output constraints yet!");
|
|
|
|
assert(I.getType() != Type::VoidTy && "Bad inline asm!");
|
2006-02-22 22:37:12 +00:00
|
|
|
RetValRegs = Regs;
|
2006-02-01 01:28:23 +00:00
|
|
|
} else {
|
2006-02-27 23:45:39 +00:00
|
|
|
IndirectStoresToEmit.push_back(std::make_pair(Regs,
|
|
|
|
I.getOperand(OpNum)));
|
2006-02-01 01:28:23 +00:00
|
|
|
OpNum++; // Consumes a call operand.
|
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know that this register is
|
|
|
|
// set.
|
2006-02-23 19:21:04 +00:00
|
|
|
Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case InlineAsm::isInput: {
|
2006-02-27 23:45:39 +00:00
|
|
|
SDOperand InOperandVal = getValue(I.getOperand(OpNum));
|
Implement simple register assignment for inline asms. This allows us to compile:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
|
|
|
OpNum++; // Consumes a call operand.
|
2006-02-04 02:16:44 +00:00
|
|
|
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
if (isdigit(ConstraintCode[0])) { // Matching constraint?
|
|
|
|
// If this is required to match an output register we have already set,
|
|
|
|
// just use its register.
|
|
|
|
unsigned OperandNo = atoi(ConstraintCode.c_str());
|
2006-02-04 02:16:44 +00:00
|
|
|
|
2006-02-23 19:21:04 +00:00
|
|
|
// Scan until we find the definition we already emitted of this operand.
|
|
|
|
// When we find it, create a RegsForValue operand.
|
|
|
|
unsigned CurOp = 2; // The first operand.
|
|
|
|
for (; OperandNo; --OperandNo) {
|
|
|
|
// Advance to the next operand.
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
|
|
|
assert((NumOps & 7) == 2 /*REGDEF*/ &&
|
|
|
|
"Skipped past definitions?");
|
|
|
|
CurOp += (NumOps>>3)+1;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned NumOps =
|
|
|
|
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
|
|
|
|
assert((NumOps & 7) == 2 /*REGDEF*/ &&
|
|
|
|
"Skipped past definitions?");
|
|
|
|
|
|
|
|
// Add NumOps>>3 registers to MatchedRegs.
|
|
|
|
RegsForValue MatchedRegs;
|
|
|
|
MatchedRegs.ValueVT = InOperandVal.getValueType();
|
|
|
|
MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
|
|
|
|
for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
|
|
|
|
unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
|
|
|
|
MatchedRegs.Regs.push_back(Reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Use the produced MatchedRegs object to
|
|
|
|
MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
|
|
|
|
MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
|
2006-02-24 01:11:24 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
|
|
|
|
if (ConstraintCode.size() == 1) // not a physreg name.
|
|
|
|
CTy = TLI.getConstraintType(ConstraintCode[0]);
|
2006-02-04 02:16:44 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
if (CTy == TargetLowering::C_Other) {
|
|
|
|
if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
|
|
|
|
assert(0 && "MATCH FAIL!");
|
2006-02-23 19:21:04 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
|
|
|
break;
|
|
|
|
} else if (CTy == TargetLowering::C_Memory) {
|
|
|
|
// Memory input.
|
|
|
|
|
|
|
|
// Check that the operand isn't a float.
|
|
|
|
if (!MVT::isInteger(InOperandVal.getValueType()))
|
|
|
|
assert(0 && "MATCH FAIL!");
|
2006-02-23 19:21:04 +00:00
|
|
|
|
2006-02-24 01:11:24 +00:00
|
|
|
// Extend/truncate to the right pointer type if needed.
|
|
|
|
MVT::ValueType PtrType = TLI.getPointerTy();
|
|
|
|
if (InOperandVal.getValueType() < PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
|
|
|
|
else if (InOperandVal.getValueType() > PtrType)
|
|
|
|
InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
|
|
|
|
|
|
|
|
// Add information to the INLINEASM node to know about this input.
|
|
|
|
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
|
|
|
AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
|
|
|
|
AsmNodeOperands.push_back(InOperandVal);
|
2006-02-23 19:21:04 +00:00
|
|
|
break;
|
Implement matching constraints. We can now say things like this:
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
|
|
|
}
|
2006-02-24 01:11:24 +00:00
|
|
|
|
|
|
|
assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
|
|
|
|
|
|
|
|
// Copy the input into the appropriate registers.
|
|
|
|
RegsForValue InRegs =
|
|
|
|
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
|
|
|
|
false, true, OutputRegs, InputRegs);
|
|
|
|
// FIXME: should be match fail.
|
|
|
|
assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
|
|
|
|
|
|
|
|
InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
|
|
|
|
|
|
|
|
InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
case InlineAsm::isClobber: {
|
|
|
|
RegsForValue ClobberedRegs =
|
|
|
|
GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
|
|
|
|
OutputRegs, InputRegs);
|
|
|
|
// Add the clobbered value to the operand list, so that the register
|
|
|
|
// allocator is aware that the physreg got clobbered.
|
|
|
|
if (!ClobberedRegs.Regs.empty())
|
|
|
|
ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
break;
|
|
|
|
}
|
2006-02-23 19:21:04 +00:00
|
|
|
}
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
|
|
|
|
// Finish up input operands.
|
|
|
|
AsmNodeOperands[0] = Chain;
|
|
|
|
if (Flag.Val) AsmNodeOperands.push_back(Flag);
|
|
|
|
|
|
|
|
std::vector<MVT::ValueType> VTs;
|
|
|
|
VTs.push_back(MVT::Other);
|
|
|
|
VTs.push_back(MVT::Flag);
|
|
|
|
Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
// If this asm returns a register value, copy the result from that register
|
|
|
|
// and set it as the value of the call.
|
2006-02-22 22:37:12 +00:00
|
|
|
if (!RetValRegs.Regs.empty())
|
|
|
|
setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
|
|
|
|
std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
|
|
|
|
|
|
|
|
// Process indirect outputs, first output all of the flagged copies out of
|
|
|
|
// physregs.
|
|
|
|
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
|
2006-02-22 22:37:12 +00:00
|
|
|
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
Value *Ptr = IndirectStoresToEmit[i].second;
|
2006-02-22 22:37:12 +00:00
|
|
|
SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
|
|
|
|
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
}
|
2006-01-26 22:24:51 +00:00
|
|
|
|
Handle physreg input/outputs. We now compile this:
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
|
|
|
// Emit the non-flagged stores from the physregs.
|
|
|
|
std::vector<SDOperand> OutChains;
|
|
|
|
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
|
|
|
|
OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
|
|
StoresToEmit[i].first,
|
|
|
|
getValue(StoresToEmit[i].second),
|
|
|
|
DAG.getSrcValue(StoresToEmit[i].second)));
|
|
|
|
if (!OutChains.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
|
2006-01-26 22:24:51 +00:00
|
|
|
DAG.setRoot(Chain);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitMalloc(MallocInst &I) {
|
|
|
|
SDOperand Src = getValue(I.getOperand(0));
|
|
|
|
|
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
2005-01-22 23:04:37 +00:00
|
|
|
|
|
|
|
if (IntPtr < Src.getValueType())
|
|
|
|
Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
|
|
|
|
else if (IntPtr > Src.getValueType())
|
|
|
|
Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
// Scale the source by the type size.
|
|
|
|
uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
|
|
|
|
Src = DAG.getNode(ISD::MUL, Src.getValueType(),
|
|
|
|
Src, getIntPtrConstant(ElementSize));
|
|
|
|
|
|
|
|
std::vector<std::pair<SDOperand, const Type*> > Args;
|
|
|
|
Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
|
2005-01-08 19:26:18 +00:00
|
|
|
|
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2005-05-13 18:50:42 +00:00
|
|
|
TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
|
2005-01-08 19:26:18 +00:00
|
|
|
DAG.getExternalSymbol("malloc", IntPtr),
|
|
|
|
Args, DAG);
|
|
|
|
setValue(&I, Result.first); // Pointers always fit in registers
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitFree(FreeInst &I) {
|
|
|
|
std::vector<std::pair<SDOperand, const Type*> > Args;
|
|
|
|
Args.push_back(std::make_pair(getValue(I.getOperand(0)),
|
|
|
|
TLI.getTargetData().getIntPtrType()));
|
|
|
|
MVT::ValueType IntPtr = TLI.getPointerTy();
|
2005-01-08 19:26:18 +00:00
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2005-05-13 18:50:42 +00:00
|
|
|
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
|
2005-01-08 19:26:18 +00:00
|
|
|
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
|
|
|
|
DAG.setRoot(Result.second);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-08-26 20:54:47 +00:00
|
|
|
// InsertAtEndOfBasicBlock - This method should be implemented by targets that
|
|
|
|
// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
|
|
|
|
// instructions are special in various ways, which require special support to
|
|
|
|
// insert. The specified MachineInstr is created but not inserted into any
|
|
|
|
// basic blocks, and the scheduler passes ownership of it to this method.
|
|
|
|
MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) {
|
|
|
|
std::cerr << "If a target marks an instruction with "
|
|
|
|
"'usesCustomDAGSchedInserter', it must implement "
|
|
|
|
"TargetLowering::InsertAtEndOfBasicBlock!\n";
|
|
|
|
abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-01-09 00:00:49 +00:00
|
|
|
void SelectionDAGLowering::visitVAStart(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-09 00:00:49 +00:00
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
|
|
|
|
getValue(I.getOperand(0)),
|
|
|
|
DAG.getSrcValue(I.getOperand(0)));
|
|
|
|
setValue(&I, V);
|
|
|
|
DAG.setRoot(V.getValue(1));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1))));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGLowering::visitVACopy(CallInst &I) {
|
2006-01-25 18:21:52 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
|
|
|
|
getValue(I.getOperand(1)),
|
|
|
|
getValue(I.getOperand(2)),
|
|
|
|
DAG.getSrcValue(I.getOperand(1)),
|
|
|
|
DAG.getSrcValue(I.getOperand(2))));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-09 00:00:49 +00:00
|
|
|
// It is always conservatively correct for llvm.returnaddress and
|
|
|
|
// llvm.frameaddress to return 0.
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
|
|
TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
|
|
|
|
unsigned Depth, SelectionDAG &DAG) {
|
|
|
|
return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-05-14 05:50:48 +00:00
|
|
|
SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
2005-01-16 07:28:41 +00:00
|
|
|
assert(0 && "LowerOperation not implemented for this target!");
|
|
|
|
abort();
|
2005-02-17 21:39:27 +00:00
|
|
|
return SDOperand();
|
2005-01-16 07:28:41 +00:00
|
|
|
}
|
|
|
|
|
2006-01-28 03:14:31 +00:00
|
|
|
SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
|
|
|
|
SelectionDAG &DAG) {
|
|
|
|
assert(0 && "CustomPromoteOperation not implemented for this target!");
|
|
|
|
abort();
|
|
|
|
return SDOperand();
|
|
|
|
}
|
|
|
|
|
2005-01-09 00:00:49 +00:00
|
|
|
void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
|
|
|
|
unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
|
|
|
|
std::pair<SDOperand,SDOperand> Result =
|
2005-01-17 19:43:36 +00:00
|
|
|
TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
|
2005-01-09 00:00:49 +00:00
|
|
|
setValue(&I, Result.first);
|
|
|
|
DAG.setRoot(Result.second);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
2006-02-15 21:59:04 +00:00
|
|
|
/// getMemsetValue - Vectorized representation of the memset value
|
2006-02-14 08:22:34 +00:00
|
|
|
/// operand.
|
|
|
|
static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
|
2006-02-15 22:12:35 +00:00
|
|
|
SelectionDAG &DAG) {
|
2006-02-14 08:22:34 +00:00
|
|
|
MVT::ValueType CurVT = VT;
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
|
|
|
|
uint64_t Val = C->getValue() & 255;
|
|
|
|
unsigned Shift = 8;
|
|
|
|
while (CurVT != MVT::i8) {
|
|
|
|
Val = (Val << Shift) | Val;
|
|
|
|
Shift <<= 1;
|
|
|
|
CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
|
|
|
|
}
|
|
|
|
return DAG.getConstant(Val, VT);
|
|
|
|
} else {
|
|
|
|
Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
|
|
|
|
unsigned Shift = 8;
|
|
|
|
while (CurVT != MVT::i8) {
|
|
|
|
Value =
|
|
|
|
DAG.getNode(ISD::OR, VT,
|
|
|
|
DAG.getNode(ISD::SHL, VT, Value,
|
|
|
|
DAG.getConstant(Shift, MVT::i8)), Value);
|
|
|
|
Shift <<= 1;
|
|
|
|
CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-15 21:59:04 +00:00
|
|
|
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
|
|
|
|
/// used when a memcpy is turned into a memset when the source is a constant
|
|
|
|
/// string ptr.
|
|
|
|
static SDOperand getMemsetStringVal(MVT::ValueType VT,
|
|
|
|
SelectionDAG &DAG, TargetLowering &TLI,
|
|
|
|
std::string &Str, unsigned Offset) {
|
|
|
|
MVT::ValueType CurVT = VT;
|
|
|
|
uint64_t Val = 0;
|
|
|
|
unsigned MSB = getSizeInBits(VT) / 8;
|
|
|
|
if (TLI.isLittleEndian())
|
|
|
|
Offset = Offset + MSB - 1;
|
|
|
|
for (unsigned i = 0; i != MSB; ++i) {
|
|
|
|
Val = (Val << 8) | Str[Offset];
|
|
|
|
Offset += TLI.isLittleEndian() ? -1 : 1;
|
|
|
|
}
|
|
|
|
return DAG.getConstant(Val, VT);
|
|
|
|
}
|
|
|
|
|
2006-02-14 08:22:34 +00:00
|
|
|
/// getMemBasePlusOffset - Returns base and offset node for the
|
|
|
|
static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
|
|
|
|
SelectionDAG &DAG, TargetLowering &TLI) {
|
|
|
|
MVT::ValueType VT = Base.getValueType();
|
|
|
|
return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
|
|
|
|
}
|
|
|
|
|
2006-02-14 20:12:38 +00:00
|
|
|
/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
|
2006-02-14 09:11:59 +00:00
|
|
|
/// to replace the memset / memcpy is below the threshold. It also returns the
|
|
|
|
/// types of the sequence of memory ops to perform memset / memcpy.
|
2006-02-14 20:12:38 +00:00
|
|
|
static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
|
|
|
|
unsigned Limit, uint64_t Size,
|
|
|
|
unsigned Align, TargetLowering &TLI) {
|
2006-02-14 08:22:34 +00:00
|
|
|
MVT::ValueType VT;
|
|
|
|
|
|
|
|
if (TLI.allowsUnalignedMemoryAccesses()) {
|
|
|
|
VT = MVT::i64;
|
|
|
|
} else {
|
|
|
|
switch (Align & 7) {
|
|
|
|
case 0:
|
|
|
|
VT = MVT::i64;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
VT = MVT::i32;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
VT = MVT::i16;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
VT = MVT::i8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-02-14 09:11:59 +00:00
|
|
|
MVT::ValueType LVT = MVT::i64;
|
|
|
|
while (!TLI.isTypeLegal(LVT))
|
|
|
|
LVT = (MVT::ValueType)((unsigned)LVT - 1);
|
|
|
|
assert(MVT::isInteger(LVT));
|
2006-02-14 08:22:34 +00:00
|
|
|
|
2006-02-14 09:11:59 +00:00
|
|
|
if (VT > LVT)
|
|
|
|
VT = LVT;
|
|
|
|
|
2006-02-14 23:05:54 +00:00
|
|
|
unsigned NumMemOps = 0;
|
2006-02-14 08:22:34 +00:00
|
|
|
while (Size != 0) {
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
|
|
|
while (VTSize > Size) {
|
|
|
|
VT = (MVT::ValueType)((unsigned)VT - 1);
|
|
|
|
VTSize >>= 1;
|
|
|
|
}
|
2006-02-14 09:11:59 +00:00
|
|
|
assert(MVT::isInteger(VT));
|
|
|
|
|
|
|
|
if (++NumMemOps > Limit)
|
|
|
|
return false;
|
2006-02-14 08:22:34 +00:00
|
|
|
MemOps.push_back(VT);
|
|
|
|
Size -= VTSize;
|
|
|
|
}
|
2006-02-14 09:11:59 +00:00
|
|
|
|
|
|
|
return true;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
|
2006-02-14 08:22:34 +00:00
|
|
|
SDOperand Op1 = getValue(I.getOperand(1));
|
|
|
|
SDOperand Op2 = getValue(I.getOperand(2));
|
|
|
|
SDOperand Op3 = getValue(I.getOperand(3));
|
|
|
|
SDOperand Op4 = getValue(I.getOperand(4));
|
|
|
|
unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
|
|
|
|
if (Align == 0) Align = 1;
|
|
|
|
|
|
|
|
if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
|
|
|
|
std::vector<MVT::ValueType> MemOps;
|
|
|
|
|
|
|
|
// Expand memset / memcpy to a series of load / store ops
|
|
|
|
// if the size operand falls below a certain threshold.
|
|
|
|
std::vector<SDOperand> OutChains;
|
|
|
|
switch (Op) {
|
2006-02-14 19:45:56 +00:00
|
|
|
default: break; // Do nothing for now.
|
2006-02-14 08:22:34 +00:00
|
|
|
case ISD::MEMSET: {
|
2006-02-14 20:12:38 +00:00
|
|
|
if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
|
|
|
|
Size->getValue(), Align, TLI)) {
|
2006-02-14 09:11:59 +00:00
|
|
|
unsigned NumMemOps = MemOps.size();
|
2006-02-14 08:22:34 +00:00
|
|
|
unsigned Offset = 0;
|
|
|
|
for (unsigned i = 0; i < NumMemOps; i++) {
|
|
|
|
MVT::ValueType VT = MemOps[i];
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
2006-02-15 22:12:35 +00:00
|
|
|
SDOperand Value = getMemsetValue(Op2, VT, DAG);
|
2006-02-15 01:54:51 +00:00
|
|
|
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
|
|
|
|
Value,
|
2006-02-22 22:37:12 +00:00
|
|
|
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
|
|
|
|
DAG.getSrcValue(I.getOperand(1), Offset));
|
2006-02-15 01:54:51 +00:00
|
|
|
OutChains.push_back(Store);
|
|
|
|
Offset += VTSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::MEMCPY: {
|
|
|
|
if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
|
|
|
|
Size->getValue(), Align, TLI)) {
|
|
|
|
unsigned NumMemOps = MemOps.size();
|
2006-02-16 23:11:42 +00:00
|
|
|
unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
|
2006-02-15 21:59:04 +00:00
|
|
|
GlobalAddressSDNode *G = NULL;
|
|
|
|
std::string Str;
|
2006-02-16 23:11:42 +00:00
|
|
|
bool CopyFromStr = false;
|
2006-02-15 21:59:04 +00:00
|
|
|
|
|
|
|
if (Op2.getOpcode() == ISD::GlobalAddress)
|
|
|
|
G = cast<GlobalAddressSDNode>(Op2);
|
|
|
|
else if (Op2.getOpcode() == ISD::ADD &&
|
|
|
|
Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
|
|
|
|
Op2.getOperand(1).getOpcode() == ISD::Constant) {
|
|
|
|
G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
|
2006-02-16 23:11:42 +00:00
|
|
|
SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
|
2006-02-15 21:59:04 +00:00
|
|
|
}
|
|
|
|
if (G) {
|
|
|
|
GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
|
2006-02-16 23:11:42 +00:00
|
|
|
if (GV) {
|
2006-03-10 23:52:03 +00:00
|
|
|
Str = GV->getStringValue(false);
|
2006-02-16 23:11:42 +00:00
|
|
|
if (!Str.empty()) {
|
|
|
|
CopyFromStr = true;
|
|
|
|
SrcOff += SrcDelta;
|
|
|
|
}
|
|
|
|
}
|
2006-02-15 21:59:04 +00:00
|
|
|
}
|
|
|
|
|
2006-02-15 01:54:51 +00:00
|
|
|
for (unsigned i = 0; i < NumMemOps; i++) {
|
|
|
|
MVT::ValueType VT = MemOps[i];
|
|
|
|
unsigned VTSize = getSizeInBits(VT) / 8;
|
2006-02-15 21:59:04 +00:00
|
|
|
SDOperand Value, Chain, Store;
|
|
|
|
|
2006-02-16 23:11:42 +00:00
|
|
|
if (CopyFromStr) {
|
2006-02-15 21:59:04 +00:00
|
|
|
Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
|
|
|
|
Chain = getRoot();
|
|
|
|
Store =
|
|
|
|
DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
|
|
|
|
DAG.getSrcValue(I.getOperand(1), DstOff));
|
|
|
|
} else {
|
|
|
|
Value = DAG.getLoad(VT, getRoot(),
|
|
|
|
getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
|
|
|
|
DAG.getSrcValue(I.getOperand(2), SrcOff));
|
|
|
|
Chain = Value.getValue(1);
|
|
|
|
Store =
|
|
|
|
DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
|
|
|
|
getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
|
|
|
|
DAG.getSrcValue(I.getOperand(1), DstOff));
|
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
OutChains.push_back(Store);
|
2006-02-15 21:59:04 +00:00
|
|
|
SrcOff += VTSize;
|
|
|
|
DstOff += VTSize;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
break;
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
}
|
2006-02-15 01:54:51 +00:00
|
|
|
|
|
|
|
if (!OutChains.empty()) {
|
|
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
|
|
|
|
return;
|
|
|
|
}
|
2006-02-14 08:22:34 +00:00
|
|
|
}
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
std::vector<SDOperand> Ops;
|
2005-01-17 19:43:36 +00:00
|
|
|
Ops.push_back(getRoot());
|
2006-02-14 08:22:34 +00:00
|
|
|
Ops.push_back(Op1);
|
|
|
|
Ops.push_back(Op2);
|
|
|
|
Ops.push_back(Op3);
|
|
|
|
Ops.push_back(Op4);
|
2005-01-11 05:56:49 +00:00
|
|
|
DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-11 05:56:49 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SelectionDAGISel code
|
|
|
|
//===----------------------------------------------------------------------===//
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
|
|
|
|
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
|
|
|
|
}
|
|
|
|
|
2005-08-17 06:37:43 +00:00
|
|
|
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
|
2005-08-18 17:35:14 +00:00
|
|
|
// FIXME: we only modify the CFG to split critical edges. This
|
|
|
|
// updates dom and loop info.
|
2005-08-17 06:37:43 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
|
|
|
|
/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
|
|
|
|
/// casting to the type of GEPI.
|
|
|
|
static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI,
|
|
|
|
Value *Ptr, Value *PtrOffset) {
|
|
|
|
if (V) return V; // Already computed.
|
|
|
|
|
|
|
|
BasicBlock::iterator InsertPt;
|
|
|
|
if (BB == GEPI->getParent()) {
|
|
|
|
// If insert into the GEP's block, insert right after the GEP.
|
|
|
|
InsertPt = GEPI;
|
|
|
|
++InsertPt;
|
|
|
|
} else {
|
|
|
|
// Otherwise, insert at the top of BB, after any PHI nodes
|
|
|
|
InsertPt = BB->begin();
|
|
|
|
while (isa<PHINode>(InsertPt)) ++InsertPt;
|
|
|
|
}
|
|
|
|
|
2005-12-08 08:00:12 +00:00
|
|
|
// If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
|
|
|
|
// BB so that there is only one value live across basic blocks (the cast
|
|
|
|
// operand).
|
|
|
|
if (CastInst *CI = dyn_cast<CastInst>(Ptr))
|
|
|
|
if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
|
|
|
|
Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
|
|
|
|
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
// Add the offset, cast it to the right type.
|
|
|
|
Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
|
|
|
|
Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
|
|
|
|
return V = Ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
|
|
|
|
/// selection, we want to be a bit careful about some things. In particular, if
|
|
|
|
/// we have a GEP instruction that is used in a different block than it is
|
|
|
|
/// defined, the addressing expression of the GEP cannot be folded into loads or
|
|
|
|
/// stores that use it. In this case, decompose the GEP and move constant
|
|
|
|
/// indices into blocks that use it.
|
|
|
|
static void OptimizeGEPExpression(GetElementPtrInst *GEPI,
|
|
|
|
const TargetData &TD) {
|
|
|
|
// If this GEP is only used inside the block it is defined in, there is no
|
|
|
|
// need to rewrite it.
|
|
|
|
bool isUsedOutsideDefBB = false;
|
|
|
|
BasicBlock *DefBB = GEPI->getParent();
|
|
|
|
for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
|
|
|
|
UI != E; ++UI) {
|
|
|
|
if (cast<Instruction>(*UI)->getParent() != DefBB) {
|
|
|
|
isUsedOutsideDefBB = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!isUsedOutsideDefBB) return;
|
|
|
|
|
|
|
|
// If this GEP has no non-zero constant indices, there is nothing we can do,
|
|
|
|
// ignore it.
|
|
|
|
bool hasConstantIndex = false;
|
|
|
|
for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
|
|
|
|
E = GEPI->op_end(); OI != E; ++OI) {
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI))
|
|
|
|
if (CI->getRawValue()) {
|
|
|
|
hasConstantIndex = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2005-12-11 09:05:13 +00:00
|
|
|
// If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
|
|
|
|
if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) return;
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
|
|
|
|
// Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
|
|
|
|
// constant offset (which we now know is non-zero) and deal with it later.
|
|
|
|
uint64_t ConstantOffset = 0;
|
|
|
|
const Type *UIntPtrTy = TD.getIntPtrType();
|
|
|
|
Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
|
|
|
|
const Type *Ty = GEPI->getOperand(0)->getType();
|
|
|
|
|
|
|
|
for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
|
|
|
|
E = GEPI->op_end(); OI != E; ++OI) {
|
|
|
|
Value *Idx = *OI;
|
|
|
|
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
|
|
|
|
unsigned Field = cast<ConstantUInt>(Idx)->getValue();
|
|
|
|
if (Field)
|
|
|
|
ConstantOffset += TD.getStructLayout(StTy)->MemberOffsets[Field];
|
|
|
|
Ty = StTy->getElementType(Field);
|
|
|
|
} else {
|
|
|
|
Ty = cast<SequentialType>(Ty)->getElementType();
|
|
|
|
|
|
|
|
// Handle constant subscripts.
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
|
|
|
|
if (CI->getRawValue() == 0) continue;
|
|
|
|
|
|
|
|
if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
|
|
|
|
ConstantOffset += (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
|
|
|
|
else
|
|
|
|
ConstantOffset+=TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ptr = Ptr + Idx * ElementSize;
|
|
|
|
|
|
|
|
// Cast Idx to UIntPtrTy if needed.
|
|
|
|
Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
|
|
|
|
|
|
|
|
uint64_t ElementSize = TD.getTypeSize(Ty);
|
|
|
|
// Mask off bits that should not be set.
|
|
|
|
ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
|
|
|
|
Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
|
|
|
|
|
|
|
|
// Multiply by the element size and add to the base.
|
|
|
|
Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
|
|
|
|
Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Make sure that the offset fits in uintptr_t.
|
|
|
|
ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
|
|
|
|
Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
|
|
|
|
|
|
|
|
// Okay, we have now emitted all of the variable index parts to the BB that
|
|
|
|
// the GEP is defined in. Loop over all of the using instructions, inserting
|
|
|
|
// an "add Ptr, ConstantOffset" into each block that uses it and update the
|
2005-12-08 08:00:12 +00:00
|
|
|
// instruction to use the newly computed value, making GEPI dead. When the
|
|
|
|
// user is a load or store instruction address, we emit the add into the user
|
|
|
|
// block, otherwise we use a canonical version right next to the gep (these
|
|
|
|
// won't be foldable as addresses, so we might as well share the computation).
|
|
|
|
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
std::map<BasicBlock*,Value*> InsertedExprs;
|
|
|
|
while (!GEPI->use_empty()) {
|
|
|
|
Instruction *User = cast<Instruction>(GEPI->use_back());
|
2005-12-08 08:00:12 +00:00
|
|
|
|
|
|
|
// If this use is not foldable into the addressing mode, use a version
|
|
|
|
// emitted in the GEP block.
|
|
|
|
Value *NewVal;
|
|
|
|
if (!isa<LoadInst>(User) &&
|
|
|
|
(!isa<StoreInst>(User) || User->getOperand(0) == GEPI)) {
|
|
|
|
NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
|
|
|
|
Ptr, PtrOffset);
|
|
|
|
} else {
|
|
|
|
// Otherwise, insert the code in the User's block so it can be folded into
|
|
|
|
// any users in that block.
|
|
|
|
NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
User->getParent(), GEPI,
|
|
|
|
Ptr, PtrOffset);
|
|
|
|
}
|
2005-12-08 08:00:12 +00:00
|
|
|
User->replaceUsesOfWith(GEPI, NewVal);
|
|
|
|
}
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
|
|
|
|
// Finally, the GEP is dead, remove it.
|
|
|
|
GEPI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
bool SelectionDAGISel::runOnFunction(Function &Fn) {
|
|
|
|
MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
|
|
|
|
RegMap = MF.getSSARegMap();
|
|
|
|
DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
|
|
|
|
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
// First, split all critical edges for PHI nodes with incoming values that are
|
|
|
|
// constants, this way the load of the constant into a vreg will not be placed
|
|
|
|
// into MBBs that are used some other way.
|
|
|
|
//
|
|
|
|
// In this pass we also look for GEP instructions that are used across basic
|
|
|
|
// blocks and rewrites them to improve basic-block-at-a-time selection.
|
|
|
|
//
|
2005-08-18 17:35:14 +00:00
|
|
|
for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
|
|
|
|
PHINode *PN;
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
BasicBlock::iterator BBI;
|
|
|
|
for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
|
2005-08-18 17:35:14 +00:00
|
|
|
for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
|
|
|
|
if (isa<Constant>(PN->getIncomingValue(i)))
|
|
|
|
SplitCriticalEdge(PN->getIncomingBlock(i), BB);
|
Fix the #1 code quality problem that I have seen on X86 (and it also affects
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24606 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 07:10:48 +00:00
|
|
|
|
|
|
|
for (BasicBlock::iterator E = BB->end(); BBI != E; )
|
|
|
|
if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(BBI++))
|
|
|
|
OptimizeGEPExpression(GEPI, TLI.getTargetData());
|
2005-08-18 17:35:14 +00:00
|
|
|
}
|
2005-11-09 19:44:01 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
|
|
|
|
|
|
|
|
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
|
|
|
|
SelectBasicBlock(I, MF, FuncInfo);
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-13 17:59:43 +00:00
|
|
|
SDOperand SelectionDAGISel::
|
|
|
|
CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
|
2005-01-11 22:03:46 +00:00
|
|
|
SDOperand Op = SDL.getValue(V);
|
2005-01-13 20:50:02 +00:00
|
|
|
assert((Op.getOpcode() != ISD::CopyFromReg ||
|
2005-08-16 21:55:35 +00:00
|
|
|
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
|
2005-01-13 20:50:02 +00:00
|
|
|
"Copy from a reg to the same reg!");
|
2005-08-16 21:55:35 +00:00
|
|
|
|
|
|
|
// If this type is not legal, we must make sure to not create an invalid
|
|
|
|
// register use.
|
|
|
|
MVT::ValueType SrcVT = Op.getValueType();
|
|
|
|
MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
|
|
|
|
SelectionDAG &DAG = SDL.DAG;
|
|
|
|
if (SrcVT == DestVT) {
|
|
|
|
return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
|
|
|
|
} else if (SrcVT < DestVT) {
|
|
|
|
// The src value is promoted to the register.
|
2005-08-17 06:06:25 +00:00
|
|
|
if (MVT::isFloatingPoint(SrcVT))
|
|
|
|
Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
|
|
|
|
else
|
2005-09-02 00:19:37 +00:00
|
|
|
Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
|
2005-08-16 21:55:35 +00:00
|
|
|
return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
|
|
|
|
} else {
|
|
|
|
// The src value is expanded into multiple registers.
|
|
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
|
|
|
|
Op, DAG.getConstant(0, MVT::i32));
|
|
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
|
|
|
|
Op, DAG.getConstant(1, MVT::i32));
|
|
|
|
Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
|
|
|
|
return DAG.getCopyToReg(Op, Reg+1, Hi);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
2005-01-17 17:15:02 +00:00
|
|
|
void SelectionDAGISel::
|
|
|
|
LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
|
|
|
|
std::vector<SDOperand> &UnorderedChains) {
|
2005-01-07 07:47:53 +00:00
|
|
|
// If this is the entry block, emit arguments.
|
2005-01-17 17:15:02 +00:00
|
|
|
Function &F = *BB->getParent();
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19639 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-17 17:55:19 +00:00
|
|
|
FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
SDOperand OldRoot = SDL.DAG.getRoot();
|
|
|
|
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
|
|
|
|
|
|
|
|
unsigned a = 0;
|
|
|
|
for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
|
|
|
|
AI != E; ++AI, ++a)
|
|
|
|
if (!AI->use_empty()) {
|
|
|
|
SDL.setValue(AI, Args[a]);
|
2005-09-13 19:30:54 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// If this argument is live outside of the entry block, insert a copy from
|
|
|
|
// whereever we got it to the vreg that other BB's will reference it as.
|
|
|
|
if (FuncInfo.ValueMap.count(AI)) {
|
|
|
|
SDOperand Copy =
|
|
|
|
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
|
|
|
|
UnorderedChains.push_back(Copy);
|
|
|
|
}
|
Implement a target independent optimization to codegen arguments only into
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19639 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-17 17:55:19 +00:00
|
|
|
}
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
|
|
|
|
// Next, if the function has live ins that need to be copied into vregs,
|
|
|
|
// emit the copies now, into the top of the block.
|
|
|
|
MachineFunction &MF = SDL.DAG.getMachineFunction();
|
|
|
|
if (MF.livein_begin() != MF.livein_end()) {
|
|
|
|
SSARegMap *RegMap = MF.getSSARegMap();
|
|
|
|
const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
|
|
|
|
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
|
|
|
|
E = MF.livein_end(); LI != E; ++LI)
|
|
|
|
if (LI->second)
|
|
|
|
MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
|
|
|
|
LI->first, RegMap->getRegClass(LI->second));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
|
|
|
|
// Finally, if the target has anything special to do, allow it to do so.
|
|
|
|
EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
|
2005-01-17 17:15:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
|
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
|
|
|
SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
|
|
|
|
|
|
|
|
std::vector<SDOperand> UnorderedChains;
|
2005-04-21 22:36:52 +00:00
|
|
|
|
Significantly simplify this code and make it more aggressive. Instead of having
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-30 19:42:35 +00:00
|
|
|
// Lower any arguments needed in this block if this is the entry block.
|
|
|
|
if (LLVMBB == &LLVMBB->getParent()->front())
|
|
|
|
LowerArguments(LLVMBB, SDL, UnorderedChains);
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
BB = FuncInfo.MBBMap[LLVMBB];
|
|
|
|
SDL.setCurrentBasicBlock(BB);
|
|
|
|
|
|
|
|
// Lower all of the non-terminator instructions.
|
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
|
|
|
|
I != E; ++I)
|
|
|
|
SDL.visit(*I);
|
|
|
|
|
|
|
|
// Ensure that all instructions which are used outside of their defining
|
|
|
|
// blocks are available as virtual registers.
|
|
|
|
for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
|
2005-01-11 22:03:46 +00:00
|
|
|
if (!I->use_empty() && !isa<PHINode>(I)) {
|
2005-01-09 01:16:24 +00:00
|
|
|
std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
|
2005-01-07 07:47:53 +00:00
|
|
|
if (VMI != FuncInfo.ValueMap.end())
|
2005-01-13 17:59:43 +00:00
|
|
|
UnorderedChains.push_back(
|
|
|
|
CopyValueToVirtualRegister(SDL, I, VMI->second));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
|
|
|
|
// ensure constants are generated when needed. Remember the virtual registers
|
|
|
|
// that need to be added to the Machine PHI nodes as input. We cannot just
|
|
|
|
// directly add them, because expansion might result in multiple MBB's for one
|
|
|
|
// BB. As such, the start of the BB might correspond to a different MBB than
|
|
|
|
// the end.
|
2005-04-21 22:36:52 +00:00
|
|
|
//
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
// Emit constants only once even if used by multiple PHI nodes.
|
|
|
|
std::map<Constant*, unsigned> ConstantsOut;
|
|
|
|
|
|
|
|
// Check successor nodes PHI nodes that expect a constant to be available from
|
|
|
|
// this block.
|
|
|
|
TerminatorInst *TI = LLVMBB->getTerminator();
|
|
|
|
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
|
|
|
|
BasicBlock *SuccBB = TI->getSuccessor(succ);
|
|
|
|
MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
|
|
|
|
PHINode *PN;
|
|
|
|
|
|
|
|
// At this point we know that there is a 1-1 correspondence between LLVM PHI
|
|
|
|
// nodes and Machine PHI nodes, but the incoming operands have not been
|
|
|
|
// emitted yet.
|
|
|
|
for (BasicBlock::iterator I = SuccBB->begin();
|
2005-01-07 21:34:19 +00:00
|
|
|
(PN = dyn_cast<PHINode>(I)); ++I)
|
|
|
|
if (!PN->use_empty()) {
|
|
|
|
unsigned Reg;
|
|
|
|
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
|
|
|
|
if (Constant *C = dyn_cast<Constant>(PHIOp)) {
|
|
|
|
unsigned &RegOut = ConstantsOut[C];
|
|
|
|
if (RegOut == 0) {
|
|
|
|
RegOut = FuncInfo.CreateRegForValue(C);
|
2005-01-13 17:59:43 +00:00
|
|
|
UnorderedChains.push_back(
|
|
|
|
CopyValueToVirtualRegister(SDL, C, RegOut));
|
2005-01-07 21:34:19 +00:00
|
|
|
}
|
|
|
|
Reg = RegOut;
|
|
|
|
} else {
|
|
|
|
Reg = FuncInfo.ValueMap[PHIOp];
|
2005-01-09 01:16:24 +00:00
|
|
|
if (Reg == 0) {
|
2005-04-21 22:36:52 +00:00
|
|
|
assert(isa<AllocaInst>(PHIOp) &&
|
2005-01-09 01:16:24 +00:00
|
|
|
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
|
|
|
|
"Didn't codegen value into a register!??");
|
|
|
|
Reg = FuncInfo.CreateRegForValue(PHIOp);
|
2005-01-13 17:59:43 +00:00
|
|
|
UnorderedChains.push_back(
|
|
|
|
CopyValueToVirtualRegister(SDL, PHIOp, Reg));
|
2005-01-09 01:16:24 +00:00
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2005-01-07 21:34:19 +00:00
|
|
|
// Remember that this register needs to added to the machine PHI node as
|
|
|
|
// the input for this MBB.
|
|
|
|
unsigned NumElements =
|
|
|
|
TLI.getNumElements(TLI.getValueType(PN->getType()));
|
|
|
|
for (unsigned i = 0, e = NumElements; i != e; ++i)
|
|
|
|
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
ConstantsOut.clear();
|
|
|
|
|
2005-01-13 17:59:43 +00:00
|
|
|
// Turn all of the unordered chains into one factored node.
|
2005-01-13 19:53:14 +00:00
|
|
|
if (!UnorderedChains.empty()) {
|
2005-11-09 05:03:03 +00:00
|
|
|
SDOperand Root = SDL.getRoot();
|
|
|
|
if (Root.getOpcode() != ISD::EntryToken) {
|
|
|
|
unsigned i = 0, e = UnorderedChains.size();
|
|
|
|
for (; i != e; ++i) {
|
|
|
|
assert(UnorderedChains[i].Val->getNumOperands() > 1);
|
|
|
|
if (UnorderedChains[i].Val->getOperand(0) == Root)
|
|
|
|
break; // Don't add the root if we already indirectly depend on it.
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == e)
|
|
|
|
UnorderedChains.push_back(Root);
|
|
|
|
}
|
2005-01-13 17:59:43 +00:00
|
|
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
|
|
|
|
}
|
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
// Lower the terminator after the copies are emitted.
|
|
|
|
SDL.visit(*LLVMBB->getTerminator());
|
2005-01-17 19:43:36 +00:00
|
|
|
|
|
|
|
// Make sure the root of the DAG is up-to-date.
|
|
|
|
DAG.setRoot(SDL.getRoot());
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
|
|
|
|
FunctionLoweringInfo &FuncInfo) {
|
2006-01-04 22:28:25 +00:00
|
|
|
SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
|
2005-01-07 07:47:53 +00:00
|
|
|
CurDAG = &DAG;
|
|
|
|
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
|
|
|
|
|
|
|
|
// First step, lower LLVM code to some DAG. This DAG may use operations and
|
|
|
|
// types that are not supported by the target.
|
|
|
|
BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
|
|
|
|
|
2005-10-10 16:47:10 +00:00
|
|
|
// Run the DAG combiner in pre-legalize mode.
|
|
|
|
DAG.Combine(false);
|
2005-09-07 00:15:36 +00:00
|
|
|
|
2005-01-07 07:47:53 +00:00
|
|
|
DEBUG(std::cerr << "Lowered selection DAG:\n");
|
|
|
|
DEBUG(DAG.dump());
|
|
|
|
|
|
|
|
// Second step, hack on the DAG until it only uses operations and types that
|
|
|
|
// the target supports.
|
2005-01-23 04:36:26 +00:00
|
|
|
DAG.Legalize();
|
2005-01-07 07:47:53 +00:00
|
|
|
|
|
|
|
DEBUG(std::cerr << "Legalized selection DAG:\n");
|
|
|
|
DEBUG(DAG.dump());
|
|
|
|
|
2005-10-10 16:47:10 +00:00
|
|
|
// Run the DAG combiner in post-legalize mode.
|
|
|
|
DAG.Combine(true);
|
2005-09-07 00:15:36 +00:00
|
|
|
|
2006-01-21 02:32:06 +00:00
|
|
|
if (ViewISelDAGs) DAG.viewGraph();
|
2005-10-05 06:09:10 +00:00
|
|
|
|
2005-03-30 01:10:47 +00:00
|
|
|
// Third, instruction select all of the operations to machine code, adding the
|
|
|
|
// code to the MachineBasicBlock.
|
2005-01-07 07:47:53 +00:00
|
|
|
InstructionSelectBasicBlock(DAG);
|
|
|
|
|
|
|
|
DEBUG(std::cerr << "Selected machine code:\n");
|
|
|
|
DEBUG(BB->dump());
|
|
|
|
|
2005-03-30 01:10:47 +00:00
|
|
|
// Next, now that we know what the last MBB the LLVM BB expanded is, update
|
2005-01-07 07:47:53 +00:00
|
|
|
// PHI nodes in successors.
|
|
|
|
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
|
|
|
|
MachineInstr *PHI = PHINodesToUpdate[i].first;
|
|
|
|
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
|
|
|
|
"This is not a machine PHI node that we are updating!");
|
|
|
|
PHI->addRegOperand(PHINodesToUpdate[i].second);
|
|
|
|
PHI->addMachineBasicBlockOperand(BB);
|
|
|
|
}
|
2005-03-30 01:10:47 +00:00
|
|
|
|
|
|
|
// Finally, add the CFG edges from the last selected MBB to the successor
|
|
|
|
// MBBs.
|
|
|
|
TerminatorInst *TI = LLVMBB->getTerminator();
|
|
|
|
for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)];
|
|
|
|
BB->addSuccessor(Succ0MBB);
|
|
|
|
}
|
2005-01-07 07:47:53 +00:00
|
|
|
}
|
2006-01-21 02:32:06 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
|
|
|
|
/// target node in the graph.
|
|
|
|
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
|
|
|
|
if (ViewSchedDAGs) DAG.viewGraph();
|
2006-01-23 07:01:07 +00:00
|
|
|
ScheduleDAG *SL = NULL;
|
|
|
|
|
|
|
|
switch (ISHeuristic) {
|
|
|
|
default: assert(0 && "Unrecognized scheduling heuristic");
|
2006-01-25 09:12:57 +00:00
|
|
|
case defaultScheduling:
|
|
|
|
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
|
|
|
|
SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
|
|
|
|
else /* TargetLowering::SchedulingForRegPressure */
|
|
|
|
SL = createBURRListDAGScheduler(DAG, BB);
|
|
|
|
break;
|
2006-01-23 07:01:07 +00:00
|
|
|
case noScheduling:
|
2006-03-10 07:49:12 +00:00
|
|
|
SL = createBFS_DAGScheduler(DAG, BB);
|
|
|
|
break;
|
2006-01-23 07:01:07 +00:00
|
|
|
case simpleScheduling:
|
2006-03-10 07:49:12 +00:00
|
|
|
SL = createSimpleDAGScheduler(false, DAG, BB);
|
|
|
|
break;
|
2006-01-23 07:01:07 +00:00
|
|
|
case simpleNoItinScheduling:
|
2006-03-10 07:49:12 +00:00
|
|
|
SL = createSimpleDAGScheduler(true, DAG, BB);
|
2006-01-23 07:01:07 +00:00
|
|
|
break;
|
2006-01-23 08:26:10 +00:00
|
|
|
case listSchedulingBURR:
|
|
|
|
SL = createBURRListDAGScheduler(DAG, BB);
|
2006-03-05 21:10:33 +00:00
|
|
|
break;
|
2006-03-06 00:22:00 +00:00
|
|
|
case listSchedulingTD:
|
2006-03-08 04:25:59 +00:00
|
|
|
SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
|
2006-03-05 21:10:33 +00:00
|
|
|
break;
|
2006-01-23 07:01:07 +00:00
|
|
|
}
|
2006-01-21 19:12:11 +00:00
|
|
|
BB = SL->Run();
|
2006-02-04 06:49:00 +00:00
|
|
|
delete SL;
|
2006-01-21 02:32:06 +00:00
|
|
|
}
|
2006-02-24 02:13:54 +00:00
|
|
|
|
2006-03-08 04:25:59 +00:00
|
|
|
HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
|
|
|
|
return new HazardRecognizer();
|
2006-03-06 00:22:00 +00:00
|
|
|
}
|
|
|
|
|
2006-02-24 02:13:54 +00:00
|
|
|
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
|
|
|
|
/// by tblgen. Others should not call it.
|
|
|
|
void SelectionDAGISel::
|
|
|
|
SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
|
|
|
|
std::vector<SDOperand> InOps;
|
|
|
|
std::swap(InOps, Ops);
|
|
|
|
|
|
|
|
Ops.push_back(InOps[0]); // input chain.
|
|
|
|
Ops.push_back(InOps[1]); // input asm string.
|
|
|
|
|
|
|
|
const char *AsmStr = cast<ExternalSymbolSDNode>(InOps[1])->getSymbol();
|
|
|
|
unsigned i = 2, e = InOps.size();
|
|
|
|
if (InOps[e-1].getValueType() == MVT::Flag)
|
|
|
|
--e; // Don't process a flag operand if it is here.
|
|
|
|
|
|
|
|
while (i != e) {
|
|
|
|
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
|
|
|
|
if ((Flags & 7) != 4 /*MEM*/) {
|
|
|
|
// Just skip over this operand, copying the operands verbatim.
|
|
|
|
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
|
|
|
|
i += (Flags >> 3) + 1;
|
|
|
|
} else {
|
|
|
|
assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
|
|
|
|
// Otherwise, this is a memory operand. Ask the target to select it.
|
|
|
|
std::vector<SDOperand> SelOps;
|
|
|
|
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
|
|
|
|
std::cerr << "Could not match memory address. Inline asm failure!\n";
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add this to the output node.
|
|
|
|
Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
|
|
|
|
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
|
|
|
|
i += 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add the flag input back if present.
|
|
|
|
if (e != InOps.size())
|
|
|
|
Ops.push_back(InOps.back());
|
|
|
|
}
|