2005-11-15 00:40:23 +00:00
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//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-11-15 00:40:23 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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2006-01-27 08:10:46 +00:00
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#include "X86Subtarget.h"
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2007-07-14 14:06:15 +00:00
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#include "X86RegisterInfo.h"
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2008-01-05 16:56:59 +00:00
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#include "X86MachineFunctionInfo.h"
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2005-11-15 00:40:23 +00:00
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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2007-08-31 15:06:30 +00:00
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#include "llvm/CodeGen/CallingConvLower.h"
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2005-11-15 00:40:23 +00:00
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namespace llvm {
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namespace X86ISD {
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2006-01-06 00:43:03 +00:00
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// X86 Specific DAG Nodes
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2005-11-15 00:40:23 +00:00
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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2005-12-17 01:21:05 +00:00
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FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
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2005-11-15 00:40:23 +00:00
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2007-12-14 02:13:44 +00:00
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/// BSF - Bit scan forward.
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/// BSR - Bit scan reverse.
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BSF,
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BSR,
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2006-01-09 18:33:28 +00:00
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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2006-01-31 03:14:29 +00:00
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/// FAND - Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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2007-01-05 07:55:56 +00:00
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/// FOR - Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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2006-01-31 22:28:30 +00:00
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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2007-01-05 21:37:56 +00:00
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/// FSRL - Bitwise logical right shift of floating point values. These
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/// corresponds to X86::PSRLDQ.
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2007-01-05 07:55:56 +00:00
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FSRL,
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2006-02-04 02:20:30 +00:00
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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2006-01-12 22:54:21 +00:00
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FILD,
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2006-02-04 02:20:30 +00:00
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FILD_FLAG,
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2005-11-15 00:40:23 +00:00
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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2006-10-18 18:26:48 +00:00
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/// has two inputs (token chain and address) and two outputs (int value
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/// and token chain).
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2005-11-15 00:40:23 +00:00
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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2005-12-21 02:39:21 +00:00
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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2005-12-23 07:31:11 +00:00
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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2005-12-21 02:39:21 +00:00
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FLD,
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2006-01-05 00:27:02 +00:00
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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2005-11-15 00:40:23 +00:00
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/// CALL/TAILCALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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/// The CALL vs TAILCALL distinction boils down to whether the callee is
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/// known not to modify the caller's stack frame, as is standard with
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/// LLVM.
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CALL,
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TAILCALL,
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2005-11-20 21:41:10 +00:00
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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2005-12-17 01:21:05 +00:00
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/// X86 compare and logical compare instructions.
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2007-09-17 17:42:53 +00:00
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CMP, COMI, UCOMI,
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2005-12-17 01:21:05 +00:00
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2005-12-21 20:21:51 +00:00
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// X86 conditional moves. Operand 1 and operand 2 are the two values
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2006-10-18 18:26:48 +00:00
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/// to select from (operand 1 is a R/W operand). Operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction. It also writes a flag result.
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2005-12-17 01:21:05 +00:00
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CMOV,
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2005-12-19 23:12:38 +00:00
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2005-12-21 20:21:51 +00:00
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/// X86 conditional branches. Operand 1 is the chain operand, operand 2
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/// is the block to branch if condition is true, operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction.
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2005-12-19 23:12:38 +00:00
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BRCOND,
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2005-12-21 02:39:21 +00:00
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2006-01-11 22:15:48 +00:00
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/// Return with a flag operand. Operand 1 is the chain operand, operand
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/// 2 is the number of bytes of stack to pop.
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2005-12-21 02:39:21 +00:00
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RET_FLAG,
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2006-01-11 22:15:48 +00:00
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/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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2006-01-31 22:28:30 +00:00
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2006-02-18 00:15:05 +00:00
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/// GlobalBaseReg - On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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2006-02-23 02:43:52 +00:00
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2006-09-28 23:33:12 +00:00
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/// Wrapper - A wrapper node for TargetConstantPool,
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2006-02-23 20:41:18 +00:00
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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2006-03-21 23:01:21 +00:00
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2006-11-30 21:55:46 +00:00
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/// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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2008-02-11 04:19:36 +00:00
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/// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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2006-03-31 19:22:53 +00:00
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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2006-03-31 21:55:24 +00:00
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/// i32, corresponds to X86::PEXTRW.
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2006-03-31 19:22:53 +00:00
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PEXTRW,
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2006-03-31 21:55:24 +00:00
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2008-02-11 04:19:36 +00:00
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/// INSERTPS - Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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2006-03-31 21:55:24 +00:00
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/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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2006-11-10 21:43:37 +00:00
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PINSRW,
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/// FMAX, FMIN - Floating point max and min.
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///
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2007-04-20 21:38:10 +00:00
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FMAX, FMIN,
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2007-07-10 00:05:58 +00:00
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/// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
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/// approximation. Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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2008-05-08 00:57:18 +00:00
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// TLSADDR, THREAThread - Thread Local Storage.
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2007-07-14 14:06:15 +00:00
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TLSADDR, THREAD_POINTER,
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2008-05-08 00:57:18 +00:00
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// EH_RETURN - Exception Handling helpers.
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2007-10-11 19:40:01 +00:00
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EH_RETURN,
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2008-03-19 16:39:45 +00:00
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/// TC_RETURN - Tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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2007-11-16 01:31:51 +00:00
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TC_RETURN,
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2008-05-08 00:57:18 +00:00
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// LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
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2008-03-01 21:52:34 +00:00
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LCMPXCHG_DAG,
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2008-03-05 01:15:49 +00:00
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LCMPXCHG8_DAG,
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2008-03-01 21:52:34 +00:00
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2008-05-08 00:57:18 +00:00
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// FNSTCW16m - Store FP control world into i16 memory.
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FNSTCW16m,
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2008-05-09 21:53:03 +00:00
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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2008-05-29 08:22:04 +00:00
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VZEXT_LOAD,
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// VSHL, VSRL - Vector logical left / right shift.
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VSHL, VSRL
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2005-11-15 00:40:23 +00:00
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};
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}
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2008-01-29 19:34:22 +00:00
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFHWMask(SDNode *N);
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFLWMask(SDNode *N);
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to SHUFP*.
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bool isSHUFPMask(SDNode *N);
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/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool isMOVHLPSMask(SDNode *N);
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/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
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/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
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/// <2, 3, 2, 3>
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bool isMOVHLPS_v_undef_Mask(SDNode *N);
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
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bool isMOVLPMask(SDNode *N);
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
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/// as well as MOVLHPS.
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bool isMOVHPMask(SDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKH.
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bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
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/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
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/// <0, 0, 1, 1>
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bool isUNPCKL_v_undef_Mask(SDNode *N);
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/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
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/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
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/// <2, 2, 3, 3>
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bool isUNPCKH_v_undef_Mask(SDNode *N);
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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bool isMOVLMask(SDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool isMOVSHDUPMask(SDNode *N);
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool isMOVSLDUPMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of zero element.
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bool isSplatLoMask(SDNode *N);
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/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
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/// instructions.
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unsigned getShuffleSHUFImmediate(SDNode *N);
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
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/// instructions.
|
|
|
|
unsigned getShufflePSHUFHWImmediate(SDNode *N);
|
|
|
|
|
|
|
|
/// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
|
|
|
|
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
|
|
|
|
/// instructions.
|
|
|
|
unsigned getShufflePSHUFLWImmediate(SDNode *N);
|
|
|
|
}
|
|
|
|
|
2006-10-18 18:26:48 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2005-11-15 00:40:23 +00:00
|
|
|
// X86TargetLowering - X86 Implementation of the TargetLowering interface
|
|
|
|
class X86TargetLowering : public TargetLowering {
|
|
|
|
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
|
2006-09-08 06:48:29 +00:00
|
|
|
int RegSaveFrameIndex; // X86-64 vararg func register save area.
|
|
|
|
unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
|
|
|
|
unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
|
2005-11-15 00:40:23 +00:00
|
|
|
int BytesToPopOnReturn; // Number of arg bytes ret should pop.
|
|
|
|
int BytesCallerReserves; // Number of arg bytes caller makes.
|
2007-10-11 19:40:01 +00:00
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
public:
|
2008-05-14 01:58:56 +00:00
|
|
|
explicit X86TargetLowering(X86TargetMachine &TM);
|
2005-11-15 00:40:23 +00:00
|
|
|
|
Much improved pic jumptable codegen:
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43924 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-09 01:32:10 +00:00
|
|
|
/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
|
|
|
|
/// jumptable.
|
|
|
|
SDOperand getPICJumpTableRelocBase(SDOperand Table,
|
|
|
|
SelectionDAG &DAG) const;
|
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
// Return the number of bytes that a function should pop when it returns (in
|
|
|
|
// addition to the space used by the return address).
|
|
|
|
//
|
|
|
|
unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
|
|
|
|
|
|
|
|
// Return the number of bytes that the caller reserves for arguments passed
|
|
|
|
// to this function.
|
|
|
|
unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
|
|
|
|
|
2007-02-26 04:01:25 +00:00
|
|
|
/// getStackPtrReg - Return the stack pointer register we are using: either
|
|
|
|
/// ESP or RSP.
|
|
|
|
unsigned getStackPtrReg() const { return X86StackPtr; }
|
2008-01-23 23:17:41 +00:00
|
|
|
|
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
|
|
/// that contains are placed at 16-byte boundaries while the rest are at
|
|
|
|
/// 4-byte boundaries.
|
|
|
|
virtual unsigned getByValTypeAlignment(const Type *Ty) const;
|
2008-05-15 08:39:06 +00:00
|
|
|
|
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
2008-05-15 22:13:02 +00:00
|
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
|
|
/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
|
2008-05-15 08:39:06 +00:00
|
|
|
/// determining it.
|
|
|
|
virtual
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
|
|
|
|
bool isSrcConst, bool isSrcStr) const;
|
2007-02-26 04:01:25 +00:00
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
|
|
///
|
|
|
|
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
|
2007-11-24 07:07:01 +00:00
|
|
|
/// ExpandOperation - Custom lower the specified operation, splitting the
|
|
|
|
/// value into two pieces.
|
|
|
|
///
|
|
|
|
virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
|
|
|
|
|
|
|
|
|
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-07 08:33:52 +00:00
|
|
|
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
|
2008-01-30 18:18:23 +00:00
|
|
|
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB);
|
2006-01-11 00:33:36 +00:00
|
|
|
|
2008-05-05 19:05:59 +00:00
|
|
|
|
2005-12-20 06:22:03 +00:00
|
|
|
/// getTargetNodeName - This method returns the name of a target specific
|
|
|
|
/// DAG node.
|
|
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
|
2008-03-10 15:42:14 +00:00
|
|
|
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
2008-06-06 12:08:01 +00:00
|
|
|
virtual MVT getSetCCResultType(const SDOperand &) const;
|
2008-03-10 15:42:14 +00:00
|
|
|
|
2006-02-16 21:11:51 +00:00
|
|
|
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
|
|
|
/// in Mask are known to be either zero or one and return them in the
|
|
|
|
/// KnownZero/KnownOne bitsets.
|
|
|
|
virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
|
2008-02-13 22:28:48 +00:00
|
|
|
const APInt &Mask,
|
2008-02-13 00:35:47 +00:00
|
|
|
APInt &KnownZero,
|
|
|
|
APInt &KnownOne,
|
2007-06-22 14:59:07 +00:00
|
|
|
const SelectionDAG &DAG,
|
2006-02-16 21:11:51 +00:00
|
|
|
unsigned Depth = 0) const;
|
2008-05-12 19:56:52 +00:00
|
|
|
|
|
|
|
virtual bool
|
|
|
|
isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
|
2006-02-16 21:11:51 +00:00
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
|
|
|
|
|
2007-03-25 02:14:49 +00:00
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
2006-07-11 02:54:03 +00:00
|
|
|
|
2006-01-31 19:43:35 +00:00
|
|
|
std::vector<unsigned>
|
2006-02-22 00:56:39 +00:00
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT) const;
|
2007-08-25 00:47:38 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
virtual const char *LowerXConstraint(MVT ConstraintVT) const;
|
2008-01-29 02:21:21 +00:00
|
|
|
|
2007-08-25 00:47:38 +00:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
|
|
|
virtual void LowerAsmOperandForConstraint(SDOperand Op,
|
|
|
|
char ConstraintLetter,
|
|
|
|
std::vector<SDOperand> &Ops,
|
2008-04-26 23:02:14 +00:00
|
|
|
SelectionDAG &DAG) const;
|
2006-10-31 20:13:11 +00:00
|
|
|
|
2006-10-18 18:26:48 +00:00
|
|
|
/// getRegForInlineAsmConstraint - Given a physical register constraint
|
|
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
|
|
/// register. This should only be used for C_Register constraints. On
|
|
|
|
/// error, this returns a register number of 0.
|
2006-07-31 23:26:50 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VT) const;
|
2006-07-31 23:26:50 +00:00
|
|
|
|
2007-03-30 23:15:24 +00:00
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
|
|
|
|
|
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43375 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-26 01:56:11 +00:00
|
|
|
/// isTruncateFree - Return true if it's free to truncate a value of
|
|
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
|
|
|
virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
|
2008-06-06 12:08:01 +00:00
|
|
|
virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
|
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43375 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-26 01:56:11 +00:00
|
|
|
|
2006-03-22 18:59:22 +00:00
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
2006-10-18 18:26:48 +00:00
|
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
|
|
|
|
/// values are assumed to be legal.
|
2008-06-06 12:08:01 +00:00
|
|
|
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const;
|
2006-04-20 08:58:49 +00:00
|
|
|
|
|
|
|
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
|
|
|
|
/// used by Targets can use this to indicate if there is a suitable
|
|
|
|
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
|
|
|
|
/// pool entry.
|
2008-04-09 20:09:42 +00:00
|
|
|
virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT EVT, SelectionDAG &DAG) const;
|
2008-03-05 01:30:59 +00:00
|
|
|
|
|
|
|
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
|
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
|
|
/// in order to save space and / or reduce runtime.
|
2008-06-06 12:08:01 +00:00
|
|
|
virtual bool ShouldShrinkFPConstant(MVT VT) const {
|
2008-03-05 01:30:59 +00:00
|
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
|
|
// shrink long double fp constant since fldt is very slow.
|
|
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
|
|
|
}
|
2007-10-11 19:40:01 +00:00
|
|
|
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
|
|
/// for tail call optimization. Target which want to do tail call
|
|
|
|
/// optimization should implement this function.
|
|
|
|
virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
|
|
|
|
SDOperand Ret,
|
|
|
|
SelectionDAG &DAG) const;
|
|
|
|
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
|
|
|
virtual const X86Subtarget* getSubtarget() {
|
|
|
|
return Subtarget;
|
2007-11-05 23:12:20 +00:00
|
|
|
}
|
|
|
|
|
2008-01-18 06:52:41 +00:00
|
|
|
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
|
|
|
|
/// computed in an SSE register, not on the X87 floating point stack.
|
2008-06-06 12:08:01 +00:00
|
|
|
bool isScalarFPTypeInSSEReg(MVT VT) const {
|
2008-01-18 06:52:41 +00:00
|
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
|
|
|
}
|
|
|
|
|
2005-11-15 00:40:23 +00:00
|
|
|
private:
|
2006-04-25 20:13:52 +00:00
|
|
|
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
|
|
|
/// make the right decision when generating code for different targets.
|
|
|
|
const X86Subtarget *Subtarget;
|
2008-05-14 01:58:56 +00:00
|
|
|
const X86RegisterInfo *RegInfo;
|
2006-04-25 20:13:52 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
/// X86StackPtr - X86 physical register used as stack ptr.
|
|
|
|
unsigned X86StackPtr;
|
2007-10-11 19:40:01 +00:00
|
|
|
|
2007-09-23 14:52:20 +00:00
|
|
|
/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
|
|
|
|
/// floating point ops.
|
|
|
|
/// When SSE is available, use it for f32 operations.
|
|
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
|
|
bool X86ScalarSSEf32;
|
|
|
|
bool X86ScalarSSEf64;
|
2008-01-29 19:34:22 +00:00
|
|
|
|
2007-02-25 08:59:22 +00:00
|
|
|
SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
|
|
|
|
unsigned CallingConv, SelectionDAG &DAG);
|
2008-01-29 19:34:22 +00:00
|
|
|
|
2007-09-14 15:48:13 +00:00
|
|
|
SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
|
|
|
|
const CCValAssign &VA, MachineFrameInfo *MFI,
|
2008-02-26 09:19:59 +00:00
|
|
|
unsigned CC, SDOperand Root, unsigned i);
|
2007-09-14 15:48:13 +00:00
|
|
|
|
2007-08-31 15:06:30 +00:00
|
|
|
SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
|
|
|
|
const SDOperand &StackPtr,
|
|
|
|
const CCValAssign &VA, SDOperand Chain,
|
|
|
|
SDOperand Arg);
|
|
|
|
|
2008-01-05 16:56:59 +00:00
|
|
|
// Call lowering helpers.
|
|
|
|
bool IsCalleePop(SDOperand Op);
|
2008-02-26 22:21:54 +00:00
|
|
|
bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
|
|
|
|
bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
|
2008-04-12 18:11:06 +00:00
|
|
|
SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
|
|
|
|
SDOperand Chain, bool IsTailCall, bool Is64Bit,
|
|
|
|
int FPDiff);
|
|
|
|
|
2008-01-05 16:56:59 +00:00
|
|
|
CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
|
|
|
|
NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
|
2007-10-11 19:40:01 +00:00
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|
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unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
|
2006-01-27 08:10:46 +00:00
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|
2007-11-24 07:07:01 +00:00
|
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std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
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SelectionDAG &DAG);
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2006-04-25 20:13:52 +00:00
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SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
|
2008-02-11 04:19:36 +00:00
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SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
|
2006-04-25 20:13:52 +00:00
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SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
|
2008-02-11 04:19:36 +00:00
|
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SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
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2006-04-25 20:13:52 +00:00
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SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
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2007-04-20 21:38:10 +00:00
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SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
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2006-04-25 20:13:52 +00:00
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SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
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2007-01-05 07:55:56 +00:00
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SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
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2007-09-29 00:00:36 +00:00
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SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
|
2006-04-25 20:13:52 +00:00
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SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
|
2006-05-25 00:59:30 +00:00
|
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|
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
|
2006-04-25 20:13:52 +00:00
|
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|
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
|
2007-04-17 09:20:00 +00:00
|
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|
SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
|
2006-04-26 01:20:17 +00:00
|
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|
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
|
2006-04-25 20:13:52 +00:00
|
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|
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
|
2008-05-10 01:26:14 +00:00
|
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|
SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG);
|
2007-03-02 23:16:35 +00:00
|
|
|
SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
|
2006-04-25 20:13:52 +00:00
|
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|
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
|
2007-01-29 22:58:52 +00:00
|
|
|
SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
|
2007-07-14 14:06:15 +00:00
|
|
|
SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
|
2007-07-27 20:02:49 +00:00
|
|
|
SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
|
2008-01-31 00:41:03 +00:00
|
|
|
SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
|
2007-12-14 02:13:44 +00:00
|
|
|
SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
|
2008-06-25 08:15:39 +00:00
|
|
|
SDOperand LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG);
|
2007-11-24 07:07:01 +00:00
|
|
|
SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
|
|
|
|
SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
|
2008-06-25 08:15:39 +00:00
|
|
|
SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
|
|
|
|
SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG);
|
2008-05-05 19:05:59 +00:00
|
|
|
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
|
|
|
SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
|
|
|
|
SDOperand Chain,
|
|
|
|
SDOperand Dst, SDOperand Src,
|
|
|
|
SDOperand Size, unsigned Align,
|
2008-04-28 17:15:20 +00:00
|
|
|
const Value *DstSV, uint64_t DstSVOff);
|
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
|
|
|
SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
|
|
|
|
SDOperand Chain,
|
|
|
|
SDOperand Dst, SDOperand Src,
|
|
|
|
SDOperand Size, unsigned Align,
|
|
|
|
bool AlwaysInline,
|
2008-04-28 17:15:20 +00:00
|
|
|
const Value *DstSV, uint64_t DstSVOff,
|
|
|
|
const Value *SrcSV, uint64_t SrcSVOff);
|
2008-05-05 19:05:59 +00:00
|
|
|
|
|
|
|
/// Utility function to emit atomic bitwise operations (and, or, xor).
|
|
|
|
// It takes the bitwise instruction to expand, the associated machine basic
|
|
|
|
// block, and the associated X86 opcodes for reg/reg and reg/imm.
|
|
|
|
MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
|
|
|
|
MachineInstr *BInstr,
|
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned regOpc,
|
2008-06-14 05:48:15 +00:00
|
|
|
unsigned immOpc,
|
|
|
|
bool invSrc = false);
|
2008-05-05 19:05:59 +00:00
|
|
|
|
|
|
|
/// Utility function to emit atomic min and max. It takes the min/max
|
|
|
|
// instruction to expand, the associated basic block, and the associated
|
|
|
|
// cmov opcode for moving the min or max value.
|
|
|
|
MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
|
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned cmovOpc);
|
2005-11-15 00:40:23 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif // X86ISELLOWERING_H
|