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Commit Graph

3393 Commits

Author SHA1 Message Date
Craig Topper
cf458e91da Add missing index comments to the left side of the DAG ISel matcher table for each individual case of SwitchOpcode/Type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-22 23:18:50 +00:00
Benjamin Kramer
0d293e45b6 Provide basic type safety for array_pod_sort comparators.
This makes using array_pod_sort significantly safer. The implementation relies
on function pointer casting but that should be safe as we're dealing with void*
here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-22 14:09:50 +00:00
Tim Northover
107cfa2169 TableGen: fix constness of new comparison function.
libc++ didn't seem to like a non-const call operator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 17:33:40 +00:00
Tim Northover
03f9197d62 TableGen: give asm match classes deterministic order.
TableGen was sorting the entries in some of its internal data
structures by pointer. This order filtered through to the final
matching table and affected the diagnostics produced on bad assembly
occasionally.

It also turns out STL algorithms are ridiculously easy to misuse on
containers with custom order methods. (No bugs before, or now that I
know of, but plenty in the middle).

This should fix the sanitizer bot, which ends up with weird pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 16:43:19 +00:00
Tim Northover
6dd670af75 AsmMatcher: emit subtarget feature enum in deterministic order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 16:43:16 +00:00
Benjamin Kramer
94ee55d4b3 Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 22:04:42 +00:00
Joey Gouly
715d98d657 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 10:28:05 +00:00
Benjamin Kramer
209a8c8e35 llvm-tblgen: Mangle operand replacements into the strings in printAliasInstr.
Cuts down the bloat in the AArch64 asm writer a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 15:42:16 +00:00
Benjamin Kramer
71faecf16f llvm-tblgen: Stabilize subreg index tables.
Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 11:22:26 +00:00
Vincent Lejeune
d8f2eb301c TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-03 19:43:28 +00:00
Jim Grosbach
ff372dc18d Tidy up. Comment grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 22:41:43 +00:00
Jim Grosbach
dd46230062 Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 22:41:39 +00:00
Craig Topper
aae60d1dc4 Move StringToOffsetTable into the TableGen include directory so I can use it in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 05:09:55 +00:00
Rui Ueyama
2957273b88 Option parsing: support case-insensitive option matching.
Re-submitting r189416 with fix for Windows build on where strcasecmp is not defined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 20:04:31 +00:00
Craig Topper
862b504201 Add missing include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 07:03:02 +00:00
Rui Ueyama
1997734e37 Revert "Option parsing: support case-insensitive option matching." as it broke Windows buildbot.
This reverts r189416.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:02:06 +00:00
Rui Ueyama
055f4e99ff Option parsing: support case-insensitive option matching.
Link.exe's command line options are case-insensitive. This patch
adds a new attribute to OptTable to let the option parser to compare
options, ignoring case.

Command lines are generally case-insensitive on Windows. CL.exe is an
exception. So this new attribute should be useful for other commands
running on Windows.

Differential Revision: http://llvm-reviews.chandlerc.com/D1485

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 23:47:01 +00:00
Jakob Stoklund Olesen
d93969c32a Add an OtherPreserved field to the CalleeSaved TableGen class.
This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.

This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 02:25:47 +00:00
Elena Demikhovsky
1765e74c15 AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:18:28 +00:00
Tim Northover
f7ab3a84b3 ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 09:57:11 +00:00
Aaron Ballman
3369599db2 Fixing a warning about control reaching the end of a non-void function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 01:43:31 +00:00
Jack Carter
0fe3792a2f [Mips][msa] Value types for MSA support.
Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, 
and CodeGenTarget.cpp

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 22:34:26 +00:00
Richard Sandiford
1f85736c97 Revert r188164: Stablize MCK_Reg ordering in AsmMatcherEmitter
Apparently caused a failure on Darwin


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:57:51 +00:00
Richard Sandiford
dfb5ceae90 Stablize MCK_Reg ordering in AsmMatcherEmitter
clang bootstraps intermittently failed for me due a difference in
the MCK_Reg ordering in ARMGenAsmMatcher.inc.  E.g. in my latest
run the stage 1 and stage 3 versions were the same but the stage 2
one was different (though still functionally correct).  This meant
that the .o comparison failed.

MCK_Regs were assigned by iterating over a std::set< std::set<Record*> >,
and since std::set is sorted lexicographically, the order depended on the
order of the pointer values.  This patch replaces the pointer ordering
with LessRecordByID.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:39:45 +00:00
Reid Kleckner
47cfec0284 Remove some std stream usage from Support and TableGen
LLVM's coding standards recommend raw_ostream and MemoryBuffer for
reading and writing text.

This has the side effect of allowing clang to compile more of Support
and TableGen in the Microsoft C++ ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:51:21 +00:00
Vladimir Medic
588f408b95 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:25:27 +00:00
Hans Wennborg
a15d5db7f2 Option parsing: remove non-SUPPORT_ALIASARGS fall-back
The clients of this code have been updated to all support AliasArgs.

This depends on Clang r187538 and lld r187541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 23:28:51 +00:00
Hans Wennborg
9dd8c0cffe Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.

For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".

This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).

Differential Revision: http://llvm-reviews.chandlerc.com/D1245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:44:41 +00:00
Andrew Trick
d3d751804c comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:54 +00:00
Tom Stellard
5519dc9de8 Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:08 +00:00
Vincent Lejeune
2ca1e4a39c TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187511 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:20 +00:00
Andrew Trick
c408335bf5 Fix register pressure tables on ARM.
The heuristic that merges register pressure sets was bogus for ARM's S/D regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:31 +00:00
Andrew Trick
bbf20d4d4a Add tracing to the tblgen register pressure table generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:28 +00:00
Craig Topper
d953bcd487 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187333 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 21:28:02 +00:00
Elena Demikhovsky
dc8a318f44 fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:45:12 +00:00
Elena Demikhovsky
c18f4efc5d Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:28:38 +00:00
Aaron Ballman
a946190351 Using a different loop induction variable than the enclosing scope. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 22:09:31 +00:00
Justin Holewinski
563a9cf7ba Fix a bug in TableGen where the intrinsic function name recognizer could mis-identify names if one was a prefix substring of the other
For two intrinsics 'llvm.nvvm.texsurf.handle' and 'llvm.nvvm.texsurf.handle.internal',
TableGen was emitting matching code like:

  if (Name.startswith("llvm.nvvm.texsurf.handle")) ...
  if (Name.startswith("llvm.nvvm.texsurf.handle.internal")) ...

We can never match "llvm.nvvm.texsurf.handle.internal" here because it will
always be erroneously matched by the first condition.

The fix is to sort the intrinsic names and emit them in reverse order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 12:32:00 +00:00
Andrew Trick
bba663e30a RegPressure: Order the "pressure sets" by number of regunits per set.
This lets heuristics easily pick the most important set to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 07:26:29 +00:00
Craig Topper
f63ef914b6 Split generated asm mnemonic matching table into a separate table for each asm variant.
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 07:33:14 +00:00
Craig Topper
349d6a70a1 Remove 'else' after 'return'. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:27:36 +00:00
Craig Topper
00f94955ef Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:25:00 +00:00
Vladimir Medic
9273151c3b This patch allows targets to define weather the instruction mnemonics in asm matcher tables will contain '.' character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186388 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 09:22:38 +00:00
Aaron Ballman
54911a5303 Teaching llvm-tblgen to not emit a switch statement when there are no case statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 16:53:32 +00:00
Craig Topper
3c70fcf02b Add 'const' qualifier to some arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 08:02:13 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Nick Lewycky
dc89737bcd Extend 'readonly' and 'readnone' to work on function arguments as well as
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 00:29:58 +00:00
Craig Topper
6227d5c690 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 01:31:24 +00:00
Chad Rosier
b7110cf5b5 Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.

The current algorithm, LessRecord, uses the StringRef compare_numeric
function.  This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:

  T1
  T1_W
  T1_X
  T1_XYZW
  T1_Y
  T1_Z
  T2
  T2_W
  T2_X
  T2_XYZW
  T2_Y
  T2_Z

In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another.  However, in other parts
of the register bank, the scaling factors are different:

dEnum/dN = 5:
  KC0_128_W
  KC0_128_X
  KC0_128_XYZW
  KC0_128_Y
  KC0_128_Z
  KC0_129_W
  KC0_129_X
  KC0_129_XYZW
  KC0_129_Y
  KC0_129_Z

The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'.  This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1.  For example, the registers are now sorted as
follows:

  T1
  T2
  T3
  ...
  T0_W
  T1_W
  T2_W
  ...
  T0_X
  T1_X
  T2_X
  ...
  KC0_128_W
  KC0_129_W
  KC0_130_W
  ...

For the Mips and R600 I see a 19% and 6% reduction in size, respectively.  I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes).  I suspect there will be even
greater wins for targets with larger register files.

Patch reviewed by Jakob.
rdar://14006013


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-27 19:38:13 +00:00
Tom Stellard
898b9f020d TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.

In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.

For example, if you have an instruction like:

def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;

You can look up the operand indices using the new function, like this:

Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst)  => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2

The operand names are case sensitive, so $dst and $DST are considered
different operands.

This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values.  These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 21:22:09 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 17:08:10 +00:00
Andrew Trick
a3d82ce19f Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:06 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:49:57 +00:00
Benjamin Kramer
aca93cf44f tblgen: Assert that InstRWs doesn't grows when we don't expect it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 20:19:35 +00:00
Benjamin Kramer
068ecc15c0 tblgen: always lookup values from the original vector as it could be grown under our feet.
PR16281.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 15:20:23 +00:00
Arnold Schwaighofer
0efc78257b CodeGenSchedule: Use resize instead of copying a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:04:30 +00:00
Arnold Schwaighofer
45dc03287e CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerous
The element passed to push_back is not copied before the vector reallocates.
The client needs to copy the element first before passing it to push_back.

No test case, will be tested by follow-up swift scheduler model change (it
segfaults without this change).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 23:23:14 +00:00
Jakub Staszak
239f8a4e11 Remove unimplemented definition. Found using [-Wunused-member-function].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:52:45 +00:00
Arnold Schwaighofer
fcce70ad52 SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

Reapply of 183255, I don't think this was causing the tablegen segfault on linux
testers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183311 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 14:06:50 +00:00
Andrew Trick
d7aad34bcb Fix a tblgen subtargetemitter bug, for future Swift support.
This fixes some of the ridiculously complex code for optimizing the
machine model tables that are shared among all processors of a given
target. A9 and Swift both use the "special" feature that maps old
itinerary classes to new machine model defs. They map different
overlapping subsets of instructions, which wasn't handled correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183302 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 06:55:20 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
54d63ccdb7 SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:41 +00:00
Ahmed Bougacha
23ed37a6b7 Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:45:26 +00:00
Ahmed Bougacha
bed2308186 Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 17:08:36 +00:00
Chad Rosier
2275cfd75b Remove the MCRegAliasIterator tables and compute the aliases dynamically.
The size reduction in the RegDiffLists are rather dramatic.  Here are a few
size differences for MCTargetDesc.o files (before and after) in bytes:
R600 - 36160B - 11184B - 69% reduction
ARM - 28480B - 8368B - 71% reduction
Mips - 816B - 576B - 29% reduction

One side effect of dynamically computing the aliases is that the iterator does
not guarantee that the entries are ordered or that duplicates have been removed.
The documentation implies this is a safe assumption and I found no clients that
requires these attributes (i.e., strict ordering and uniqueness).

My local LNT tester results showed no execution-time failures or significant
compile-time regressions (i.e., beyond what I would consider noise) for -O0g,
-O2 and -O3 runs on x86_64 and i386 configurations.
rdar://12906217


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28 18:08:48 +00:00
Bill Schmidt
d35da5055b Recognize ValueType operands in source patterns for fast-isel.
Currently the fast-isel table generator recognizes registers, register
classes, and immediates for source pattern operands.  ValueType
operands are not recognized.  This is not a problem for existing
targets with fast-isel support, but will not work for targets like
PowerPC and SPARC that use types in source patterns.

The proposed patch allows ValueType operands and treats them in the
same manner as register classes.  There is no convenient way to map
from a ValueType to a register class, but there's no need to do so.
The table generator already requires that all types in the source
pattern be identical, and we know the register class of the output
operand already.  So we just assign that register class to any
ValueType operands we encounter.

No functional effect on existing targets.  Testing deferred until the
PowerPC target implements fast-isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 20:45:11 +00:00
Jakob Stoklund Olesen
997fa623fc Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 18:03:08 +00:00
Ulrich Weigand
d999062f31 Handle tied sub-operands in AsmMatcherEmitter
The problem this patch addresses is the handling of register tie
constraints in AsmMatcherEmitter, where one operand is tied to a
sub-operand of another operand.  The typical scenario for this to
happen is the tie between the "write-back" register of a pre-inc
instruction, and the base register sub-operand of the memory address
operand of that instruction.

The current AsmMatcherEmitter code attempts to handle tied
operands by emitting the operand as usual first, and emitting
a CVT_Tied node when handling the second (tied) operand.  However,
this really only works correctly if the tied operand does not
have sub-operands (and isn't a sub-operand itself).  Under those
circumstances, a wrong MC operand list is generated.

In discussions with Jim Grosbach, it turned out that the MC operand
list really ought not to contain tied operands in the first place;
instead, it ought to consist of exactly those operands that are
named in the AsmString.  However, getting there requires significant
rework of (some) targets.

This patch fixes the immediate problem, and at the same time makes
one (small) step in the direction of the long-term solution, by
implementing two changes:

1. Restricts the AsmMatcherEmitter handling of tied operands to
   apply solely to simple operands (not complex operands or
   sub-operand of such).

This means that at least we don't get silently corrupt MC operand
lists as output.  However, if we do have tied sub-operands, they
would now no longer be handled at all, except for:

2. If we have an operand that does not occur in the AsmString,
   and also isn't handled as tied operand, simply emit a dummy
   MC operand (constant 0).

This works as long as target code never attempts to access
MC operands that do no not occur in the AsmString (and are
not tied simple operands), which happens to be the case for
all targets where this situation can occur (ARM and PowerPC).

[ Note that this change means that many of the ARM custom
  converters are now superfluous, since the implement the
  same "hack" now performed already by common code. ]

Longer term, we ought to fix targets to never access *any*
MC operand that does not occur in the AsmString (including
tied simple operands), and then finally completely remove
all such operands from the MC operand list.

Patch approved by Jim Grosbach.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-27 18:48:23 +00:00
Andrew Trick
a809c8db3d Machine model: Generate table entries for super-resources.
Super-resources and resource groups are two ways of expressing
overlapping sets of processor resources. Now we generate table entries
the same way for both so the scheduler never needs to explicitly check
for super-resources.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:16 +00:00
Andrew Trick
e30f32a69b Machine model: verify well-formed processor resource groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:14 +00:00
Andrew Trick
6982bdd119 Machine model: rewrite a tablegen loop to avoid comparing record pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:11 +00:00
Chad Rosier
88eb89b89f [asm parser] Add support for predicating MnemonicAlias based on the assembler
variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 22:35:36 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:52:28 +00:00
Andrew Trick
bc4de7cec1 Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:08:31 +00:00
Dan Gohman
1cbd401756 Revert r178166. According to Howard, this code is actually ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 00:13:08 +00:00
Dan Gohman
dcdc0faf59 Avoid undefined behavior from passing a std::vector's own contents
in as an argument to push_back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 18:44:56 +00:00
Andrew Trick
82e7c4f533 TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 21:36:39 +00:00
Dave Zarzycki
9b3939983f x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:43 +00:00
Jakob Stoklund Olesen
8e3cb3ee0c Allow types to be omitted in output patterns.
This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 19:37:00 +00:00
Jakob Stoklund Olesen
19209960b6 Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 00:56:16 +00:00
Jakob Stoklund Olesen
f0a804df49 Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:35:01 +00:00
Jakob Stoklund Olesen
7a42fb3b6e Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 18:08:44 +00:00
Sean Silva
426db657da Add TableGen ctags(1) emitter and helper script.
To use this in conjunction with exuberant ctags to generate a single
combined tags file, run tblgen first and then
  $ ctags --append [...]

Since some identifiers have corresponding definitions in C++ code,
it can be useful (if using vim) to also use cscope, and
  :set cscopetagorder=1
so that
  :tag X
will preferentially select the tablegen symbol, while
  :cscope find g X
will always find the C++ symbol.

Patch by Kevin Schoedel!

(a couple small formatting changes courtesy of clang-format)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21 23:40:38 +00:00
Ulrich Weigand
ec8d1a5b72 Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).

Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.

This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.

This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):

  def STWU  : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
                    "stwu $rS, $dst", LdStStoreUpd, []>,
                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;

  def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
            (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;

Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.

Approved by Jakob Stoklund Olesen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19 19:51:09 +00:00
Andrew Trick
02fec34de1 TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 20:42:25 +00:00
Jakob Stoklund Olesen
4c16916883 Extract a method.
This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 04:08:07 +00:00
Jakob Stoklund Olesen
26369a930c Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17 17:26:09 +00:00
Andrew Trick
1ab961f6d3 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 18:58:55 +00:00
Jakob Stoklund Olesen
64110ffc9e Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 22:51:13 +00:00
Andrew Trick
157c6c4e8e Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 22:47:01 +00:00
Andrew Trick
1754aca83a MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:21:50 +00:00
Kevin Enderby
12dccaed9c Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 21:17:13 +00:00
Andrew Trick
c812110023 MIsched machine model: tablegen subtarget emitter improvement.
Fix the way resources are counted. I'm taking some time to cleanup the
way MachineScheduler handles in-order machine resources. Eventually
we'll need more PPC/Atom test cases in tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 23:31:26 +00:00
Michael J. Spencer
f15fe8195b [TableGen] Fix ICE on MSVC 2012 Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26 21:29:47 +00:00
Jyotsna Verma
1912c7624a Fix for bug 15246 -- out-of-bound error in the TableGen backend, CodeGenMapTable.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 17:58:13 +00:00
David Peixotto
af7c042af1 PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 19:21:47 +00:00
Kay Tiong Khoo
6c3daabc3e Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 00:19:12 +00:00
Jim Grosbach
fa05def52c Allow targets to add custom asm operand matching logic.
For example, ARM has several instructions with a literal '' immediate in the syntax
that's not represented as an actual operand. The asm matcher is expected a token
operand, but the parser will have created an immediate operand. This is currently
handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but
will be better handled by this hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 06:00:06 +00:00
Eli Bendersky
d07c2a5fa1 Fix comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:53:11 +00:00
Jack Carter
37ef65b9c1 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 08:32:10 +00:00
Andrew Trick
d9a4f0cbd2 MachineModel: Inconsequential TableGen SubtargetEmitter fix.
Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 03:19:54 +00:00
Jakob Stoklund Olesen
f79c5e2f84 Clarify intent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 17:56:23 +00:00
Tim Northover
72062f5744 Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.

This initial commit should have support for:
    + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
      (except the late addition CRC instructions).
    + CodeGen features required for C++03 and C99.
    + Compilation for the "small" memory model: code+static data <
      4GB.
    + Absolute and position-independent code.
    + GNU-style (i.e. "__thread") TLS.
    + Debugging information.

The principal omission, currently, is performance tuning.

This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.

Further reviews would be gratefully received.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 12:12:40 +00:00
Bill Wendling
e3617247a0 Use the AttributeSet instead of AttributeWithIndex.
In the future, AttributeWithIndex won't be used anymore. Besides, it exposes the
internals of the AttributeSet to outside users, which isn't goodness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 03:25:05 +00:00
Chad Rosier
1c99a7f489 [ms-inline asm] Address the FIXME in AsmParser.cpp.
// FIXME: Constraints are hard coded to 'm', but we need an 'r'
// constraint for addressof.  This needs to be cleaned up!

Test cases are already in place.  Specifically,
clang/test/CodeGen/ms-inline-asm.c t15(), t16(), and t24().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15 23:07:53 +00:00
Michael Ilseman
4d0b4a45dc Support for half intrinsics. Pushes MMX into slower encoding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 01:45:05 +00:00
Jordan Rose
b50df4a3df TableGen: Keep track of superclass reference ranges.
def foo : bar;
          ~~~

This allows us to produce more precise diagnostics about a certain
superclass, and even provide fixits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 18:50:11 +00:00
Tim Northover
12da505d93 Remove locale-dependence of enum mangling and use existing function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 16:47:31 +00:00
Tim Northover
88abcde3b4 Make TableGen mangle operand method names before putting in enum.
The purpose of this patch is to allow PredicateMethods to be set to something
like "isUImm<8>", calling a C++ template method to reduce code duplication. For
this to work, the PredicateMethod must be mangled into a valid C++ identifier
for insertion into an enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 15:17:36 +00:00
Tim Northover
7bf2e1b9ef Check whether MCInst operand isImm before calling getImm.
When processing possible aliases, TableGen assumes that if an operand *can* be
an immediate, then it always *will* be. This is incorrect for the AArch64
backend. This patch inserts a check in the generated code to make sure isImm is
true first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 13:32:04 +00:00
Andrew Trick
47579cf390 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 03:36:49 +00:00
Chandler Carruth
7f00f87767 Sort a few more #include lines in tools/... unittests/... and utils/...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 10:26:28 +00:00
NAKAMURA Takumi
fc093def2d TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
Reported by Yang Yongyong, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:43:14 +00:00
Elena Demikhovsky
94d7ab7da4 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 10:03:57 +00:00
Bill Wendling
629fb82419 Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of attribute instead of the value of the attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 00:37:52 +00:00
Richard Smith
8efd0f00be Fix an uninitialized member variable, found by -fsanitize=bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:05:39 +00:00
Jim Grosbach
fbf3b4a076 MC: Add MCInstrDesc::mayAffectControlFlow() method.
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:53 +00:00
Roman Divacky
759e3fa641 Remove edis - the enhanced disassembler. Fixes PR14654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 19:55:47 +00:00
Bill Wendling
034b94b170 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 07:18:57 +00:00
Anshuman Dasgupta
079e0819bc Fix PR14568: Avoid the DFA packetizer from making an invalid read
beyond array bounds.

No test case since I cannot reproduce an ICE with this bug. According
to Carlos -- the bug reporter -- a segfault occurs only when LLVM is
compiled with a specific version of GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10 22:45:57 +00:00
Bill Wendling
99faa3b4ec s/AttrListPtr/AttributeSet/g to better label what this class is going to be in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07 23:16:57 +00:00
Andrew Trick
553c42cefc RegisterPresssureTracker: Track live physical register by unit.
This is much simpler to reason about, more efficient, and
fixes some corner cases involving implicit super-register defs.
Fixed rdar://12797931.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 21:37:42 +00:00
Andrew Trick
eca1fcf3d2 RegisterPressure API. Add support for physical register units.
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).

Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 06:47:12 +00:00
Michael J. Spencer
96a564f2be Copy clang/Driver/<Option parsing stuff> to llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05 00:29:32 +00:00
Chandler Carruth
4ffd89fa4d Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 10:37:14 +00:00
Jakob Stoklund Olesen
e26e8a64ab Add an MCPhysReg typedef to replace naked uint16_t.
Use this type for arrays of physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29 02:39:28 +00:00
Jakob Stoklund Olesen
a9fa4fd973 Remove all references to TargetInstrInfoImpl.
This class has been merged into its super-class TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28 02:35:17 +00:00
Bill Wendling
0976e00fd1 Make the AttrListPtr object a part of the LLVMContext.
When code deletes the context, the AttributeImpls that the AttrListPtr points to
are now invalid. Therefore, instead of keeping a separate managed static for the
AttrListPtrs that's reference counted, move it into the LLVMContext and delete
it when deleting the AttributeImpls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20 05:09:20 +00:00
Weiming Zhao
e56764bad1 Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 21:55:34 +00:00
Evandro Menezes
f1adbfe4e2 Fix issue with invalid flat operand number
Avoid iterating over list of operands beyond the number of operands in it.

PS: this fixes issue with revision .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 21:27:03 +00:00
Evandro Menezes
f1bb42152a Fix issue with invalid flat operand number
Avoid iterating over list of operands beyond the number of operands in it.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 20:29:37 +00:00
Michael Liao
be02a90de1 Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08 07:28:54 +00:00
Rafael Espindola
322ff88345 Fix a build problem with xlc. The error message was
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+".
"../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate.

Patch by Kai.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02 20:57:36 +00:00
Jakob Stoklund Olesen
ad0b3b21e3 Generate a table-driven version of TRI::composeSubRegIndices().
Explicitly allow composition of null sub-register indices, and handle
that common case in an inlinable stub.

Use a compressed table implementation instead of the previous nested
switches which generated pretty bad code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01 00:32:10 +00:00
Kaelyn Uhrain
50a6102397 Don't return false when the function's return type is a pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 21:25:08 +00:00
Joerg Sonnenberger
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
David Blaikie
a8a0a155de Remove unused member & unnecessary semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 17:04:55 +00:00
NAKAMURA Takumi
0b031cb717 llvm/utils/TableGen/CMakeLists.txt: Update corresponding to r166685.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 15:57:56 +00:00
Sebastian Pop
becdf4d7cd add TableGen support to create relationship maps between instructions
Relationship maps are represented as InstrMapping records which are parsed by
TableGen and the information is used to construct mapping tables to represent
appropriate relations between instructions. These tables are emitted into
XXXGenInstrInfo.inc file along with the functions to query them.

Patch by Jyotsna Verma <jverma@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 15:54:06 +00:00
Joerg Sonnenberger
2c6d71388f Don't use stack unwinding to provide the location information for
SetTheory, but pass down the location explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24 22:03:59 +00:00
Lang Hames
64486737d5 Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src",
rather than "$src = $dst").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-20 22:44:13 +00:00
Bill Wendling
07aae2e7d5 Add an enum for the return and function indexes into the AttrListPtr object. This gets rid of some magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 07:29:08 +00:00
Bill Wendling
cb3de0bc80 Attributes Rewrite
Convert the internal representation of the Attributes class into a pointer to an
opaque object that's uniqued by and stored in the LLVMContext object. The
Attributes class then becomes a thin wrapper around this opaque
object. Eventually, the internal representation will be expanded to include
attributes that represent code generation options, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 04:46:55 +00:00
Chad Rosier
6e006d3de8 [ms-inline asm] Use the new API introduced in r165830 in lieu of the
MapAndConstraints vector.  Also remove the unused Kind argument.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 22:53:36 +00:00
Richard Trieu
5628920346 Change (!list.size() == 0) to (!list.empty()). No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 17:57:35 +00:00
Sean Silva
ed84062812 Remove unnecessary classof()'s
isa<> et al. automatically infer when the cast is an upcast (including a
self-cast), so these are no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 23:30:49 +00:00
Chad Rosier
fcb5e95c31 Remove extra semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 22:25:56 +00:00
Sean Silva
fff8287f10 tblgen: Compile TableGen without RTTI.
TableGen no longer needs RTTI!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:27:18 +00:00
Sean Silva
8b43dbf9ea tblgen: Move mini Type hierarchy to LLVM-style RTTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:49 +00:00
Sean Silva
3f7b7f8ce0 tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:47 +00:00
Sean Silva
6cfc806a6b tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:43 +00:00
Bill Wendling
11d00420e4 Pass into the AttributeWithIndex::get method an ArrayRef of attribute
enums. These are then created via the correct Attributes creation method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 06:13:42 +00:00
Andrew Trick
dbe6d43dfa TableGen subtarget emitter cleanup.
Consistently evaluate Aliases and Sequences recursively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:13 +00:00
Andrew Trick
6312cb0997 misched: Generate IsBuffered flag for machine resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:04 +00:00
Micah Villmow
791cfc211a Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165403 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:39:34 +00:00
Chad Rosier
9ba9d4d76b [ms-inline asm] Add a few typedefs to simplify future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 18:41:14 +00:00
Sean Silva
736ceace11 tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of
these uses are actually more like isa<> or cast<>, and will be changed
to the semanticaly appropriate one in a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 03:31:58 +00:00
Andrew Trick
13745262a8 Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:32 +00:00
Andrew Trick
2062b1260f TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:28 +00:00
Andrew Trick
fe05d98c25 Cleanup TableGen subtarget emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:25 +00:00
Chad Rosier
d494a3bfc5 [ms-inline asm] Default to the 'm' constraint. This matches the behavior of the
MSVC compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 22:18:38 +00:00
Sean Silva
9e21138ab7 tblgen: Migrate llvm-tblgen to new TableGenMain API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 21:29:19 +00:00
Chad Rosier
c69bb70deb Fix 80-column violations. Cleanup whitespace in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02 00:25:57 +00:00
Chad Rosier
22685876ed [ms-inline asm] Add the convertToMapAndConstraints() function that is used to
map constraints and MCInst operands to inline asm operands.  This replaces the
getMCInstOperandNum() function.

The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01 23:45:51 +00:00
Sylvestre Ledru
94c22716d6 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 10:14:43 +00:00
Sylvestre Ledru
7e2c793a2b Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 09:59:43 +00:00
Chad Rosier
2590c2e1e9 Rather then have a wrapper function, have tblgen instantiate the implementation.
Also remove an unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24 22:57:55 +00:00
Chad Rosier
00796a1b15 Rather then have a wrapper function, have tblgen instantiate the implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24 19:32:29 +00:00
Andrew Trick
9264988311 Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22 02:24:21 +00:00
Chad Rosier
d717a066c6 [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 22:21:26 +00:00
Chad Rosier
6018944afd Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 19:25:59 +00:00
Micah Villmow
3e9b6db60f Add in new data types that are used by AMDIL/ANL among others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 22:47:07 +00:00
Owen Anderson
eb79b545fc Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 22:15:06 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 06:37:45 +00:00
Andrew Trick
3b8fb648c6 SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 04:43:19 +00:00
Sean Silva
b2df610b44 Iterate deterministicaly over ClassInfo*'s
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:03 +00:00
Sean Silva
decfdf548b Iterate deterministically over register classes
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:01 +00:00
Sean Silva
90fee07298 Refactor Record* by-ID comparator to Record.h
This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:00 +00:00
Craig Topper
3a36444366 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 07:02:21 +00:00
Craig Topper
fee7f01d1e Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 06:10:45 +00:00
Andrew Trick
34aadd6334 Replaced ReInitMCSubtargetInfo with InitMCProcessor.
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 05:33:15 +00:00
Andrew Trick
e076bb1e93 comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 04:03:30 +00:00
Andrew Trick
e3dbc98a4f TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:55:55 +00:00
Andrew Trick
4d2d1c49d7 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:41:43 +00:00
Andrew Trick
ee290ba35a TableGen subtarget emitter. Remove unnecessary header dependence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:32:57 +00:00
Andrew Trick
e127dfd0b1 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:18:56 +00:00
Craig Topper
b198f5c897 Mark asm matcher conversion table as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 01:41:49 +00:00
Craig Topper
be480ff607 Fix typo in comment. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 01:13:36 +00:00
Andrew Trick
e4095f95ac Backout the wrong subtarget emitter fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:14:15 +00:00
Andrew Trick
f23ddf54ea Fix release build after reverting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:05:04 +00:00
Andrew Trick
e1b5328717 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:00:42 +00:00
Andrew Trick
a2a47d1c50 InitMCProcessor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:12 +00:00
Andrew Trick
5d94082143 comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:04 +00:00
Andrew Trick
41be51b72c TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:01 +00:00
Andrew Trick
021ba269b2 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:58 +00:00
Andrew Trick
db7afac457 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:55 +00:00
Andrew Trick
544c88039f TableGen subtarget emitter. Format and emit data tables for the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:50 +00:00
Andrew Trick
52c3a1d654 TableGen subtarget emitter. Generate data tables for the new machine model.
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:48 +00:00
Andrew Trick
40096d2693 TableGen subtarget emitter. Emit processor resources for the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:45 +00:00
Andrew Trick
bc4ff6e3cf TableGen subtarget parser: Add getProcResourcesIdx().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:43 +00:00