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295 Commits

Author SHA1 Message Date
Bob Wilson
a7fcb9b840 Fix a tab. Thanks to Johnny Chen for pointing it out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83973 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-13 15:27:23 +00:00
Dan Gohman
59ac57153b Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83688 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-09 23:28:27 +00:00
Bob Wilson
a3e8bf8412 Fix a comment typo. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-06 20:18:46 +00:00
Evan Cheng
0d92f5f768 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 08:22:27 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:33:39 +00:00
Jim Grosbach
c732adf3a1 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-30 01:35:11 +00:00
Evan Cheng
5adb66a646 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 09:14:39 +00:00
Anton Korobeynikov
b0d8d78138 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. 
Disable rematting of it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-28 07:26:46 +00:00
Anton Korobeynikov
6a2fa325c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-27 23:52:58 +00:00
Evan Cheng
7995ef3b18 Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 01:47:07 +00:00
David Goodwin
e8d82c0e4f Calls clobber FPSCR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80956 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 22:12:28 +00:00
David Goodwin
ca01a8d4ab RRX reads CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-01 18:32:09 +00:00
Evan Cheng
d17479e845 Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-28 06:59:37 +00:00
Misha Brukman
bf16f1ddc4 STRD and LDRD require ARMv5TE, not just ARMv5T. 
See http://llvm.org/PR4687 for more info and links.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-27 14:14:21 +00:00
Bob Wilson
4f38b383d5 Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-21 21:58:55 +00:00
David Goodwin
5d598aaf3d Update Cortex-A8 instruction itineraries for integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-19 18:00:44 +00:00
Jim Grosbach
f35d21617e Add missing defs of R2 and D1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 16:59:44 +00:00
David Goodwin
6d3d9c3fc3 Finalize itineraries for cortex-a8 integer multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:51:13 +00:00
Jim Grosbach
8db5cce021 Remove unnecessary newline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:12:16 +00:00
Jim Grosbach
1add659b0a Correct comment wording 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 15:11:43 +00:00
David Goodwin
1a8f36e3ce Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 18:31:53 +00:00
Jim Grosbach
378756c0f2 register naming cleanup (s/ip/r12/) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-12 15:21:13 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 20:47:22 +00:00
Jim Grosbach
1b747ad8a0 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 00:09:57 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:56:29 +00:00
Anton Korobeynikov
8e9ece75db Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 23:10:41 +00:00
Anton Korobeynikov
baf31088f1 Use VLDM / VSTM to spill/reload 128-bit Neon registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 13:35:48 +00:00
David Goodwin
8b7d7ade85 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 16:52:47 +00:00
David Goodwin
42a83f2d15 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-04 17:53:06 +00:00
Evan Cheng
20a2a0aff3 Make sure Thumb2 uses the right call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 21:26:42 +00:00
Evan Cheng
0531d04d00 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 20:10:36 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Evan Cheng
756da12ae4 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:46:53 +00:00
Evan Cheng
f6bc4ae4a1 1. In Thumb mode, select tBx instead of ARM variants. 
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 01:49:27 +00:00
David Goodwin
c2ffd286af Fix detection of valid BFC immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75576 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 00:57:56 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Evan Cheng
d75223d6c6 LDM_RET should be marked mayLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75187 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 22:57:41 +00:00
Evan Cheng
e7cbe4118b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 21:03:57 +00:00
Evan Cheng
0fc0ade095 Also statically set bit 25 for BR_JT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74974 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 23:45:10 +00:00
Evan Cheng
bc8a94540a Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 23:40:25 +00:00
Evan Cheng
1c83eb33c3 Add BX and BXr9 encodings. Patch by Sean Callanan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74938 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 19:16:24 +00:00
Evan Cheng
36a0aebac2 Add bfc to armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:23:46 +00:00
Evan Cheng
edcbada3d0 Added ARM::mls for armv6t2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-06 22:05:45 +00:00
Evan Cheng
d770d9e7d1 Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 06:38:40 +00:00
Evan Cheng
31926a78e3 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74683 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 01:30:04 +00:00
Bob Wilson
8b024a5eb5 Add a new addressing mode for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 23:16:05 +00:00
David Goodwin
c0309b48b5 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 15:33:01 +00:00
Evan Cheng
055b0310f8 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 07:51:04 +00:00
Evan Cheng
2b51d51bc3 Simplify predicate CarryDefIsUsed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74277 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 06:10:18 +00:00
Evan Cheng
8de898abc8 Mark a bunch of instructions commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74237 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 00:19:44 +00:00
Evan Cheng
6267422318 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:34:10 +00:00
Evan Cheng
1e249e3705 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 20:59:23 +00:00
Evan Cheng
023dd3fb0b 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 23:14:45 +00:00
Evan Cheng
f49810c7e6 Initial Thumb2 support. Majority of the work is done by David Goodwin. There are 
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 17:48:47 +00:00
Evan Cheng
e07715cfba Minor reorg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 05:25:29 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Bob Wilson
1c76d0ee5c Add explicit types for shift count constants. This is in preparation for 
another change that makes the types ambiguous (at least as far as tablegen
is concerned).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 22:08:29 +00:00
Bob Wilson
54fc124d72 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:01:46 +00:00
Evan Cheng
8557c2bcb8 Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 01:51:50 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
bb62962342 Rename methods for the sake of consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 21:46:20 +00:00
Evan Cheng
358dec5180 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 08:28:29 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 20:46:18 +00:00
Anton Korobeynikov
d4022c3fbb Add placeholder for thumb2 stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-29 23:41:08 +00:00
Jim Grosbach
f957012866 Update the names of the exception handling sjlj instrinsics to 
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-14 00:46:35 +00:00
Jim Grosbach
0e0da734bb Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is 
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-12 23:59:14 +00:00
Evan Cheng
b3379fbc60 A few more isAsCheapAsAMove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63852 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-05 08:42:55 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 18:15:48 +00:00
Evan Cheng
a956255ebf Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59314 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-14 20:09:11 +00:00
Evan Cheng
148cad8b30 Fix pre- and post-indexed load / store encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-13 07:34:59 +00:00
Evan Cheng
3c4a4ffa3d Consolidate formats; fix FCMPED etc. encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-12 07:18:38 +00:00
Evan Cheng
4df60f5491 Jump table JIT support. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 09:06:08 +00:00
Evan Cheng
8b59db3f2c Encode misc arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 01:41:35 +00:00
Evan Cheng
97f48c39fd Encode extend instructions; more clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 22:15:19 +00:00
Evan Cheng
12c3a533c5 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 17:48:05 +00:00
Evan Cheng
d87293ce78 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 08:47:38 +00:00
Evan Cheng
eb4f52eb62 Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 03:35:07 +00:00
Evan Cheng
9092213a5e Fix so_imm encoding bug; add support for MOVi2pieces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58790 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 02:25:39 +00:00
Evan Cheng
fbc9d412ef Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 01:21:28 +00:00
Evan Cheng
83b5cf0272 Encode pic load / store instructions; fix some encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 23:22:34 +00:00
Evan Cheng
edda31c412 Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 18:35:52 +00:00
Jim Grosbach
0a4b9dc9b1 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 18:38:31 +00:00
Evan Cheng
c072966838 Forgot this in last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58527 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:11:09 +00:00
Jim Grosbach
2642196a65 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-14 20:36:24 +00:00
Chris Lattner
e563bbc312 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-11 22:08:30 +00:00
Jim Grosbach
76e9661b6c Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57262 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-07 21:08:09 +00:00
Jim Grosbach
17a415a4f2 Fix Opcode values of CMP and CMN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57251 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-07 17:40:46 +00:00
Evan Cheng
7fd7ca4e7f Fix addrmode1 instruction encodings; fix bx_ret encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-17 07:53:38 +00:00
Evan Cheng
05fc966401 Revert 56176. All those instruction formats are still needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-13 01:35:33 +00:00
Evan Cheng
a964b7dffe Eliminate unnecessary instruction formats. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 23:15:39 +00:00
Dan Gohman
f5aeb1a8e4 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 16:56:44 +00:00
Evan Cheng
3aac788365 Control flow instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b ldm / stm instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d AXI2 and AXI3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:34:13 +00:00
Evan Cheng
840917be2c addrmode3 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 07:00:14 +00:00
Evan Cheng
93912739c9 Rest of addrmode2 instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec Addr2 word / byte load encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 19:02:21 +00:00