Commit Graph

28 Commits

Author SHA1 Message Date
Akira Hatanaka
72e9b6aeb4 Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 20:16:42 +00:00
Akira Hatanaka
bb2e1b581a Add Android ABI to Mips backend to handle functions returning vectors of four
floats.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 03:48:05 +00:00
Akira Hatanaka
66e19c3e9d This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16 22:19:56 +00:00
Jia Liu
bb481f8820 remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 07:46:26 +00:00
Akira Hatanaka
4d2b0f3ce7 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:47:44 +00:00
Akira Hatanaka
ed2a7d2780 Change names for MIPS "generic" processors defined in Mips.td to match what GNU
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:08:41 +00:00
Akira Hatanaka
1daa5bea58 Initial Mips64 support. Patch by Liu with some modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 20:28:08 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Akira Hatanaka
d199d0c59c Drop support for Allegrex. Allegrex implements a variant of Mips2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Akira Hatanaka
ad5f0c9e73 Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Akira Hatanaka
794bf17cbe Lower MachineInstr to MC Inst and print to .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 23:56:50 +00:00
Akira Hatanaka
4552c9a3b3 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:51:11 +00:00
Akira Hatanaka
0bf3dfbef6 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:00:26 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
Bruno Cardoso Lopes
81092dc20a Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes
c4bb67c8d9 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10 02:13:22 +00:00
Bruno Cardoso Lopes
2c2304c623 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 21:42:32 +00:00
Chris Lattner
23e70ebf35 fix emacs language spec's, patch by Edmund Grimley-Evans!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 16:20:04 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Bruno Cardoso Lopes
d3bdf19ce7 Added support for fround, fextend and FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 17:23:44 +00:00
Evan Cheng
027fdbe3ba Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 07:34:46 +00:00
Bruno Cardoso Lopes
d3a680dda5 Added new features to represent specific instructions groups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30 17:01:06 +00:00
Bruno Cardoso Lopes
7728f7e890 Fixed features usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-09 05:32:22 +00:00
Bruno Cardoso Lopes
225ca9cdd7 Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes
000604afd4 Better processor definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43749 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-06 03:15:20 +00:00
Bruno Cardoso Lopes
6d32ca0762 support for Schedule included on Mips.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41159 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes
972f5896e4 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 07:42:06 +00:00