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48bcda4dd6
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16799 Commits

Author SHA1 Message Date
Wesley Peck
48bcda4dd6 The BRK instruction in the MicroBlaze is a branch-and-link. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 22:21:08 +00:00
Wesley Peck
ef5b390263 Fix tblgen instruction errors exposed by MC asm parser tests 
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 21:40:53 +00:00
Owen Anderson
57dac88f77 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 21:36:43 +00:00
Eric Christopher
79ab2fe01a Revert the accidental commit I made reverting the previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:50:14 +00:00
Jim Grosbach
d1d5a39cad ARM fixup encoding for direct call instructions (BL). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 20:05:40 +00:00
Eric Christopher
6c50119ba3 Revert this temporarily. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:47:02 +00:00
Eric Christopher
391f228e7e Change the prologue and epilogue to use push/pop for the low ARM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:26:03 +00:00
Owen Anderson
c7139a6f0d Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 19:07:48 +00:00
Wesley Peck
60f923c5e2 Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118807 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:41:33 +00:00
Chris Lattner
af510f16ec add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:23:57 +00:00
Jim Grosbach
c466b937db Encoding of destination fixup for ARM branch and conditional branch 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 18:04:49 +00:00
Chris Lattner
1e68fdb946 add pr# 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 17:17:56 +00:00
Jim Grosbach
7eab97f260 Encoding for ARM LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 16:55:29 +00:00
Rafael Espindola
3f2d13c98e Remove some explicit arguments to getELFSection. This is 
a leftover from the removal of isExplicit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 03:40:25 +00:00
Jim Grosbach
928f3325a7 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:55:59 +00:00
Jim Grosbach
d507d1f616 Fix encoding of Ra register for ARM smla* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:27:41 +00:00
Jim Grosbach
570a922691 ARM STRH encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-11 01:09:40 +00:00
Jim Grosbach
954ffff79b Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:44:32 +00:00
Jim Grosbach
5d5eb9e381 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:38:36 +00:00
Jim Grosbach
c1235e2a4e Fix ARM encoding of non-return LDM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:18:49 +00:00
Jim Grosbach
866aa394ca Fix ARM encoding of LDM+Return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 23:12:48 +00:00
Nate Begeman
bf5be2654e Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 21:35:41 +00:00
Jim Grosbach
7c7ddb21c3 Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 17:59:10 +00:00
Jim Grosbach
2c4d5125c7 Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes
c4bb67c8d9 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 02:13:22 +00:00
Bill Wendling
8ea974039a Emit a '!' if this is a "writeback" register or memory address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay
cc8d10e1a8 Rename a parameter to avoid confusion with a local variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-10 00:08:58 +00:00
Bill Wendling
8e8b18bcfa Emit the warning about the register list not being in ascending order only once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:45:59 +00:00
Bill Wendling
5fa22a1975 s/std::vector/SmallVector/ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 23:28:44 +00:00
Bill Wendling
c3236753d6 Delete the allocated vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:51:42 +00:00
Bob Wilson
66f6c79450 Define the subtarget feature for the architecture version, 
as derived from the target triple.  This is important for enabling
features that are implied based on the architecture version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:50:47 +00:00
Bob Wilson
54f9256380 Do not use MEMBARRIER_MCR for any Thumb code. 
It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:50:44 +00:00
Bill Wendling
7729e06c12 Two types of instructions have register lists: 
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 22:44:22 +00:00
Jim Grosbach
3a2429a86c Change the ARMConstantPoolValue modifier string to an enumeration. This will 
help in MC'izing the references that use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 21:36:17 +00:00
Jim Grosbach
c9962aca8f Handle ARM constant pool values that need an explicit reference to the '.' 
pseudo-label. (TLS stuff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 19:40:22 +00:00
Chris Lattner
274191fa70 add a case we fail to devirt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 19:37:28 +00:00
Jim Grosbach
16cb3763c5 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 19:22:26 +00:00
Jim Grosbach
5df08d8f55 Further MCize ARM constant pool values. This allows basic PIC references for 
object file emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 18:45:04 +00:00
Jim Grosbach
e0ee08e367 Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 18:43:54 +00:00
Jim Grosbach
d92354c574 For ARM load/store instructions, encode [reg+reg] with no shifter immediate as 
a left shift by zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:38:15 +00:00
Jim Grosbach
a9a0dde872 ARM .word data fixups don't need an adjustment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes
9e03061b2f Fix trailing whitespace and style, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:25:34 +00:00
Jim Grosbach
54fea632b1 Add encoder method for ARM load/store shifted register offset operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 17:20:53 +00:00
Jim Grosbach
679cbd3b21 Add support for a few simple fixups to the ARM Darwin asm backend. This allows 
constant pool references and global variable refernces to resolve properly
for object file generation. For example,

int x;
void foo(unsigned a, unsigned *p) {
  p[a] = x;
}

can now be successfully compiled directly to an (ARM mode) object file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 01:37:15 +00:00
Bill Wendling
5e559a22c1 Revert r118457 and r118458. These won't hold for GPRs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-09 00:30:18 +00:00
Bill Wendling
4b97c55648 Get the register and count from the register list operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:51:20 +00:00
Bill Wendling
3734ef3fb4 reglist has two operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:50:20 +00:00
Bill Wendling
87f4f9a946 The "addRegListOperands()" function returns the start register and the total 
number of registers in the list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:49:57 +00:00
Owen Anderson
c24cb3551e Add support for ARM's specialized vector-compare-against-zero instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes
2c2304c623 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-08 21:42:32 +00:00