6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-16 11:05:54 +00:00
Code Issues Projects Releases Wiki Activity
74,617 Commits 39 Branches 0 Tags 277 MiB
49cb9b8886
Commit Graph

1273 Commits

Author SHA1 Message Date
Jim Grosbach
0ffd4a09df ARM testcases for assembly parsing and encoding SMLA* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:01:34 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:13:31 +00:00
Jim Grosbach
248e6c328c ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:04:48 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:44:50 +00:00
Jim Grosbach
9076b6e8f4 ARM assembly parsing and encoding tests for SEL instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 16:59:33 +00:00
Jim Grosbach
8409f04731 ARM parsing and encoding tests for SBC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:03:59 +00:00
Jim Grosbach
8ae45af794 ARM testcases for SADD/SASX parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:00:49 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:37:43 +00:00
Jim Grosbach
616fbdf987 ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:29:23 +00:00
Jim Grosbach
a4c34ab544 ARM parsing and encodings tests for saturating arithmetic insns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:18:28 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:57:11 +00:00
Jim Grosbach
61b1b21e9a Add tests for ARM PKH assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:02:03 +00:00
Eli Friedman
a4d0bd84f7 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:36:11 +00:00
Jim Grosbach
88d1bc832c Add parsing/encoding tests for ARM ORR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:48:53 +00:00
Jim Grosbach
a678514459 Consolidate ARM NOP encoding test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:39:38 +00:00
Jim Grosbach
c3635c2e92 ARM parsing and encoding tests for MVN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:20:31 +00:00
Jim Grosbach
b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:59:29 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:35:35 +00:00
Jim Grosbach
2317fe1584 Move mr[r]c[2] ARM tests and tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:28:56 +00:00
Jim Grosbach
1a2be4db5b ARM testcases for MOVT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:23:25 +00:00
Jim Grosbach
5f16057d1e ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:10:31 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:13:28 +00:00
Jim Grosbach
0ec2aa21d0 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:02:39 +00:00
Eli Friedman
7105259ce8 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 02:41:28 +00:00
Eli Friedman
5232cc675c PR10370: Make sure we know how to relax push correctly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 21:28:39 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 18:46:47 +00:00
Jim Grosbach
33c16a2737 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 22:04:21 +00:00
Jim Grosbach
70d8fcfaa0 Add some testcases for ARM MLA/MLS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:43:05 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:19:17 +00:00
Jim Grosbach
1134be2428 Enable some tests we now handle correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:02:23 +00:00
Jim Grosbach
3b14a5c546 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:35:38 +00:00
Jim Grosbach
791feea100 ARM ISB assembly parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:02:25 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:00:31 +00:00
Jim Grosbach
00a66653cb ARM tests for EOR instruction parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:22:21 +00:00
Jim Grosbach
6a86feafa8 Remove duplicate tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:19:19 +00:00
Jim Grosbach
e77494e3e3 ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:18:13 +00:00
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:40:38 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:59:38 +00:00
Jim Grosbach
14ab1c3387 ARM parsing and encoding tests for CMN/CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:26:58 +00:00
Jim Grosbach
d986bc66bc Shuffle ARM assembly tests a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:19:10 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:01:08 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:14:23 +00:00
Jim Grosbach
f333d471d2 Testcases for ARM assembly BX/BXJ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:46 +00:00
Jim Grosbach
37023b05c8 Testcases for ARM assembly BLX/BL instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:10:10 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd Fix copy-pasto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370 Add tests for ARM parsing of 'BIC' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96 Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:10:23 +00:00
Jim Grosbach
59642c2600 Add tests for ARM parsing of 'AND' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74 Add tests for ARM parsing of 'ADD' instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:50:29 +00:00
Jim Grosbach
dc89561fec Add check for predicate w/o S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-12 16:25:04 +00:00
Jim Grosbach
3f00e31706 Fix recognition of ARM 'adcs' mnemonic. 
The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 17:09:57 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates. 
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 16:48:36 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo 
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 03:57:24 +00:00
Evan Cheng
3286920505 Add support for ARM / Thumb mode switching with .code 16 and .code 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 22:36:29 +00:00
Evan Cheng
39dfb0ff84 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 03:55:05 +00:00
Kevin Enderby
d7c7e2ff7d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 17:55:20 +00:00
Kevin Enderby
d521f2d2f1 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a 
push with a small constant produces a 2-byte push.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 17:23:46 +00:00
Eli Friedman
af45b3d8cb Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-05 18:21:20 +00:00
Joerg Sonnenberger
ca0ede7655 Recognize the xstorerng alias for VIA PadLock's xstore instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 01:38:03 +00:00
Jim Grosbach
254cf03a45 Asm parser range checking on .<size> <value> directives. 
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-29 16:05:14 +00:00
Jim Grosbach
adf7366771 ARM Thumb2 asm syntax optional destination operand for binary operators. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 00:19:13 +00:00
Jim Grosbach
6b8f1e35ea ARM Assembly support for Thumb mov-immediate. 
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 23:54:06 +00:00
Jim Grosbach
fbd01783a6 ARM assembler support for ldmfd/stmfd mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 20:32:18 +00:00
Jim Grosbach
0d06bb9548 ARM assembler support for vpush/vpop. 
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 20:00:07 +00:00
Jim Grosbach
0ff9220ccb ARM Assembly syntax support for arithmetic implied dest operand. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 19:09:15 +00:00
Jim Grosbach
75c2b2028b Move ARM-specific test to ARM directory. 
Hopefully make the x86-target-only Windows bots happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-25 01:53:17 +00:00
Jim Grosbach
56fc642000 Testcase for r133818 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 20:59:01 +00:00
Eli Friedman
a390a1aa48 Add support for movntil/movntiq mnemonics. Reported on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-23 21:07:47 +00:00
Nick Lewycky
94d4c91bc5 Add support for assembling "movq" when it's correct to do so, while continuing 
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-21 22:45:41 +00:00
Bob Wilson
38c892624b Revert r133452: "Emit movq for 64-bit register to XMM register moves..." 
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-21 17:35:13 +00:00
Nick Lewycky
1bd15700a0 Emit movq for 64-bit register to XMM register moves, but continue to accept 
movd when assembling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-20 18:33:26 +00:00
Hans Wennborg
5cc6491f50 MC: Allow .common as alias for .comm assembler directive. PR10116. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-18 13:51:54 +00:00
Bill Wendling
393c4047c0 Improve the heuristic to emit the alias if the number of hard-coded registers 
are also greater than the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 04:31:19 +00:00
Bill Wendling
740e5b3586 Heuristic: If the number of operands in the alias are more than the number of 
operands in the aliasee, don't print the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 03:17:20 +00:00
Roman Divacky
be234dabf4 Test that ".byte 1, 2, 3, 4" does the right thing. 
Requested by nbjoerg!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 17:32:17 +00:00
Rafael Espindola
6536644713 Basic support for macros with explicit arguments. 
We still don't handle

* default values
* :req
* :vararg
* \()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-05 02:43:45 +00:00
Nick Lewycky
e0b87032f5 Add support for @GOTPTOFF in i386 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 03:33:27 +00:00
Rafael Espindola
04507f062f Use %rbp on a 64 bit test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 04:04:50 +00:00
Benjamin Kramer
06a8d54967 Move ARM specific test into the ARM subdir. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes
be64b39431 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:46:09 +00:00
Charles Davis
88c816453f Add the suffix to the Win64 EH data sections' names if given. Add a test for 
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 21:38:47 +00:00
Charles Davis
07cbe23173 Assorted fixes for Win64 EH unwind info emission: 
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.

Add a test for the latter two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 15:10:25 +00:00
Charles Davis
3a5d7d0665 Add a test for Win64 EH unwind information emission. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 03:54:43 +00:00
Charles Davis
3ac7b034d6 Add a test for the chained directives that I forgot last time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 05:17:43 +00:00
Charles Davis
ca93138e11 Test .seh_startchained and .seh_endchained parsing. 
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.

The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 02:45:47 +00:00
Charles Davis
410ef2b263 Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with 
them.

I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:43:45 +00:00
Charles Davis
575630ccb8 Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the 
buggy methods that parse these directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:51:25 +00:00
Charles Davis
47268164f3 Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another 
one I found by inspection).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:08:15 +00:00
Charles Davis
309213279e Add a test for the .seh_handler directive. Fix problems with the parsing 
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
56926a3961 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 00:35:03 +00:00