Commit Graph

5953 Commits

Author SHA1 Message Date
Chandler Carruth
4a85cc982a Add loop aligning to MachineBlockPlacement based on review discussion so
it's a bit more plausible to use this instead of CodePlacementOpt. The
code for this was shamelessly stolen from CodePlacementOpt, and then
trimmed down a bit. There doesn't seem to be much utility in returning
true/false from this pass as we may or may not have rewritten all of the
blocks. Also, the statistic of counting how many loops were aligned
doesn't seem terribly important so I removed it. If folks would like it
to be included, I'm happy to add it back.

This was probably the most egregious of the missing features, and now
I'm going to start gathering some performance numbers and looking at
specific loop structures that have different layout between the two.

Test is updated to include both basic loop alignment and nested loop
alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 08:57:37 +00:00
Chandler Carruth
4162eced73 Add a very basic test for MachineBlockPlacement. This is essentially the
canonical example I used when developing it, and is one of the primary
motivating real-world use cases for __builtin_expect (when burried under
a macro).

I'm working on more test cases here, but I'm trying to make sure both
that the pass is doing the right thing with the test cases and that they
aren't too brittle to changes elsewhere in the code generation pipeline.

Feedback and/or suggestions on how to test this are very welcome.
Especially feedback on whether testing the block comments is a good
strategy; I couldn't find any good examples to steal from but all the
other ideas I had were a lot uglier or more fragile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 08:01:56 +00:00
Craig Topper
b4c945716f Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 06:55:01 +00:00
Chad Rosier
6690bca623 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 00:07:12 +00:00
Evan Cheng
fd230df463 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 22:22:54 +00:00
Nadav Rotem
815af82b74 Improve code generation for vselect on SSE2:
When checking the availability of instructions using the TLI, a 'promoted'
instruction IS available. It means that the value is bitcasted to another type
for which there is an operation. The correct check for the availablity of an
instruction is to check if it should be expanded.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 20:43:16 +00:00
James Molloy
cdd8e46bec Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 14:11:07 +00:00
Nadav Rotem
ca58c72267 Add support for the vector-widening of vselect and vector-setcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 09:45:11 +00:00
Craig Topper
717cdb0df8 Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Lang Hames
aa13603a3e Added testcase for <rdar://problem/10215997>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 23:50:52 +00:00
Nadav Rotem
d88bc2a683 Add additional element-promotion tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 23:05:33 +00:00
Nadav Rotem
fbf19ef186 Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 22:32:43 +00:00
Bob Wilson
ad952ad8f0 Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:34:51 +00:00
Bob Wilson
db2b18feba Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:34:47 +00:00
Justin Holewinski
c3cab3aec0 PTX: Fix disabling of MAD instruction selection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 13:39:20 +00:00
Chad Rosier
fe04757f5e Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 05:28:00 +00:00
Nick Lewycky
44d798d976 Add support for a new extension to the .file directive:
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 23:05:28 +00:00
Nadav Rotem
f9b9abbd08 Add CHECKs and document PR11158.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 20:23:23 +00:00
Nadav Rotem
63aa7910ae stabalize tests by specifying the exact sse level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 19:45:38 +00:00
Hal Finkel
3bca0b9d6e use FileCheck and not grep in new tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 16:01:41 +00:00
Nadav Rotem
39c14efd6d Clean the triple, add check lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 07:07:51 +00:00
Nadav Rotem
ee6fd6a2b2 Previously v2i32 vectors were legalized to v4i32. Now, they are legalized to
v2i64. These tests do not check MMX nor zmoving into them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 06:59:01 +00:00
Hal Finkel
87525be07a Test case for CanLowerReturn fix (r141981)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:59 +00:00
Hal Finkel
b31d3d271f Add PPC 440 scheduler and some associated tests (new files)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 04:03:55 +00:00
Nadav Rotem
f6481aee43 Add tripple and stabalize a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 21:20:54 +00:00
Nadav Rotem
acb10f1519 Add triple to tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:53:20 +00:00
Nadav Rotem
9eee96a598 fix a typo in the test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:43:41 +00:00
Nadav Rotem
8fb06b3e8f Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 20:31:33 +00:00
Nadav Rotem
ea6578b72a Remove the the test which checks the saving of a vector of booleans into memory.
The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 19:06:06 +00:00
Nadav Rotem
c32a8c9073 Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 10:02:06 +00:00
Eli Friedman
46995fa7e2 Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 23:58:49 +00:00
Jakob Stoklund Olesen
ac7caa0d43 Update live-in lists when splitting critical edges.
Fixes PR10814. Patch by Jan Sjödin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 17:25:46 +00:00
Craig Topper
54a11176f6 Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
Craig Topper
909652f687 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen
a80444f88d Add value numbers when spilling dead defs.
When spilling around an instruction with a dead def, remember to add a
value number for the def.

The missing value number wouldn't normally create problems since there
would be an incoming live range as well.  However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.

The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.

This fixes part of PR11125.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 00:34:31 +00:00
Benjamin Kramer
d38e99e949 Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 14:27:54 +00:00
Kalle Raiskila
898f336c51 Mark 'branch indirect' instruction as an indirect branch.
Not having it confused assembly printing of jumptables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 11:40:03 +00:00
Bill Wendling
4e68054b20 More closely follow libgcc, which has code after the `ret' instruction to
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 08:24:19 +00:00
Bill Wendling
1203fe7fc8 Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:48:07 +00:00
Bill Wendling
82222c20be Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:42:32 +00:00
Craig Topper
8ab1d1e900 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 07:09:14 +00:00
Jakob Stoklund Olesen
dee83c90bb Also inflate register classes around inline asm.
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 23:37:40 +00:00
Bill Wendling
f6fb7ed53c We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 23:03:40 +00:00
Jakob Stoklund Olesen
1c062c24ab Fix -widen-vmovs liveness issues.
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:06:23 +00:00
Bob Wilson
b75e5d96dd Make this test more specific. There are 3 stats that matched "machine-licm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:34:31 +00:00
Eric Christopher
6618a241f7 Add a new wrapper node for a DILexicalBlock that encapsulates it and a
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 22:59:11 +00:00
Bill Wendling
e575499d83 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:40:47 +00:00
Devang Patel
2e35047947 Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:09:58 +00:00
Nadav Rotem
6fe4e51547 Add support for legalization of vector SHL/SRA/SRL instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 14:36:35 +00:00
Craig Topper
a6f386b4cd Test case for X86 LZCNT instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:47:01 +00:00