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20719 Commits

Author SHA1 Message Date
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
99486be8ba Simplify offset verification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:10:05 +00:00
Jim Grosbach
517a013a4f Fix copy/past-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500 ARM NEON two-operand aliases for VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
540c6d9d26 Don't include alignment padding in BBInfo.Size. 
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:55:02 +00:00
Jim Grosbach
8254f02231 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82 ARM VFP support 'flds/fldd' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:49:29 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
08a7d92da6 Modify class ReadHardware and add definition of 64-bit version of instruction 
RDHWR. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:31:26 +00:00
Akira Hatanaka
f99c1e5a19 Add newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:26:03 +00:00
Akira Hatanaka
be7b67368c Add 64-bit HWR29 register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:23:52 +00:00
Akira Hatanaka
da86fa14f0 32 to 64-bit anyext pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:21:19 +00:00
Akira Hatanaka
0a18cdc372 32 to 64-bit zext pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:14:41 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Bruno Cardoso Lopes
d1bcf0dbc1 Variable cleanup. Based on past patch submittals variable names have 
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:35:30 +00:00
Akira Hatanaka
2c78be01f6 64-bit WrapperPICPat patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:11:43 +00:00
Akira Hatanaka
20aa12ae5c Define base class for WrapperPICPat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:54:54 +00:00
Akira Hatanaka
7398bf01c2 Modify LowerFCOPYSIGN to handle Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 21:48:50 +00:00
Akira Hatanaka
bd15090aa2 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:15:01 +00:00
Akira Hatanaka
3bdc03a592 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:13:53 +00:00
Akira Hatanaka
4d0eb637f0 Fix 64-bit immediate patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 20:10:24 +00:00
Jim Grosbach
4f66a050a2 Nuke inadvertant debugging commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 19:46:59 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca ARM support the .arm and .thumb directives for assembly mode switching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Craig Topper
d802326335 Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 08:30:53 +00:00
Bill Wendling
b3ec329c14 Adjust the stack by one pointer size for all frameless stacks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:58:55 +00:00
Bill Wendling
c61751373a Fix off-by-one error when encoding the stack size for a frameless stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:49:49 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 07:15:52 +00:00
Hal Finkel
234bb38d6c make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:34:06 +00:00
Hal Finkel
6d0e014b1f make base register selection used in eliminateFrameIndex 64-bit clean 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:34:02 +00:00
Hal Finkel
ae37cd0a37 set mayStore and mayLoad on CR pseudos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:33:57 +00:00
Hal Finkel
7ad6b7d359 64-bit LR8 load should use X11 not R11 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2fe71c5ef4 Eliminate delta argument from AdjustBBOffsetsAfter. 
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83 Compute some alignment information for each basic block. 
These fields are not used for anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 04:17:35 +00:00
Jim Grosbach
1ceef1a491 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc Move common expression into a method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63 ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>. 
No functional change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:08:25 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:07:24 +00:00
Bruno Cardoso Lopes
e3d3572e28 Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:28:57 +00:00
Jim Grosbach
4e4139588c ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen
6fbea43b0b Revert r145971: "Use conservative size estimate for tBR_JTr." 
This caused more offset errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:41:31 +00:00
Bill Wendling
84d518af19 Explicitly check for the different SUB instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:14:27 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e Use conservative size estimate for tBR_JTr. 
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
305e5fe797 Remove alignment from deserted constant islands. 
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:55:35 +00:00
Bill Wendling
581ac2723c Encode the total stack if there isn't a frame. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:34:01 +00:00
Bill Wendling
57a3cd2f32 * Add a macro to remove a magic number. 
* Rename variables to reflect what they're actually used for.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145968 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 21:23:42 +00:00
Hal Finkel
d21e930eac add RESTORE_CR and support CR unspills 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 20:55:36 +00:00
Hal Finkel
16588e794c remove old FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 20:52:56 +00:00
Bill Wendling
5b2c4978ce Check the correct value for small stack sizes. Also modify some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 19:16:17 +00:00
Bill Wendling
75e14e0ebd For a small sized stack, we encode that value directly with no "stack adjust" value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 19:09:06 +00:00
Justin Holewinski
4c7ffb6a7e PTX: Continue to fix up the register mess. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:48 +00:00
Justin Holewinski
e37a83f66b PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:39:46 +00:00
Craig Topper
fe03315925 Add X86ISD::HADD/HSUB to getTargetNodeName 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:31:36 +00:00
Craig Topper
cb6bd11bd6 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 09:04:59 +00:00
Craig Topper
34671b812a Merge floating point and integer UNPCK X86ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 08:21:25 +00:00
Craig Topper
3d8c2ce3e4 Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:31:16 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Craig Topper
1ff73d7a67 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:59:07 +00:00
Jim Grosbach
df33e0d05e Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 04:49:29 +00:00
Bruno Cardoso Lopes
ff452f5349 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
2bcc789a9d Add register HWR29 numbering. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 03:34:36 +00:00
Bill Wendling
80caf9c273 Add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:57:48 +00:00
Jim Grosbach
cb86509e7a Tidy up value checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
6482e91149 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:48:32 +00:00
Chad Rosier
ed42c5f778 [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
3e572ac2fb Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145890 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
8c741b8064 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:19 +00:00
Bill Wendling
79df986c60 The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145888 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:26:14 +00:00
Jim Grosbach
d9a6e8978d Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e80fba0e6c Use an existing function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:51:12 +00:00
Jim Grosbach
370b78d795 Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 00:47:03 +00:00
Jim Grosbach
f503ef6800 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 23:45:46 +00:00
Jim Grosbach
713c70238c Tweak ADDrr fix. Bad check for explicit .w 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:27:04 +00:00
Jim Grosbach
927b9df4c6 Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 22:16:39 +00:00
Akira Hatanaka
d6bc5237d8 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:26:34 +00:00
Akira Hatanaka
cee46abc16 Split ExtIns into two base classes and have instructions EXT and INS derive from 
them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:14:28 +00:00
Jim Grosbach
da84786bee Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
2bf08ec854 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 21:03:03 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909 Fix previous commit. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:12:26 +00:00
Jim Grosbach
45755a77ec Tidy up. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:09:44 +00:00
Jim Grosbach
afb500ace1 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 19:55:46 +00:00
Hal Finkel
3fd0018af1 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:17 +00:00
Hal Finkel
9489487f98 don't include CR bit subregs in callee-saved list 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:55:12 +00:00
Hal Finkel
2e313caa36 add register pressure for CR regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 17:54:17 +00:00
Craig Topper
1dc0fbc168 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 07:27:14 +00:00
Craig Topper
beabc6cc6d Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145803 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 06:56:46 +00:00
Bob Wilson
6ce2deacef Fix 80-column issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
0cb2a45cce Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 21:24:48 +00:00
Sanjoy Das
199ce33b3b Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-03 09:32:07 +00:00