Daniel Dunbar
7a570d09ac
MC/AsmParser: Add macro argument substitution support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 19:00:10 +00:00
Daniel Dunbar
c64a0d7c3e
MC/AsmParser: Add basic support for macro instantiation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:54:11 +00:00
Daniel Dunbar
6d8cf082f6
MC/AsmParser: Add basic parsing support for .macro definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:47:21 +00:00
Daniel Dunbar
3c802de01a
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
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support macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18 18:38:02 +00:00
Eli Friedman
879259faa3
Test for ELF .size directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:15:24 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c
Add AVX 256-bit compare instructions and a bunch of testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
87a85c7ef0
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:07:28 +00:00
Chris Lattner
37a746bc85
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:23:55 +00:00
Bruno Cardoso Lopes
fd920fa59a
Add AVX 256-bit packed logical forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7
Add AVX 256-bit unop arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
a0d09a85e2
Add AVX 256 binary arithmetic instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
aa099be71f
Add AVX 256-bit MOVMSK forms
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:06:32 +00:00
Daniel Dunbar
b6c3a607ac
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 19:37:35 +00:00
Daniel Dunbar
492b7a21cb
MC/AsmParser: Move .desc parsing to Darwin specific parser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 19:22:53 +00:00
Daniel Dunbar
9ac66b008d
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 18:49:22 +00:00
Bruno Cardoso Lopes
d52e78efac
Add AVX 256-bit packed MOVNT variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8
Add AVX 256-bit unpack and interleave
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Chris Lattner
834df19452
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:12 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
cc69e13a36
Add more assembly opcodes for SSE compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:24:03 +00:00
Bruno Cardoso Lopes
ced9ec9bac
Add AVX AES instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
4f6bdf9042
Add AVX SSE4.2 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
09df2ae0d0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312
Add AVX SSE4.1 extractps and pinsr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
4fd32db6a6
Add AVX SSE4.1 Extract Integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
ee94e8297e
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
36869b69b0
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
07de40629f
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:36:24 +00:00
Bruno Cardoso Lopes
68b559e5f3
Add AVX SSE4.1 blend, mpsadbw and vdp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
4a544be3a8
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
c607570563
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
2c70d4ad35
Add AVX SSE4.1 round instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
f5cd8c51e3
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61
Add AVX SSE3 packed addsub instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
79b634c244
Add AVX SSE3 replicate and convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
6596a62076
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
e26f14d150
Add AVX SSE2 mask creation and conditional store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
1e4b723b20
Add AVX SSE2 packed integer extract/insert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
876085dcfa
Add AVX SSE2 integer unpack instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae
Add AVX SSE2 packed integer shuffle instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
6d5d2b5de2
Add AVX SSE2 pack with saturation integer instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c
Add AVX SSE2 integer packed compare instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716
Add *several* AVX integer packed binop instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
147b7cad2f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88
Add AVX non-temporal stores
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
ea86423cbd
Add sqrt, rsqrt and rcp AVX instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
4548260ab5
Described the missing AVX forms of SSE2 convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
bdffc16d65
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3
revert this now, it's using avx instead of sse :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes
a0ae87fd5d
Add some AVX convert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
788184365a
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 20:48:23 +00:00
Chris Lattner
645b209c4a
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 07:29:18 +00:00
Bruno Cardoso Lopes
6539dc6e6c
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
e93e300ad0
Add AVX MOVMSK{PS,PD}rr instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
428256b818
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 21:10:57 +00:00
Bruno Cardoso Lopes
7dbfd07e32
Add AVX SHUF{PS,PD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:07:15 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes
62a76c6401
Add AVX compare packed instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
0caca3967b
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
c3d57b179c
Add AVX MOV{SS,SD}{rr,rm} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 22:38:56 +00:00
Eric Christopher
97994e0262
Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion
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during test runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 21:11:51 +00:00
Bruno Cardoso Lopes
f4f4bad696
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
be4d595afd
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:31 +00:00
Chris Lattner
1cf44fc051
fix rdar://7873482 by teaching the instruction encoder to emit
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segment prefixes. Daniel wrote most of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
d7f9cc4de7
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes
cf125d02a0
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
7be0d2c8e9
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
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Handle OpSize TSFlag for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
c902a59f4c
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
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Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
99405df044
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Chris Lattner
1087f54ddb
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Kevin Enderby
31cc9655b6
MC/X86: Add alias for movzx.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 21:20:21 +00:00
Kevin Enderby
5e394429ab
MC/X86: Add alias for fwait.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 20:59:10 +00:00
Kevin Enderby
31b6c5b2f3
Fix the use of x86 control and debug registers so that the assertion failure in
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getX86RegNum() does not happen. Patch by Shantonu Sen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 19:01:27 +00:00
Kevin Enderby
bd658918df
MC/X86: Add aliases for Jcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 21:33:19 +00:00
Eric Christopher
bd3ba537cd
Add a quick test of relocations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 00:53:40 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Eric Christopher
02b46bc942
Add support for initialized global data for darwin tls. Update comments
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and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c
Changed the encoding of X86 floating point stack operations where both operands
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are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
Daniel Dunbar
39e2dd7bab
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
Daniel Dunbar
79373680ed
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
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for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Eric Christopher
7e2f5aaa67
Make sure aeskeygenassist uses an unsigned immediate field.
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Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Dan Gohman
e350690e3b
Fix an mmx movd encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6
MC/X86: Add aliases for CMOVcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
4c361972fd
MC/X86: Add alias for setz, setnz, jz, jnz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Kevin Enderby
9d31d79493
Added retl for 32-bit x86 and added retq for 64-bit x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
14aaeac5cf
Define the x86 pause instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
Dan Gohman
ee5673b622
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
Chris Lattner
a7f1354eb5
fix rdar://7986634 - match instruction opcodes case insensitively.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:34:33 +00:00
Eric Christopher
591466baff
A more combo tls testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:19:42 +00:00
Eric Christopher
aa6c72ec95
Few more simple tls testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:35:15 +00:00