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44 Commits

Author SHA1 Message Date
Akira Hatanaka
2ef99c5dff [mips] Define a pseudo instruction which writes to both the lower and higher 
parts of the accumulators and gets expanded post-RA.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-15 01:48:30 +00:00
Akira Hatanaka
397f6da28c [mips] Use predicates to guard instructions using accumulator registers instead 
of relying on AddedComplexity.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-15 01:21:37 +00:00
Akira Hatanaka
adb1297d49 [mips] Rename isel nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-15 01:12:50 +00:00
Akira Hatanaka
243702b95a [mips] Fix definition of mfhi and mflo instructions to read from the whole 
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 18:49:46 +00:00
Akira Hatanaka
69f8e0935a [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:02:02 +00:00
Akira Hatanaka
a796d90c0e [mips] Use ptr_rc to simplify definitions of base+index load/store instructions. 
Also, fix predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 00:55:15 +00:00
Akira Hatanaka
a98a486ad1 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 21:08:22 +00:00
Akira Hatanaka
88373c29fe [mips] Use register operands instead of register classes in DSP instruction 
definitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 01:02:20 +00:00
Akira Hatanaka
7d6355226c [mips] Rename DSPRegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 00:53:38 +00:00
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 00:47:08 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
7af40bfa66 [mips] Mark pseudo instructions as code-gen only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188017 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:44:39 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
a1fe9ef62e [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 22:20:40 +00:00
Akira Hatanaka
a2b2200ff8 [mips] Split the DSP control register and define one register for each field of 
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 18:37:49 +00:00
Akira Hatanaka
99ad6ac65e [mips] Handle reading, writing or copying of ccond field of DSP control 
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 23:07:05 +00:00
Akira Hatanaka
c147c1b994 [mips] Fix handling of instructions which copy to/from accumulator registers. 
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 23:22:09 +00:00
Akira Hatanaka
cd6c57917d [mips] Instruction selection patterns for DSP-ASE vector select and compare 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 22:37:26 +00:00
Akira Hatanaka
b0caf5ff64 [mips] Clear isCommutable bit of instructions which are not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 20:40:39 +00:00
Akira Hatanaka
d597263b94 [mips] In performDSPShiftCombine, check that all elements in the vector are 
shifted by the same amount and the shift amount is smaller than the element
size.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 19:58:23 +00:00
Akira Hatanaka
97a62bf2a4 [mips] Instruction selection patterns for DSP-ASE vector shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 23:21:32 +00:00
Akira Hatanaka
26aef5b7d6 [mips] DSP-ASE move from HI/LO register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 00:52:44 +00:00
Akira Hatanaka
3d60241c3e [mips] Reapply r179420 and r179421. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-13 00:55:41 +00:00
Akira Hatanaka
d35d5bdfc4 Revert r179420 and r179421. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 22:40:07 +00:00
Akira Hatanaka
6d224459f4 [mips] Instruction selection patterns for carry-setting and using add 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 22:24:52 +00:00
Akira Hatanaka
9367b8d4f2 [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 22:14:24 +00:00
Akira Hatanaka
fd2cd0db97 [mips] Add patterns for DSP indexed load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 02:14:45 +00:00
Akira Hatanaka
2c2c33a167 [mips] Fix DSP instructions to have explicit accumulator register operands. 
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 01:58:00 +00:00
Akira Hatanaka
2cd7d3f9ce [mips] Define pseudo instructions for spilling and copying accumulator 
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-30 00:54:52 +00:00
Akira Hatanaka
1e7739f614 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:20:09 +00:00
Akira Hatanaka
0232064e6f [mips] Move class IsCommutable into MipsInstrInfo.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170054 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-13 00:32:01 +00:00
Akira Hatanaka
93ba059e48 MIPS DSP: other miscellaneous instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 20:50:31 +00:00
Akira Hatanaka
e91ff1d135 MIPS DSP: ADDUH.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 20:16:04 +00:00
Akira Hatanaka
cb39aa05af MIPS DSP: ABSQ_S.PH instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:09:21 +00:00
Akira Hatanaka
23bb38f034 MIPS DSP: SHLL.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:05:08 +00:00
Akira Hatanaka
833f7a5c4b MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 04:08:42 +00:00
Akira Hatanaka
451b0e7b8a MIPS DSP: CMPU.EQ.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:58:34 +00:00
Akira Hatanaka
a216401621 MIPS DSP: ADDU.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:13:59 +00:00
Akira Hatanaka
01f7089bca MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:15:57 +00:00
Akira Hatanaka
2df483efb3 MIPS DSP: all the remaining instructions which read or write accumulators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:11:20 +00:00
Akira Hatanaka
fd89e6ffda MIPS DSP: add support for extract-word instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:05:42 +00:00
Akira Hatanaka
7e105bcc3a MIPS DSP: add bitcast patterns between vectors and int. 
No test cases. These patterns will get tested along with dsp intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:56:38 +00:00
Akira Hatanaka
7509ec18d1 MIPS DSP: add vector load/store patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:50:59 +00:00
Akira Hatanaka
ef5fc952e8 MIPS DSP: Add immediate leaves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 00:07:12 +00:00