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3718 Commits

Author SHA1 Message Date
Evan Cheng
3fefc182a0 Increment use count of new virtuals created during PHI elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36233 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 00:36:11 +00:00
Chris Lattner
8c7d2d56bf Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:53:02 +00:00
Chris Lattner
895c4ab564 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 21:14:16 +00:00
Evan Cheng
20b0abc24f Copy coalescing change to prevent a physical register from being pin to a 
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:32:26 +00:00
Evan Cheng
e52eef8e9a Add a register allocation preference field; add a method to compute size of a live interval. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36216 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:25:11 +00:00
Evan Cheng
38b7ca6651 Keep track of number of uses within the function per virtual register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36214 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:22:11 +00:00
Chris Lattner
95a5e0507e SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 19:03:21 +00:00
Reid Spencer
9a9203b894 Fix problems in the PartSet lowering having to do with incorrect bit width. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36180 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 22:21:14 +00:00
Anton Korobeynikov
bed2946a96 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 18:10:23 +00:00
Chris Lattner
1c35968d4d disable switch lowering using shift/and. It still breaks ppc bootstrap for 
some reason.  :(  Will investigate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36011 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 19:39:41 +00:00
Anton Korobeynikov
e01017bba4 Fix PR1325: Case range optimization was performed in the case it 
shouldn't. Also fix some "latent" bug on 64-bit platforms


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35990 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 13:25:55 +00:00
Chris Lattner
3ff981749b disable shift/and lowering to work around PR1325 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35985 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 02:26:56 +00:00
Anton Korobeynikov
8085bcfdca Fix PR1323 : we haven't updated phi nodes in good manner :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35963 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-13 06:53:51 +00:00
Reid Spencer
df41353497 Make sure intrinsics that are lowered to functions make the function weak 
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35956 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 21:53:38 +00:00
Reid Spencer
eeedcb6905 Fix bugs in generated code for part_select and part_set so that llc doesn't 
barf when CBE is run with a program that contains these intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35946 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 13:30:14 +00:00
Reid Spencer
37958093c6 Fix a bug in PartSet. The replacement value needs to be zext or trunc to 
the size of the value, not just zext. Also, give better names to two BBs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35945 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 12:46:33 +00:00
Chris Lattner
3a508c94a6 the result of an inline asm copy can be an arbitrary VT that the register 
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 06:00:20 +00:00
Chris Lattner
4829b1c6ab fold noop vbitconvert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 05:58:43 +00:00
Chris Lattner
c2941779c3 Fix weirdness handling single element vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 04:44:28 +00:00
Reid Spencer
f75b874957 For PR1284: 
Implement the "part_set" intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35938 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 02:48:46 +00:00
Chris Lattner
c24bbaddf8 fix an infinite loop compiling ldecod, notice by JeffC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 16:51:53 +00:00
Chris Lattner
1eba01e9a0 Fix this harder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 06:50:51 +00:00
Chris Lattner
c56a81dff1 don't create shifts by zero, fix some problems with my previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 06:43:25 +00:00
Chris Lattner
20a35c3fa5 Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 05:32:27 +00:00
Chris Lattner
1982ef20c4 Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 05:11:38 +00:00
Reid Spencer
18da072088 For PR1146: 
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35877 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 02:44:20 +00:00
Chris Lattner
c6eb6d7255 apparently some people commit without building the tree, or they forget to 
commit a LOT of files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35858 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 03:20:39 +00:00
Jeff Cohen
2da8da46ba No longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35850 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 23:42:32 +00:00
Chris Lattner
2b95fd67da remove dead target hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 23:34:08 +00:00
Chris Lattner
b445d0cbb9 remove some dead target hooks, subsumed by isLegalAddressingMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 22:27:04 +00:00
Anton Korobeynikov
54e2b142be Use integer log for metric calculation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35834 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 21:57:03 +00:00
Jeff Cohen
efc3662636 Unbreak VC++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35817 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 14:32:59 +00:00
Anton Korobeynikov
4198c58c71 Next stage into switch lowering refactoring 
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35816 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 12:31:58 +00:00
Reid Spencer
5694b6e90e For PR1146: 
Adapt handling of parameter attributes to use the new ParamAttrsList class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35814 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 06:17:21 +00:00
Chris Lattner
1a6acc214d implement CodeGen/X86/inline-asm-x-scalar.ll:test3 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35802 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 05:31:20 +00:00
Chris Lattner
ff33cc4d08 add some assertions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35800 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 05:23:13 +00:00
Chris Lattner
0ebe9c132c Fix a bug introduced with my previous patch, where it didn't correctly handle 
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35789 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 01:19:33 +00:00
Chris Lattner
d2eae62e93 Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308: 
some instructions can have multiple frame indices in them.  If this happens,
rewrite all of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35785 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 00:46:10 +00:00
Chris Lattner
4b993b19f9 Fix PR1316 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35783 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 00:33:58 +00:00
Chris Lattner
921169b103 Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35779 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-08 22:23:26 +00:00
Chris Lattner
e303ac9052 minor comment fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35696 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-06 17:47:14 +00:00
Reid Spencer
3f108cb555 Change the bit_part_select (non)implementation from "return 0" to abort. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35679 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-05 01:20:18 +00:00
Reid Spencer
addd11d98e Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35678 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 23:48:25 +00:00
Anton Korobeynikov
5502bf67cd Properly emit range comparisons for switch cases, where neighbour cases 
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35672 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 21:14:49 +00:00
Evan Cheng
9193514e2e Re-materialize all loads from fixed stack slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35660 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 07:40:01 +00:00
Evan Cheng
710216275b Trivially re-materializable instructions have spill weights that are half of what it would be otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-04 07:04:55 +00:00
Evan Cheng
595b6d121c Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35618 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:43:29 +00:00
Scott Michel
c9dc114578 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 21:36:32 +00:00
Evan Cheng
bcfd4665b5 Ugh. Copy coalescer does not update register numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35600 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 18:49:18 +00:00
Reid Spencer
dc1966e6ba For PR1297: 
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35567 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:01:49 +00:00
Reid Spencer
e9391fd9b5 For PR1297: 
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35547 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:35:23 +00:00
Reid Spencer
a4f9c4d29a For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35546 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:34:11 +00:00
Reid Spencer
577cc32d9a For PR1297: 
Change getOperationName to return std::string instead of const char*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35545 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 07:32:19 +00:00
Chris Lattner
c8d288f8fa move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35529 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 04:18:03 +00:00
Chris Lattner
d2f340b746 switch TL::getValueType to use MVT::getValueType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 04:05:24 +00:00
Chris Lattner
31442f9dc5 Add a -print-lsr-output option to LLC, to print the output of the LSR pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35522 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 00:24:43 +00:00
Chris Lattner
1436bb657d add one addressing mode description hook to rule them all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 23:14:50 +00:00
Dale Johannesen
2041a0ef75 Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 21:38:07 +00:00
Evan Cheng
7cb33c8652 Don't add the same MI to register reuse "last def/use" twice if it reads the 
register more than once.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35513 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 20:21:35 +00:00
Evan Cheng
2f52457539 Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length 
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35512 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 20:18:35 +00:00
Evan Cheng
b0b6c76ffe Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 07:56:46 +00:00
Evan Cheng
974777868c New entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35445 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 02:48:56 +00:00
Evan Cheng
197d19d11c Notes on re-materialization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35420 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 08:30:04 +00:00
Evan Cheng
2005a02f32 Move rematerialization out of beta. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35419 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 08:26:40 +00:00
Evan Cheng
7aff11a1ed Scale 1 is always ok. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35407 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:55:52 +00:00
Evan Cheng
caaf69107e Remove isLegalAddressImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:53:55 +00:00
Evan Cheng
baeccc8741 GEP index sinking fixes: 
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35403 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:49:39 +00:00
Evan Cheng
d592a28ca1 Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should 
not violate that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35396 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:30:37 +00:00
Anton Korobeynikov
dd43321079 Remove dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35380 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 12:05:48 +00:00
Anton Korobeynikov
b17b08d1f2 Split big monster into small helpers. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35379 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 11:29:11 +00:00
Evan Cheng
d0083bc5ec SDISel does not preserve all, it changes CFG and other info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35376 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 00:53:36 +00:00
Evan Cheng
018d6e1537 Don't call getOperandConstraint() if operand index is greater than 
TID->numOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35375 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 00:48:28 +00:00
Evan Cheng
ad7ccf34b5 Fix for PR1266. Don't mark a two address operand IsKill. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35365 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 22:40:42 +00:00
Evan Cheng
32eb1f1ca4 Change findRegisterUseOperand() to return operand index instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35363 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 22:37:45 +00:00
Dale Johannesen
c6b9ef80a8 Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 
hopefully forestall similar errors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35362 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 22:23:54 +00:00
Evan Cheng
15213b77cf SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 07:12:51 +00:00
Anton Korobeynikov
3a84b9baf6 First step of switch lowering refactoring: perform worklist-driven 
strategy, emit JT's where possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35338 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 15:07:15 +00:00
Chris Lattner
5df99b376f Implement support for vector operands to inline asm, implementing 
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35332 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 05:00:54 +00:00
Chris Lattner
c13dd1cf4c implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35327 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 04:35:41 +00:00
Chris Lattner
065421f99f Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35324 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:18:14 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:14:49 +00:00
Chris Lattner
82dcb4fe23 don't rely on ADL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35299 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 17:37:03 +00:00
Evan Cheng
dae54ce7fc Adjust offset to compensate for big endian machines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 00:02:43 +00:00
Evan Cheng
e177e307fc Make sure SEXTLOAD of the specific type is supported on the target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:13:36 +00:00
Evan Cheng
b37b80ce46 Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 20:55:21 +00:00
Evan Cheng
0b063def98 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 02:16:52 +00:00
Dan Gohman
ecb7a77885 Change uses of Function::front to Function::getEntryBlock for readability. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35265 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 16:38:57 +00:00
Evan Cheng
c88138fb5e More opportunities to reduce load size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35254 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 01:54:19 +00:00
Evan Cheng
2c3535d2a6 Fix for PR1257. Bug in live range shortening as a result of copy coalescing 
where the destination is dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35252 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 01:26:05 +00:00
Dale Johannesen
fa4bce2b76 repair x86 performance, dejagnu problems from previous change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 21:51:52 +00:00
Evan Cheng
007b69eeaa fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35239 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 20:14:05 +00:00
Evan Cheng
c3c70881cf Potential spiller improvement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35228 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 22:22:38 +00:00
Dale Johannesen
8e59e163db do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 21:54:54 +00:00
Dale Johannesen
69cb9b78f1 maintain LiveIn when splitting blocks (register scavenging needs it) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35226 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 21:35:06 +00:00
Jeff Cohen
c01a53007a Fix some VC++ warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35224 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 20:43:18 +00:00
Lauro Ramos Venancio
a0a26b7454 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35220 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 20:09:03 +00:00
Evan Cheng
29a68fb5b7 Minor bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35219 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 19:32:11 +00:00
Lauro Ramos Venancio
8334b9fa3b CopyToReg source operand can be a physical register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35213 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 16:46:44 +00:00
Evan Cheng
2638e1a6b9 First cut trivial re-materialization support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35208 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:13:50 +00:00
Evan Cheng
757072d954 Remove -reduce-joining-phys-regs options. Make it on by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35165 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 18:08:26 +00:00
Evan Cheng
79b098445b Minor bug fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35153 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 04:22:35 +00:00
Evan Cheng
cf596c54d4 - Merge UsedBlocks info after two virtual registers are coalesced. 
- Use distance to closest use to determine whether to abort coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35141 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 09:05:55 +00:00
Evan Cheng
e951cd1647 Keep UsedBlocks info accurate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35140 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-18 09:02:31 +00:00
Evan Cheng
c6a2410d58 Track the BB's where each virtual register is used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35135 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 09:29:54 +00:00
Evan Cheng
ba1a3df608 Joining a live interval of a physical register with a virtual one can turn out 
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35134 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 09:27:35 +00:00
Evan Cheng
db264ae07f Use SmallSet instead of std::set. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35133 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 08:53:30 +00:00
Evan Cheng
2edd563825 If sdisel has decided to sink GEP index expression into any BB. Replace all uses 
in that BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 08:22:49 +00:00
Evan Cheng
9e2d86add8 Turn on GEP index sinking by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35127 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 18:32:30 +00:00
Evan Cheng
9f5ead9601 Stupid bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35126 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 17:50:20 +00:00
Evan Cheng
3cd4e5095b Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:46:27 +00:00
Evan Cheng
14245a9d62 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 08:42:32 +00:00
Evan Cheng
56fdd7af88 Debugging output stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35117 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-15 21:19:28 +00:00
Evan Cheng
c6deb3d447 Estimate a cost using the possible number of scratch registers required and use 
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-14 22:43:40 +00:00
Evan Cheng
61230d18d2 Try schedule def + use closer whne Sethi-Ullman numbers are the same. 
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-13 23:25:11 +00:00
Evan Cheng
c289faf015 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35076 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-12 23:37:10 +00:00
Evan Cheng
e2ee99620f If a virtual register is already marked alive in this block, that means it is 
alive in one of the successor block. Do not add it to the kill list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35041 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 09:48:56 +00:00
Evan Cheng
219705131d Print preds / succs BB numbers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35040 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 08:29:08 +00:00
Evan Cheng
f0e3bb1333 Avoid variable shadowing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35039 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-09 06:02:17 +00:00
Chris Lattner
6dfc6806bf implement support for floating point constants used as inline asm memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 22:29:47 +00:00
Chris Lattner
b4ddac9bf7 make this fail even in non-assert builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35025 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 07:07:03 +00:00
Anton Korobeynikov
d0b82b301d Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35008 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 16:25:09 +00:00
Anton Korobeynikov
6a143590b3 Cleanup: make SetCounter an instance variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35007 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 08:25:02 +00:00
Evan Cheng
83060c544b Avoid combining indexed load further. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35005 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 08:07:03 +00:00
Anton Korobeynikov
a6199c87c2 Fix DWARF debugging information on x86/Linux and (hopefully) 
Mingw32/Cygwin targets. This fixes PR978


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35000 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 02:47:57 +00:00
Evan Cheng
caddd590f7 Minor bug fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34985 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 21:58:15 +00:00
Devang Patel
0f54dcbf07 Now LoopStrengthReduce is a LoopPass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34984 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 21:14:09 +00:00
Chris Lattner
edf2e8da25 big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not 
the lo-reg first.  This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34983 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 20:01:06 +00:00
Anton Korobeynikov
fb269cf3e7 Small eye-candy: use asciz directive everywhere, where possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34981 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 19:25:02 +00:00
Evan Cheng
87f8bf65dd If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 10:02:38 +00:00
Evan Cheng
b74a3e6fda Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34964 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 10:01:25 +00:00
Anton Korobeynikov
0db79d86de Enumerate SDISel formal parameter attributes. Make use of new 
enumeration.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-06 06:10:33 +00:00
Jeff Cohen
ca5183d445 Unbreak VC++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34917 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-05 00:00:42 +00:00
Chris Lattner
b654176cb4 fold away addc nodes when we know there cannot be a carry-out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:40:38 +00:00
Chris Lattner
bcf2484450 generalize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34910 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:08:45 +00:00
Chris Lattner
91153686f0 canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of 
addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34909 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:03:15 +00:00
Chris Lattner
175415e116 eliminate some ops if they have an undef RHS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 20:01:46 +00:00
Reid Spencer
d7f3de655b Remove unneeded header file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34903 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-04 04:41:04 +00:00
Chris Lattner
8b2d42c949 Fix CodeGen/Generic/fpowi-promote.ll and PR1239 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34893 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-03 23:43:21 +00:00
Chris Lattner
a9569f10de Add an expand action for ISD label which just deletes the label. 
This "fixes" PR1238.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34890 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-03 19:21:38 +00:00
Evan Cheng
a7288df62d Only propagate IsKill if the last use is a kill. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34878 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-03 06:32:37 +00:00
Nate Begeman
af80638869 http://llvm.org/bugs/show_bug.cgi?id=1237 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34875 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-03 06:18:18 +00:00
Evan Cheng
a16d4429e4 Watch out for cases like this: 
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
        %reg1032 = tMOVrr %r3<kill>
        %reg1033 = tMOVri8 1
        %reg1034 = tMOVri8 0
        tCMPi8 %reg1029<kill>, 0
        tBcc mbb<entry,0x8b06a10>, 0
    Successors according to CFG: 0x8b06980 0x8b06a10

entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
    Predecessors according to CFG: 0x8b056f0
        %reg1036 = tMOVrr %reg1034<kill>
    Successors according to CFG: 0x8b06a10

entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
    Predecessors according to CFG: 0x8b056f0 0x8b06980
        %reg1024<dead> = tMOVrr %reg1030<kill>
        ...

reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34866 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-03 02:18:00 +00:00
Evan Cheng
5de3b7f351 Mark dead def as unused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34844 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-02 10:43:16 +00:00
Evan Cheng
7b466d0481 Dead live-in detection bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34843 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-02 10:41:15 +00:00
Evan Cheng
6b448092bf - Keep track all def and uses of stack slot available in register. 
- Available value use may be deleted (e.g. noop move).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34841 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-02 08:52:00 +00:00
Evan Cheng
c3dd314b78 Invalidate last use of a reused register if the use is a deleted noop copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34839 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-02 05:41:42 +00:00
Jim Laskey
0102ca8f5a Emit eh filter info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34805 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 20:26:43 +00:00
Jim Laskey
59e8434a85 Collect eh filter info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34804 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 20:25:32 +00:00
Jim Laskey
0b4711bd94 Lower eh filter intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34802 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 20:24:30 +00:00
Evan Cheng
a81a5ab357 Delete register scavenger when done with it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34786 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-01 10:23:33 +00:00