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786225adf0
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110 Commits

Author SHA1 Message Date
Evan Cheng
786225adf0 Make use of getStore(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-05 23:01:46 +00:00
Evan Cheng
c548428c5d Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 
extra operand to LOADX to specify the exact value extension type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-04 00:56:09 +00:00
Evan Cheng
c356a572e3 Reflects MachineConstantPoolEntry changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-12 21:04:05 +00:00
Evan Cheng
95514bae73 SelectNodeTo now returns a SDNode*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29901 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-26 08:00:10 +00:00
Evan Cheng
9ade218533 Select() no longer require Result operand by reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-26 05:34:46 +00:00
Evan Cheng
6da2f3268d Match tblgen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29895 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-26 01:07:58 +00:00
Evan Cheng
23329f5e03 SelectNodeTo() may return a SDOperand that is different from the input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-16 07:30:09 +00:00
Evan Cheng
64a752f7c7 Match tablegen changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:08:15 +00:00
Chris Lattner
bd564bfc63 Start eliminating temporary vectors used to create DAG nodes. Instead, pass 
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-08 02:23:42 +00:00
Evan Cheng
2ef88a09b7 Match tablegen isel changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-07 22:28:20 +00:00
Evan Cheng
2641cad180 Remove InFlightSet hack. No longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-28 00:47:19 +00:00
Evan Cheng
a7dc4a59cb Type of extract_element index operand should be iPTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28797 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-15 08:18:06 +00:00
Evan Cheng
6848be1a27 Change RET node to include signness information of the return values. i.e. 
RET chain, value1, sign1, value2, sign2, ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-26 23:10:12 +00:00
Chris Lattner
8b5fbc5cd4 Add support for the missing FP condition codes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28482 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-25 22:26:02 +00:00
Evan Cheng
6a3d5a62f0 Assert if InflightSet is not cleared after instruction selecting a BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-25 00:24:28 +00:00
Evan Cheng
afe358e7d4 Clear HandleMap and ReplaceMap after instruction selection. Or it may cause 
non-deterministic behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-24 20:46:25 +00:00
Chris Lattner
d74ea2bbd8 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-24 17:04:05 +00:00
Chris Lattner
27aaa398ee Remove dead variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28247 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-12 17:31:21 +00:00
Nate Begeman
37efe67645 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 18:53:45 +00:00
Nate Begeman
f15485a8d0 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 01:32:24 +00:00
Chris Lattner
420736dc85 #include Intrinsics.h into all dag isels 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 06:47:10 +00:00
Nate Begeman
81e8097377 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 01:40:33 +00:00
Chris Lattner
9601a86a64 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:08:37 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Nate Begeman
368e18d56a Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 21:11:51 +00:00
Chris Lattner
6fa1f57c66 Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc. 
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26202 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 06:41:34 +00:00
Chris Lattner
94dd29216c Switch targets over to using SelectionDAG::getCALLSEQ_START to create 
CALLSEQ_START nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 09:00:43 +00:00
Chris Lattner
ad7a3e6208 Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr 
intrinsics.

Autogen frameindex matcher


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26107 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-10 07:35:42 +00:00
Evan Cheng
7e9b26fc73 Match getTargetNode() changes (now return SDNode* instead of SDOperand). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26085 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 07:17:49 +00:00
Chris Lattner
3029f92051 Adjust to MachineConstantPool interface change: instead of keeping a 
value/alignment pair for each constant, keep a value/offset pair.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26078 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 04:46:04 +00:00
Evan Cheng
34167215a8 Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26067 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 00:37:58 +00:00
Chris Lattner
c26017a4ae Fix the Sparc backend with Evan's recent tblgen changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26009 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-05 08:35:50 +00:00
Evan Cheng
900c826bc7 Use SelectRoot() as the entry to any tblgen based isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25998 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-05 06:51:51 +00:00
Chris Lattner
7c90f73a1b Rename SPARC V8 target to be the LLVM SPARC target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-05 05:50:24 +00:00
Chris Lattner
c275dfa727 Custom lower VAARG for the case when we are doing vaarg(double). In this 
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25967 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 08:31:30 +00:00
Evan Cheng
b8973bd8f5 Allow the specification of explicit alignments for constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25855 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 22:23:14 +00:00
Chris Lattner
c03468bafa add a missing break that caused a lot of failures last night :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25851 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 17:20:06 +00:00
Chris Lattner
7a4d2913ea treat conditional branches the same way as conditional moves (giving them 
an operand that contains the condcode), making things significantly simpler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25840 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 06:56:30 +00:00
Chris Lattner
6788faa06a compactify all of the integer conditional moves into one instruction that takes 
a CC as an operand.  Much smaller, much happier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25839 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 06:49:09 +00:00
Chris Lattner
86638b94c1 Compile this: 
void %X(int %A) {
        %C = setlt int %A, 123          ; <bool> [#uses=1]
        br bool %C, label %T, label %F

T:              ; preds = %0
        call int %main( int 0 )         ; <int>:0 [#uses=0]
        ret void

F:              ; preds = %0
        ret void
}

to this:

X:
        save -96, %o6, %o6
        subcc %i0, 122, %l0
        bg .LBBX_2      ! F
        nop
...

not this:

X:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        subcc %i0, 122, %l2
        bg .LBBX_4      !
        nop
.LBBX_3:        !
        or %g0, %l0, %l1
.LBBX_4:        !
        subcc %l1, 0, %l0
        bne .LBBX_2     ! F
        nop


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25833 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 05:05:52 +00:00
Chris Lattner
b716343851 I don't see why this optimization isn't safe, but it isn't, so disable it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25829 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 02:45:52 +00:00
Chris Lattner
2adc05cf5b Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25819 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 22:20:49 +00:00
Chris Lattner
3772bcb333 Revamp the ICC/FCC reading instructions to be parameterized in terms of the 
SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25815 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 07:43:04 +00:00
Chris Lattner
9072c05cd8 Compile: 
uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 06:14:02 +00:00
Chris Lattner
76afdc9a80 First step towards V9 instructions in the V8 backend, two conditional move 
patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 05:35:57 +00:00
Chris Lattner
dea9528f7f When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold 
the two operations together.  This allows us to compile this:

void %two(int %a, int* %b) {
        %tmp.2 = seteq int %a, 0
        %tmp.0.0 = select bool %tmp.2, int 10, int 20
        store int %tmp.0.0, int* %b
        ret void
}

into:

two:
        save -96, %o6, %o6
        or %g0, 20, %l0
        or %g0, 10, %l1
        subcc %i0, 0, %l2
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        st %l1, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

instead of:

two:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        or %g0, 20, %l2
        or %g0, 10, %l3
        subcc %i0, 0, %l4
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        subcc %l1, 0, %l0
        bne .LBBtwo_4   ! entry
        nop
.LBBtwo_3:      ! entry
        or %g0, %l2, %l3
.LBBtwo_4:      ! entry
        st %l3, [%i1]
        restore %g0, %g0, %g0
        retl
        nop


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25806 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 04:34:44 +00:00
Chris Lattner
c6fd6cd65c Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 04:09:27 +00:00
Chris Lattner
4a397e0e94 Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes, 
allowing redundant and's to be eliminated by the dag combiner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25800 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 03:51:45 +00:00
Chris Lattner
44ea7b1a6c Use V8ISD::CALL instead of ISD::CALL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25716 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 23:30:03 +00:00
Nate Begeman
ee625573b5 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 21:09:22 +00:00