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17840 Commits

Author SHA1 Message Date
Bob Wilson
d11c57a937 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 17:50:30 +00:00
Evan Cheng
c3a20bab75 Fix PLD encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:48:34 +00:00
Kevin Enderby
9e56fb12c5 Changed llvm-mc arm target to give an error if .syntax divided is used. Since 
only .syntax unified is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:22:36 +00:00
David Greene
54d8ebafc7 [AVX] Clean up the code to configure target lowering for AVX. Specify 
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 22:38:56 +00:00
Roman Divacky
bf7553210a Introduce virtual ParseRegister method in TargetAsmParser. 
Create override of this method in X86/ARM/MBlaze.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 17:14:22 +00:00
Eric Christopher
4a2b316762 Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124357 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 05:44:56 +00:00
NAKAMURA Takumi
40ccb798cc lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64. 
CALL64 marks %xmm* as dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 03:20:19 +00:00
Bill Wendling
8cb415e4c0 Add support for printing out floating point values from the ARM assembly 
parser. The parser will always give us a binary representation of the floating
point number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 20:57:43 +00:00
David Greene
cfe33c46aa [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a 
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 19:13:22 +00:00
David Greene
91585098ef [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default 
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 15:38:49 +00:00
Bruno Cardoso Lopes
1b10d5be40 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:28:14 +00:00
Bill Wendling
717082b9bd Add needed braces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:06:22 +00:00
NAKAMURA Takumi
7754f85885 Target/X86: Tweak win64's tailcall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:04:09 +00:00
NAKAMURA Takumi
e5fffe9c3f Fix whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:03:37 +00:00
NAKAMURA Takumi
c5b7a4223d lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 01:28:06 +00:00
NAKAMURA Takumi
b901076387 lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 01:27:58 +00:00
Bill Wendling
0f4db7efa1 Revert 124230. It was causing test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:48:36 +00:00
Bill Wendling
261b9c1a35 The floating point value is encoded in its binary form as an Imm. Convert it 
appropriately so that it prints out the decimal representation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:27:46 +00:00
Evan Cheng
7cfa656ad8 Don't merge restore with tail call instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 01:28:33 +00:00
Anton Korobeynikov
5899a60d2f Provide correct registers for EH stuff on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 22:38:45 +00:00
Chris Lattner
ccea167db5 fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 03:42:46 +00:00
Chris Lattner
96c0771c01 this isn't a memset, we do convert dest[i] to one though :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 02:32:00 +00:00
Chris Lattner
7ea7d32de6 with recent work, we now optimize this into: 
define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 01:12:18 +00:00
Anders Carlsson
f330b3227a Add a memset loop that LoopIdiomRecognize doesn't recognize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 20:31:00 +00:00
Rafael Espindola
dd0dfdf8be Initialize MCNoExecStack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 18:50:12 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:55:27 +00:00
Ted Kremenek
584520e8e2 Null initialize a few variables flagged by 
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:05:06 +00:00
Rafael Espindola
0cf5e3d51d Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 05:43:40 +00:00
Rafael Espindola
1c13026e8f Remove more duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:43:11 +00:00
Rafael Espindola
c85dca66e6 Remove duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:28:49 +00:00
Venkatraman Govindaraju
8184e289db Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-22 13:05:16 +00:00
Venkatraman Govindaraju
e105a3901f Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju
fc3faa75cb Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 22:00:00 +00:00
Evan Cheng
53519f015e Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 18:55:51 +00:00
Bruno Cardoso Lopes
030160073d Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 14:07:40 +00:00
Venkatraman Govindaraju
46713296e0 Implement support for byval arguments in Sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 14:00:01 +00:00
Andrew Trick
c8bfd1d78f Convert -enable-sched-cycles and -enable-sched-hazard to -disable 
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 05:51:33 +00:00
Evan Cheng
d7e3cc840b Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative 
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 23:55:07 +00:00
Bruno Cardoso Lopes
e47f3751d7 Fix the encoding and parsing of clrex instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
6456121d5c Change instruction names for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
8dd37f7b7d Add cdp/cdp2 instructions for thumb/thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
b32f7a5f4b - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
6b3a999f22 Add mcr*2 and mr*c2 support to thumb2 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
fa5bd27fbe Add mcr* and mr*c support to thumb targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:35:57 +00:00
Kalle Raiskila
5106b84506 Allow sign-extending of i8 and i16 to i128 on SPU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 15:49:06 +00:00
Bruno Cardoso Lopes
8197754be5 Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 13:17:59 +00:00
Evan Cheng
907276dc44 Correct itinerary entry for t2MOV_pic_ga_add_pc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123907 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 08:43:03 +00:00
Evan Cheng
9fe2009956 Sorry, several patches in one. 
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 08:34:58 +00:00
Venkatraman Govindaraju
71e39dac0c Sparc backend: Implements a delay slot filler that attempt to fill delay slots 
with useful instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 05:08:26 +00:00
Bruno Cardoso Lopes
3abd75bf1d Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 16:56:52 +00:00
Daniel Dunbar
ec91d52a77 ARM/ISel: Factor out isScaledConstantInRange() helper. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 15:12:16 +00:00
Andrew Trick
32cec0a756 For ARM subtargets with useNEONForSinglePrecisionFP, double count uses 
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:35:27 +00:00
Andrew Trick
7fa75ce11d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:26:13 +00:00
Evan Cheng
fc8475bde9 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes
61505907f5 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
e7255a80e3 Fix MRS encoding for arm and thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
892fc6d7b6 Fix the encoding of t2ISB by using the right class and also parse it correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
fdcee77887 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
a461d42228 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:45:56 +00:00
Jim Grosbach
ff12a8bd99 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123769 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:59:19 +00:00
Bruno Cardoso Lopes
fb67faa661 Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123768 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes
6b9028251c Negative zero is not legal on mips. Patch by Sasa Stankovic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:41:41 +00:00
Bruno Cardoso Lopes
b1fce0a016 Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:38:25 +00:00
Bruno Cardoso Lopes
8be7611245 Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:29:17 +00:00
Chris Lattner
908d8e82b5 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123752 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 07:47:48 +00:00
Venkatraman Govindaraju
687ae9606b SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 06:09:55 +00:00
Daniel Dunbar
4b462672d2 McARM: Use accessors where appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:27 +00:00
Daniel Dunbar
6ec56204f3 McARM: Fill in ASMOperand::dump() for memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:21 +00:00
Daniel Dunbar
2637dc9a25 McARM: Make ARMOperand use a union where appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:15 +00:00
Daniel Dunbar
05d8b71424 McARM: Unify ParseMemory() successfull return. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123740 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:24 +00:00
Daniel Dunbar
0571093f4c McARM: Early exit on failure (NEFC). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:17 +00:00
Daniel Dunbar
d3df5f32c0 McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. 
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:11 +00:00
Daniel Dunbar
023835d51b McARM: Add a variety of asserts on the sanity of memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:05 +00:00
Daniel Dunbar
81f453c4b9 McARM: Use a consistent marker for not-set OffsetRegNum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:33:57 +00:00
Daniel Dunbar
2e3cea3153 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 03:06:03 +00:00
Eric Christopher
cdfe3c359b The stub routine that we're calling uses test and so clobbers 
the flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 01:37:20 +00:00
Chris Lattner
32899199c0 minor change to rafael's recent patches: if something is 
constant but requires a unique address, we can still put it in a
readonly section, just not a mergable one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 01:23:44 +00:00
Jeffrey Yasskin
955ed73d12 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 00:51:23 +00:00
Douglas Gregor
e735882224 Add a missing <cctype> include, from Joerg Sonnenberger! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-17 19:17:01 +00:00
Kalle Raiskila
9dcb98cbe7 Split up RotateShift itinerary in SPU. 
'rotq*' and 'shlq*' instructions go to the odd pipeline,
wheras the inter-vector equivalents 'rot*', 'shl*' go 
to the even.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-17 13:33:19 +00:00
Kalle Raiskila
8702e8be8d Don't crash SPU BE with memory accesses with big alignmnet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123620 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-17 11:59:20 +00:00
Evan Cheng
5de5d4b6d0 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-17 08:03:18 +00:00
Anton Korobeynikov
1d8334eabc Provide instruction sizes for ARMv5 variants of MUL instructions. 
This fixes PR8987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 21:28:33 +00:00
Anders Carlsson
5822b86e4d Update README.txt to remove the DAE enhancement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 21:26:15 +00:00
Rafael Espindola
7010401c6b Only put unnamed_addr constants in mergeable sections. Fixes PR8297. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 17:19:34 +00:00
Chris Lattner
dec28ceb02 fix PR8514, a bug where the "heroic" transformation of shift/and 
into and/shift would cause nodes to move around and a dangling pointer
to happen.  The code tried to avoid this with a HandleSDNode, but 
got the details wrong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 08:48:11 +00:00
Chris Lattner
b0daffc609 add some commentary 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123572 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 06:39:44 +00:00
Evan Cheng
df55fea807 Spill R4 if it's going to be used to restore SP from FP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 05:14:33 +00:00
Venkatraman Govindaraju
c1a62834a2 Implement AnalyzeBranch in Sparc Backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 03:15:11 +00:00
Chris Lattner
9cd3da47f9 fix PR8981, a crash trying to form a conditional inc with a floating point compare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 02:56:53 +00:00
Chris Lattner
b99fdee325 reapply my fix for PR8961 with a tweak to properly handle 
multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 02:27:38 +00:00
Chandler Carruth
cad33c624e Simplify a README.txt entry significantly to expose the core issue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 01:40:23 +00:00
Eric Christopher
a0f720f500 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-15 00:25:09 +00:00
Bob Wilson
ca3f06963c Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-15 00:09:18 +00:00
Eric Christopher
41262da6cc Fix 80-cols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 23:50:53 +00:00
Ted Kremenek
d7f696edec 'HiReg' is written but never read. Nuke its 
declaration and its assignments.

Found by clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 22:34:13 +00:00
Anton Korobeynikov
3965b5e974 Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 21:58:08 +00:00
Anton Korobeynikov
e749911372 Cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 21:57:58 +00:00
Chris Lattner
d357e88740 revert my fastisel patch again which apparently still gives the 
llvm-gcc-i386-linux-selfhost buildbot heartburn...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 06:14:33 +00:00
Chris Lattner
9e27cc8049 reapply r123414 now that the botz are calmed down and the fix is already in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 04:24:28 +00:00
Evan Cheng
f3eb3bba16 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 02:38:49 +00:00
Chris Lattner
a899d1c264 r123414 broke llvm-gcc bootstrap apparently, revert 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 02:07:32 +00:00
Chris Lattner
d754041493 fix PR8961 - a fast isel miscompilation where we'd insert a new instruction 
after sext's generated for addressing that got folded.  Previously we compiled
test5 into:

_test5:                                 ## @test5
## BB#0:
        movq    -8(%rsp), %rax          ## 8-byte Reload
        movq    (%rdi,%rax), %rdi
        addq    %rdx, %rdi
        movslq  %esi, %rax
        movq    %rax, -8(%rsp)          ## 8-byte Spill
        movq    %rdi, %rax
        ret

which is insane and wrong.  Now we produce:

_test5:                                 ## @test5
## BB#0:
	movslq	%esi, %rax
	movq	(%rdi,%rax), %rax
	addq	%rdx, %rax
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 00:01:01 +00:00
Owen Anderson
0c9f250d54 Recognize alternative register names like ip -> r12. 
Fixes <rdar://problem/8857982>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:50:36 +00:00
Jakob Stoklund Olesen
f7ca976e74 Fix a few more places that should use MBB::getLastNonDebugInstr(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123408 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:47:43 +00:00
Chris Lattner
4c5456a56f typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:11:56 +00:00
Chris Lattner
4cd18f98f7 memcpy + metadata = bliss :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:08:15 +00:00
Owen Anderson
e4e5e2aae7 Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting 
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 21:46:02 +00:00
Jakob Stoklund Olesen
4f28c1c714 Teach frame lowering to ignore debug values after the terminators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 21:28:52 +00:00
Bob Wilson
422578547e Tidy comments, indentation, and 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 21:10:12 +00:00
Kevin Enderby
67b212e03b Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and 
directional local labels like 1f and 2b.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 20:32:36 +00:00
Jim Grosbach
5f3e2be7c9 When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly 
set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 19:16:48 +00:00
Evan Cheng
7597212abc Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 07:58:56 +00:00
Eric Christopher
04f5079ca1 Experiment with changing the default 32-bit linux stack alignment to 
16 bytes for PR8969. Update all testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 06:47:10 +00:00
Kevin Enderby
fef9ff4922 Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or 
.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 01:07:01 +00:00
Jason W Kim
8a8696db6b Change call to Error() to assert() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123350 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 00:27:00 +00:00
Jason W Kim
8dc602d245 Added clarifying comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 23:25:02 +00:00
Jason W Kim
650b7d76af JimG sez: "The value-kinds look like masks, but they're not consistently used 
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 23:21:49 +00:00
Bill Wendling
7caebff83d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 21:20:59 +00:00
Matt Beaumont-Gay
5f8a917b65 Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top 
of the switch block to appease GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 18:02:55 +00:00
Nick Lewycky
e45f2dfde6 Add another note taken from the gcc bugzilla. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 09:06:19 +00:00
Venkatraman Govindaraju
860b64cb1e Implement RETURNADDR and FRAMEADDR lowering in SPARC backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123310 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 05:08:36 +00:00
Venkatraman Govindaraju
c178308b23 Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to 
ensure %o7 is not assigned as the destination of getpcx instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 03:52:59 +00:00
Venkatraman Govindaraju
7d29ffbe5b Fix SPARC backend call instruction so that arguments passed through registers 
are correctly marked as used instead of passing all possible argument registers
as used.  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 03:18:21 +00:00
Matt Beaumont-Gay
676943b31a Prefer llvm_unreachable to assert(0) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 01:42:42 +00:00
Jason W Kim
86a97f2e4d 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 00:19:25 +00:00
Jason W Kim
9081b4b4cf Workaround for bug 8721. 
.s Test added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 23:53:41 +00:00
Venkatraman Govindaraju
f27df33b02 SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 22:38:28 +00:00
Evan Cheng
b72d2a92b7 Clean up ARM subtarget code by using Triple ADT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 21:46:47 +00:00
Daniel Dunbar
eb9f3f91c0 McARM: Fill in GetMnemonicAcceptInfo(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123253 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 19:06:29 +00:00
Bob Wilson
6c562f69fe Fix a comment: We now have intrinsics for vcvtr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 17:56:41 +00:00
Chris Lattner
3a5004dc3e Fix PR8946, a missing reg/reg form of movdqu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 17:04:55 +00:00
Daniel Dunbar
3771dd041f McARM: Sketch some logic for determining when to add carry set and predication code operands based on the "canonical mnemonic". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123239 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 15:59:53 +00:00
Daniel Dunbar
352e148cbe McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 15:59:50 +00:00
Kalle Raiskila
b9505f6bed Fix a thinko in 123226 that caused test failures on "other" platforms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123229 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 11:27:56 +00:00
Kalle Raiskila
76020ed6f3 Add a "nop filler" pass to SPU. 
Filling no-ops is done just before emitting of assembly,
when the instruction stream is final. No-ops are inserted
to align the instructions so the dual-issue of the pipeline
is utilized. This speeds up generated code with a minimum of 
1% on a select set of algorithms.

This pass may be redundant if the instruction scheduler and 
all subsequent passes that modify the instruction stream 
(prolog+epilog inserter, register scavenger, are there others?)
are made aware of the instruction alignments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 09:07:54 +00:00
Chandler Carruth
15ed90c859 Teach constant folding to perform conversions from constant floating 
point values to their integer representation through the SSE intrinsic
calls. This is the last part of a README.txt entry for which I have real
world examples.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 01:07:24 +00:00
Owen Anderson
da1c122da5 Fix a random missed optimization by making InstCombine more aggressive when determining which bits are demanded by 
a comparison against a constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 00:36:45 +00:00
Eric Christopher
94bb7b561c Even if we don't have 7 bytes of stack space we may need to save and 
restore the stack pointer from the frame pointer on thumbv6.

Fixes rdar://8819685


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 00:16:04 +00:00
Eric Christopher
4dd312f233 Expand on the safeness of restoring the sp from the fp a bit more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 23:10:59 +00:00
Chris Lattner
4a6fb94c40 +0.0 vs -0.0 differences can be handled by looking at the user of the 
operation in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123190 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 21:01:17 +00:00
Daniel Dunbar
8ab1112bdc McARM: Flush out hard coded known non-predicated mnemonic list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 21:01:03 +00:00
Daniel Dunbar
8d66b7852a McARM: Mark some T2 ...s instructions as codegen only, they aren't real 
instructions but are restricted pseudo forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 15:26:39 +00:00
Daniel Dunbar
238100aaa7 ARM/MC: Mark several '...S' instructions as codegen only, they aren't real 
instructions but are restricted pseudo forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 15:26:35 +00:00
Daniel Dunbar
6a5c22ed89 MC/ARM/AsmParser: Minor nitty fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123175 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 15:26:21 +00:00
Anton Korobeynikov
2c8bd754de Fix merge fallout 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 12:56:18 +00:00
Anton Korobeynikov
7af6fad0a7 Update CMake stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 12:39:23 +00:00
Anton Korobeynikov
16c29b5f28 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 12:39:04 +00:00
Daniel Dunbar
badbd2fde9 MC/ARM/AsmParser: Split out SplitMnemonicAndCC(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 12:24:52 +00:00
Jakob Stoklund Olesen
c9df025e33 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 02:58:51 +00:00
Chris Lattner
00a35d0f14 expand on a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123145 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 00:33:01 +00:00
Chris Lattner
66d7a5793c typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123142 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 23:48:41 +00:00
Chris Lattner
7cc4e304a6 xref a PR # 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 23:42:22 +00:00
Chandler Carruth
fb00e2715b Add a note about the inability to model FP -> int conversions which 
perform rounding other than truncation in the IR. Common C code for this
turns into really an LLVM intrinsic call that blocks a lot of further
optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 22:36:18 +00:00
Jakob Stoklund Olesen
be97e906e0 Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 
physical register numbers.

This makes the hack used in LiveInterval official, and lets LiveInterval be
oblivious of stack slots.

The isPhysicalRegister() and isVirtualRegister() predicates don't know about
this, so when a variable may contain a stack slot, isStackSlot() should always
be tested first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 21:17:37 +00:00
Chandler Carruth
96b1b6c135 Add a note about a missed FP optimization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 21:00:19 +00:00
Chandler Carruth
694d753b09 Another missed memset in std::vector initialization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 11:29:57 +00:00
Chandler Carruth
27a2a13b62 Fix a cut-paste-o so that the sample code is correct for my last note. 
Also, switch to a more clear 'sink' function with its declaration to
avoid any confusion about 'g'. Thanks for the suggestion Frits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 10:10:59 +00:00
Chandler Carruth
e5ca494ae6 Another missed optimization of trivial vector code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 09:58:36 +00:00
Chandler Carruth
d8723a9b55 Add a note about vector's size-constructor producing dead stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 09:58:33 +00:00
Jakob Stoklund Olesen
4314268128 Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance. 
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 03:05:53 +00:00
Chandler Carruth
75fbd3793f Add a note about a missed memset optimization from std::fill. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-09 01:32:55 +00:00
Jakob Stoklund Olesen
b258135301 Fix the last virtual register enumerations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-08 23:11:11 +00:00
Evan Cheng
55d4200336 Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-08 01:24:27 +00:00
Evan Cheng
c36b7069b4 Do not model all INLINEASM instructions as having unmodelled side effects. 
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 23:50:32 +00:00
Bob Wilson
70f85730b1 Add an explanatory message for an assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 23:40:46 +00:00
Matt Beaumont-Gay
697970286a Eliminate variable only used in debug builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 22:34:58 +00:00
Bob Wilson
11a1dfffc8 Lower some BUILD_VECTORS using VEXT+shuffle. 
Patch by Tim Northover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123035 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 21:37:30 +00:00
Benjamin Kramer
eaff66a895 Revert 122959, it needs more thought. Add it back to README.txt with additional notes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 20:42:20 +00:00
Evan Cheng
a5e1362f96 Revert r122955. It seems using movups to lower memcpy can cause massive regression (even on Nehalem) in edge cases. I also didn't see any real performance benefit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 19:35:30 +00:00
Bob Wilson
5e8b833707 Add ARM patterns to match EXTRACT_SUBVECTOR nodes. 
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.

The test changes are needed to keep those spill-q tests from testing aligned
spills and restores.  If the only aligned stack objects are spill slots, we
no longer realign the stack frame.  Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-07 04:59:04 +00:00
Chris Lattner
01cdc2016d With Benjamin's recent amazing patches, we should be able to do even better things :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122978 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 22:25:00 +00:00
Bob Wilson
6819dbb6f8 PR8921: LDM/POP do not support interworking prior to v5t. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 19:24:41 +00:00
Bob Wilson
28f1015e36 Remove extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 19:24:36 +00:00
Bob Wilson
0fef58465c Fix comment typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122968 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 19:24:32 +00:00
Benjamin Kramer
fa36680076 Add a note from llvmdev, this time with more info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 17:35:50 +00:00
Rafael Espindola
2f867a63da Correctly disassemble truncated asm. 
Patch by Richard Simth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 16:48:42 +00:00
Benjamin Kramer
7d9f51f4b5 EarlyCSE does this now (and GVN always did it). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 13:19:46 +00:00
Benjamin Kramer
240d42d185 InstCombine: If we call llvm.objectsize on a malloc call we can replace it with the size passed to malloc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 13:11:05 +00:00
Benjamin Kramer
5191e7cc26 Remove dead code and silence warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122957 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 13:01:02 +00:00
Evan Cheng
461f1fc359 Use movups to lower memcpy and memset even if it's not fast (like corei7). 
The theory is it's still faster than a pair of movq / a quad of movl. This
will probably hurt older chips like P4 but should run faster on current
and future Intel processors. rdar://8817010


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 07:58:36 +00:00
Chris Lattner
cce240d26b add a note about object size from drystone, add a poorly optimized loop from 179.art. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 07:41:22 +00:00
Chris Lattner
c1853e4a03 add a trivial instcombine missed in Dhrystone 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 07:09:23 +00:00
Evan Cheng
0521928ae7 Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy 
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 06:52:41 +00:00
Bill Wendling
a99ec28134 PR8919 - LLVM incorrectly generates "_alloca" as the stack probing call. That 
works only on MinGW32. On 64-bit, the function to call is "__chkstk".
Patch by KS Sreeram!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 00:50:34 +00:00
Bill Wendling
78d15761e4 PR8918 - When used with MinGW64, LLVM generates a "calll __main" at the 
beginning of the "main" function. The assembler complains about the invalid
suffix for the 'call' instruction. The right instruction is "callq __main".
Patch by KS Sreeram!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122933 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 00:47:10 +00:00
Chris Lattner
c010e61ae1 fix PR8900, a shuffle miscompilation. Patch by Nadav Rotem! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-05 22:28:46 +00:00
Chris Lattner
c46ec649b1 silence more self assignment warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122920 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-05 22:26:52 +00:00
Chris Lattner
54c6d6f42d fix some -Wself-assign warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-05 18:41:05 +00:00
Wesley Peck
3d2148f5ac Commit 122778 broke DWARF debug output when using the MBlaze backend. Fixed by overriding TargetFrameInfo::getFrameIndexOffset to take into account the new frame index information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-05 17:34:20 +00:00
Jakob Stoklund Olesen
631ee4b89f Use the EdgeBundles analysis in X86FloatingPoint instead of recomputing CFG 
bundles in the pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-04 21:10:11 +00:00
Jakob Stoklund Olesen
8dd070edc2 Turn the EdgeBundles class into a stand-alone machine CFG analysis pass. 
The analysis will be needed by both the greedy register allocator and the
X86FloatingPoint pass. It only needs to be computed once when the CFG doesn't
change.

This pass is very fast, usually showing up as 0.0% wall time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-04 21:10:05 +00:00
Dale Johannesen
1e08cd1eae Eliminate a warning compiling with llvm-gcc. (IMO the 
warning is overzealous but gcc is what it is.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122829 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-04 19:31:24 +00:00
Andrew Trick
6018deefe8 Fix the ARM IIC_iCMPsi itinerary and add an important assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-04 00:32:57 +00:00
Bill Wendling
2c502f915f Formatting changes. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-03 23:59:05 +00:00
Evan Cheng
7158e08b8e Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack in 
prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if
the adjustment is 4 in 32-bit mode.

In the epilogue, takes care to pop to a caller-saved register that's not live
at the exit (either return or tailcall instruction).
rdar://8771137


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-03 22:53:22 +00:00
Wesley Peck
b020808f0d Fix more stack layout issues in the MBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-03 21:40:26 +00:00
Benjamin Kramer
80220369b0 Try to reuse the value when lowering memset. 
This allows us to compile:
  void test(char *s, int a) {
    __builtin_memset(s, a, 15);
  }
into 1 mul + 3 stores instead of 3 muls + 3 stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-02 19:57:05 +00:00
Oscar Fuentes
3458534f11 A workaround for a bug in cmake 2.8.3 diagnosed on PR 8885. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-02 19:32:31 +00:00
Chris Lattner
527b47d189 update a bunch of entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122700 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-02 18:31:38 +00:00