Evan Cheng
b620724e61
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-01 00:16:10 +00:00
David Goodwin
c9d138f505
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27 19:59:26 +00:00
David Goodwin
e1e52edfff
Fix typo in addrmode definition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22 22:24:31 +00:00
Evan Cheng
446c428bf3
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 06:43:01 +00:00
David Goodwin
3ca524e336
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75254 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 17:03:29 +00:00
Evan Cheng
dda0f4cb79
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 22:51:32 +00:00
Bob Wilson
205a5ca6cf
Implement NEON vld1 instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 18:11:30 +00:00
Evan Cheng
34a0fa362d
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 01:46:35 +00:00
Evan Cheng
e88d5cee9d
Thumb2 pre/post indexed loads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 07:28:31 +00:00
Evan Cheng
d770d9e7d1
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-02 06:38:40 +00:00
Bob Wilson
8b024a5eb5
Add a new addressing mode for NEON load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 23:16:05 +00:00
David Goodwin
5e47a9a6e4
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 18:04:13 +00:00
Evan Cheng
f3c21b857b
A few more load instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 02:15:48 +00:00
Evan Cheng
055b0310f8
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29 07:51:04 +00:00
Evan Cheng
9cb9e6778c
Renaming for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 02:26:13 +00:00
Evan Cheng
0aa1d8c52d
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25 02:08:06 +00:00
Evan Cheng
09c39fcf83
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 19:38:13 +00:00
Evan Cheng
f49810c7e6
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-23 17:48:47 +00:00
Bob Wilson
5bafff36c7
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22 23:27:02 +00:00
Evan Cheng
ffa6d962a7
Handle the rest of pseudo instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 23:36:57 +00:00
Evan Cheng
148cad8b30
Fix pre- and post-indexed load / store encoding bugs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 07:34:59 +00:00
Evan Cheng
3c4a4ffa3d
Consolidate formats; fix FCMPED etc. encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-12 07:18:38 +00:00
Evan Cheng
80a119842d
Fix VFP conversion instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-12 06:41:41 +00:00
Evan Cheng
0a0ab1387a
Fix FMDRR encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-11 22:46:12 +00:00
Evan Cheng
cd8e66a1ef
Encode VFP load / store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-11 21:48:44 +00:00
Evan Cheng
78be83d7c2
Encode VFP conversion instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-11 19:40:26 +00:00
Evan Cheng
96581d3633
Encode VFP arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-11 02:11:05 +00:00
Evan Cheng
4df60f5491
Jump table JIT support. Work in progress.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-07 09:06:08 +00:00
Evan Cheng
8b59db3f2c
Encode misc arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-07 01:41:35 +00:00
Evan Cheng
97f48c39fd
Encode extend instructions; more clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 22:15:19 +00:00
Evan Cheng
12c3a533c5
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 17:48:05 +00:00
Evan Cheng
d87293ce78
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 08:47:38 +00:00
Evan Cheng
eb4f52eb62
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 03:35:07 +00:00
Evan Cheng
fbc9d412ef
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-06 01:21:28 +00:00
Evan Cheng
83b5cf0272
Encode pic load / store instructions; fix some encoding bugs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 23:22:34 +00:00
Evan Cheng
edda31c412
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 18:35:52 +00:00
Evan Cheng
e7fe672445
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04 17:57:07 +00:00
Jim Grosbach
0a4b9dc9b1
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03 18:38:31 +00:00
Jim Grosbach
2642196a65
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-14 20:36:24 +00:00
Evan Cheng
7fd7ca4e7f
Fix addrmode1 instruction encodings; fix bx_ret encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 07:53:38 +00:00
Evan Cheng
29c57c34ef
Specify instruction encoding using range list to avoid endianess issues.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 07:16:21 +00:00
Evan Cheng
05fc966401
Revert 56176. All those instruction formats are still needed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-13 01:35:33 +00:00
Evan Cheng
a964b7dffe
Eliminate unnecessary instruction formats.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12 23:15:39 +00:00
Evan Cheng
49a9f2958d
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56172 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12 22:45:55 +00:00
Evan Cheng
3aac788365
Control flow instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b
ldm / stm instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d
AXI2 and AXI3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:34:13 +00:00
Evan Cheng
4bbd5f8a9c
Reorganize instruction formats again; AXI1 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:19:00 +00:00
Evan Cheng
840917be2c
addrmode3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:00:14 +00:00
Evan Cheng
0d14fc8cd5
Reorganize some instruction format definitions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:51:14 +00:00
Evan Cheng
93912739c9
Rest of addrmode2 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec
Addr2 word / byte load encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 19:02:21 +00:00
Evan Cheng
b7880ac470
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 18:32:16 +00:00
Evan Cheng
612b79edc9
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:40:52 +00:00
Evan Cheng
130966411f
More refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 06:41:12 +00:00
Evan Cheng
37f25d989a
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:39:26 +00:00