Commit Graph

81210 Commits

Author SHA1 Message Date
Peter Collingbourne
ce2b45bd7d IR: Do not consider available_externally linkage to be linker-weak.
From the linker's perspective, an available_externally global is equivalent
to an external declaration (per isDeclarationForLinker()), so it is incorrect
to consider it to be a weak definition.

Also clean up some logic in the dead argument elimination pass and clarify
its comments to better explain how its behavior depends on linkage,
introduce GlobalValue::isStrongDefinitionForLinker() and start using
it throughout the optimizers and backend.

Differential Revision: http://reviews.llvm.org/D10941

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241413 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 20:52:35 +00:00
Sanjay Patel
3b19ca3a2e use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241412 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 20:15:21 +00:00
Benjamin Kramer
54b3b4c15e [TargetLowering] StringRefize asm constraint getters.
There is some functional change here because it changes target code from
atoi(3) to StringRef::getAsInteger which has error checking. For valid
constraints there should be no difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241411 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 19:29:18 +00:00
Asaf Badouh
5047893c31 [x86][AVX512] add Multiply High Op
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241406 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 12:23:20 +00:00
Michael Kuperstein
bb803fd76e [X86] Fix incorrect/inefficient pushw encodings for x86-64 targets
Correctly support assembling "pushw $imm8" on x86-64 targets. 
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)

This fixes PR23996

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 10:25:41 +00:00
Nemanja Ivanovic
8be316bf23 Add missing builtins to the PPC back end for ABI compliance (vol. 2)
This patch corresponds to review:
http://reviews.llvm.org/D10874

Back end portion of the second round of additions to altivec.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241398 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 06:03:51 +00:00
Sanjay Patel
8720b26a58 use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241395 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 19:38:52 +00:00
Simon Pilgrim
4606f6d8da [X86][SSE] Improved i8/i16 to f64 uint2fp vector conversions
Followup to D10433 and D10589 that fixes i8/i16 uint2fp vector conversions by zero extending to i32 and using the sint2fp path (unless the target does actually support uint2fp).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241394 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 15:33:34 +00:00
Sanjay Patel
2244d521c0 use valid bits to avoid unnecessary machine trace metric recomputations
Although this does cut the number of traces recomputed by ~10% for the
test case mentioned in http://reviews.llvm.org/D10460, it doesn't
make a dent in the overall performance. That example needs to be more
selective when invalidating traces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241393 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 15:00:28 +00:00
Yaron Keren
57dee47d17 Fix spelling, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241392 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 05:48:52 +00:00
Peter Collingbourne
dfe478600b LTO: expose LTO_SYMBOL_ALIAS, which indicates that the symbol is an alias.
This is needed for COFF linkers to distinguish between weak external aliases
and regular symbols with LLVM weak linkage, which are represented as strong
symbols in COFF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241389 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 03:42:35 +00:00
Rui Ueyama
392450ed6f Object/COFF: Do not rely on VirtualSize being 0 in object files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241387 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 03:25:51 +00:00
Lang Hames
b21c7647d8 [RuntimeDyld] Skip relocations for external symbols with 64-bit address ~0ULL.
Requested by Eugene Rozenfeld of the LLILC team, this feature allows JIT
clients to skip relocations for selected external symbols by returning ~0ULL
from their symbol resolver. If this value is returned for a given symbol,
RuntimeDyld will skip all relocations for that symbol. The client will be
responsible for applying the skipped relocations manually before the code
is executed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241383 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 01:35:26 +00:00
Craig Topper
9a9ee6f550 [X86] Add proper 64-bit mode checks to jrcxz and jcxz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241381 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-04 00:01:07 +00:00
Matt Arsenault
11528555b1 AMDGPU: Fix indentation of switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241380 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 23:33:38 +00:00
Simon Atanasyan
afc0340d96 [ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools
SHT_NOBITS sections do not have content in an object file. Now the yaml2obj
tool does not accept `Content` field for such sections, and the obj2yaml
tool does not attempt to read the section content from a file.

Restore r241350 and r241352.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241377 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 23:00:54 +00:00
Rafael Espindola
b811509613 Use a continue to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241375 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 22:02:28 +00:00
Rafael Espindola
5b685b0cf8 Use a continue to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241374 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 21:57:41 +00:00
Rafael Espindola
75ad04a92a Context is allocated just a few lines above. Don't check if it is null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241373 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 21:54:41 +00:00
Rafael Espindola
643de689aa Fix build with -DLLVM_USE_INTEL_JITEVENTS=ON -DLLVM_USE_OPROFILE=ON.
Is anyone using those?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 21:47:00 +00:00
Filipe Cabecinhas
177fabfc30 Remove always-true comparison, NFC.
Summary:
Looking at r241279, I noticed that UpgradedIntrinsics only gets written
to in the following code:

    if (UpgradeIntrinsicFunction(&F, NewFn))
      UpgradedIntrinsics[&F] = NewFn;

Looking through UpgradeIntrinsicFunction, we always return false OR
NewFn will be set to a different function from our source.

This patch pulls the F != NewFn into UpgradeIntrinsicFunction as an
assert, and removes the check from callers of UpgradeIntrinsicFunction.

Reviewers: rafael, chandlerc

Subscribers: llvm-commits-list

Differential Revision: http://reviews.llvm.org/D10915

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241369 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 20:12:01 +00:00
Rafael Espindola
5954faae4d Return ErrorOr from getSymbolAddress.
It can fail trying to get the section on ELF and COFF. This makes sure the
error is handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 18:19:00 +00:00
Rafael Espindola
115b2eb8bf Replace a few more MachO only uses of getSymbolAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241365 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 18:02:36 +00:00
Rafael Espindola
e235dc4936 Use getValue instead of getAddress in a few MachO only cases.
In MachO the value of the symbol is always the address, so we can use the
simpler function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241364 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 17:44:18 +00:00
Rafael Espindola
a89ad42b36 This reverts commit r241350 and r241352.
r241350 broke lld tests.
r241352 depends on r241350.

Original messages:
"[ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools"
"[ELFYAML] Make the Size field for .bss section optional"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241354 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 14:54:02 +00:00
Simon Atanasyan
5f78433f81 [ELFYAML] Make the Size field for .bss section optional
It's a common case to have a zero-size .bss section in an object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241352 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 14:19:06 +00:00
Simon Atanasyan
c97046c6e6 [ELFYAML] Fix handling SHT_NOBITS sections by obj2yaml/yaml2obj tools
SHT_NOBITS sections do not have content in an object file. Now yaml2obj
tool does not accept `Content` field for such sections, and obj2yaml
tool does not attempt to read the section content from a file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241350 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 14:07:06 +00:00
Rafael Espindola
21afba1004 Avoid a use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241345 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 12:20:34 +00:00
Simon Pilgrim
339c530319 [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt2)
Add support for v2i8/v2i16 to v2f64 by using a sign extension to v2i32 before conversion to v2f64.

Differential Revision: http://reviews.llvm.org/D10589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 08:01:36 +00:00
Yaron Keren
a450348ecc Initialize booleans CallsUnwindInit and CallsEHReturn with false instead of 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241324 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 07:56:24 +00:00
Simon Pilgrim
e3c6222c76 [X86][SSE] Sign extension for target vector sizes less than 128 bits (pt1)
This patch adds support for sign extension for sub 128-bit vectors, such as to v2i32. It concatenates with UNDEF subvectors up to 128-bits, performs the sign extension (i.e. as v4i32) and then extracts the target subvector.

Patch 1/2 of D10589 - the second patch covers the conversion of v2i8/v2i16 to v2f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241323 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 07:51:01 +00:00
Nadav Rotem
6890be345e Fix an overly aggressive assertion in getCopyFromPartsVector.
The assertion in getCopyFromPartsVector assumed that the vector 'part' must
match the type of argument (arguments are potentially split into multiple
parts). However, in some cases the targets return a 'part' of the right size
but with a different type. We already handle this case correctly later on
and generate a bitcast. This commit just makes sure that we are actually
checking the property that we care about.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241312 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 23:23:52 +00:00
Adrian Prantl
c3d9cd3f73 DIBuilder: Now that DICompileUnit is distinct, stop using temporary nodes
for the arrays.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241308 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 22:32:52 +00:00
Akira Hatanaka
516286ff69 Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName.
This commit changes normal isel and fast isel to read the user-defined trap
function name from function attribute "trap-func-name" attached to llvm.trap or
llvm.debugtrap instead of from TargetOptions::TrapFuncName. This is needed to
use clang's command line option "-ftrap-function" for LTO and enable changing
the trap function name on a per-call-site basis.

Out-of-tree projects currently using TargetOptions::TrapFuncName to specify the
trap function name should attach attribute "trap-func-name" to the call sites
of llvm.trap and llvm.debugtrap instead.

rdar://problem/21225723

Differential Revision: http://reviews.llvm.org/D10832


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241305 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 22:13:27 +00:00
Akira Hatanaka
7ef8957773 Add functions for adding and testing string attributes to CallInst. NFC.
This change is needed later when I make changes to attach string function
attributes to llvm.trap and llvm.debugtrap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241304 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 22:08:48 +00:00
Dan Gohman
44bc052f4d [WebAssembly] Set the HasFloatingPointExceptions flag for WebAssembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241302 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 21:36:25 +00:00
Rafael Espindola
c223f39fa7 Try to fix the build of IntelJITEventListener.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 21:24:12 +00:00
Rafael Espindola
8a80641a85 Return ErrorOr from SymbolRef::getName.
This function can really fail since the string table offset can be out of
bounds.

Using ErrorOr makes sure the error is checked.

Hopefully a lot of the boilerplate code in tools/* can go away once we have
a diagnostic manager in Object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241297 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 20:55:21 +00:00
Bill Schmidt
397fac95d5 [PPC64LE] Remove implicit-subreg restriction from VSX swap removal
In r241285, I removed the SUBREG_TO_REG restriction from VSX swap
removal, determining that this was overly conservative.  We have
another form of the same restriction in that we check for the presence
of implicit subregs in vector operations.  As with SUBREG_TO_REG for
partial register conversions, an implicit subreg is safe in and of
itself, provided no other operation makes a lane-sensitive assumption
about the result.  This patch removes that restriction, by removing
the HasImplicitSubreg flag and all code that relies on it.

I've added a test case that fails to optimize before this patch is
applied, and optimizes properly with the patch.  Test based on a
report from Anton Blanchard.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241290 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 19:01:22 +00:00
Bill Schmidt
a5a5a62fff [PPC64LE] Teach swap optimization about the doubleword splat idiom
With a previous patch, the VSX swap optimization is able to recognize
the doubleword load-splat idiom that can be implemented using lxvdsx.
However, that does not cover a doubleword splat where the source is a
register.  We can implement this using xxspltd (a special form of
xxpermdi).  This patch teaches the swap optimization pass about this
idiom.

As a prerequisite, it also permits swap optimization to succeed for
all forms of SUBREG_TO_REG.  Previously we were conservative and only
allowed SUBREG_TO_REG when it copied a full register.  However, on
reflection any form of SUBREG_TO_REG is safe in and of itself, so long
as an unsafe operation is not performed on its result.  In particular,
a widening SUBREG_TO_REG often occurs as an input to a doubleword
splat idiom, particularly in auto-vectorized code.

The doubleword splat idiom is an XXPERMDI operation where both source
registers are identical, and the selection mask is either 0 (splat the
first element) or 3 (splat the second element).  To determine whether
the registers are identical, we use the existing mechanism for looking
through "copy-like" operations.  That mechanism has a side effect of
marking the XXPERMDI operation as using a physical register, which
would invalidate its presence in a swap-optimized region.  This is
correct for the form of XXPERMDI that performs a swap and hence would
be removed, but is not what we want for a doubleword-splat variety of
XXPERMDI.  Therefore we reset the physical-register flag on the
XXPERMDI when it represents a splat.

A simple test case is added to verify that we generate the splat and
that we also remove the xxswapd instructions that would otherwise be
associated with the load and store of another operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241285 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 17:03:06 +00:00
Rafael Espindola
9561506e34 Convert a member variable to a local one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241284 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 16:59:57 +00:00
Rafael Espindola
9afb3a2589 Fix for PR23310: llvm-dis crashes when trying to upgrade an intrinsic.
When trying to upgrade @llvm.x86.sse2.psrl.dq while parsing a module,
BitcodeReader adds the function to its worklist twice, resulting in a
crash when accessing it the second time.

This patch replaces the worklist vector by a map.

Patch by Philip Pfaffe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241281 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 16:22:40 +00:00
Rafael Espindola
002ff89e22 Rangify some loops.
Patch by Philip Pfaffe!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241279 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 15:55:09 +00:00
Leny Kholodov
479dc2c0fe [Support] Lazy load of dbghlp.dll on Windows
This patch changes linkage with dbghlp.dll for clang from static (at load time)
to on demand (at the first use of required functions). Clang uses dbghlp.dll
only in minor use-cases. First of all in case of crash and in case of plugin load.
The dbghlp.dll library can be absent on system. In this case clang will fail
to load. With lazy load of dbghlp.dll clang can work even if dbghlp.dll
is not available.

Differential Revision: http://reviews.llvm.org/D10737



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241271 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 14:34:57 +00:00
Yaron Keren
8bbc5bbd34 Remove whitespace from start of line, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241268 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 14:25:09 +00:00
Yaron Keren
016970f468 Delete whitespace at start of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241265 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 14:17:12 +00:00
Pawel Bylica
074d71dea6 Reapply r240291: Fix shl folding in DAG combiner.
The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared.

It has been reverted previously because of some problems with comparing APInt with raw uint64_t. That has been fixed/changed with r241204.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241254 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 11:44:54 +00:00
Charlie Turner
8992bae990 [GraphWriter] Don't wait on xdg-open when not on Apple.
By default, the GraphWriter code assumes that the generic file open
program (`open` on Apple, `xdg-open` on other systems) can wait on the
forked proces to complete. When the fork ends, the code would delete
the temporary dot files created, and return.

On GNU/Linux, the xdg-open program does not have a "wait for your fork
to complete before dying" option. So the behaviour was that xdg-open
would launch a process, quickly die itself, and then the GraphWriter
code would think its OK to quickly delete all the temporary files.
Once the temporary files were deleted, the dot viewers would get very
upset, and often give you weird errors.

This change only waits on the generic open program on Apple platforms.
Elsewhere, we don't wait on the process, and hence we don't try and
clean up the temporary files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241250 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 09:32:07 +00:00
Sanjoy Das
d0872b393c [NFC] Make the Statepoint class more like CallSite
Summary: Rename some methods to make Statepoint look more like CallSite.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241235 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 02:53:45 +00:00
Eric Christopher
320404f134 Implement TargetTransformInfo::hasCompatibleFunctionAttributes for X86.
This checks subtarget feature compatibility for inlining by verifying
that the callee is a strict subset of the caller's features. This includes
the cpu as part of the subtarget we can get via the incoming functions as
the backend takes CPUs as feature sets.

This allows us to inline things like:

int foo() { return baz(); }

int __attribute__((target("sse4.2"))) bar() {
  return foo();
}

so that generic code can be inlined into specialized functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241221 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 01:11:50 +00:00
Eric Christopher
5d5b914c59 Add a routine to TargetTransformInfo that will allow targets to look
at the attributes on a function to determine whether or not to allow
inlining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-02 01:11:47 +00:00
JF Bastien
1ff585db47 WebAssembly: start instructions
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 23:41:25 +00:00
Quentin Colombet
a1a323c637 [TwoAddressInstructionPass] Try 3 Addr Conversion After Commuting.
TwoAddressInstructionPass stops after a successful commuting but 3 Addr
conversion might be good for some cases.
 
Consider:

int foo(int a, int b) {
  return a + b;
}

Before this commit, we emit:

addl	%esi, %edi
movl	%edi, %eax
ret

After this commit, we try 3 Addr conversion:

leal	(%rsi,%rdi), %eax
ret

Patch by Volkan Keles <vkeles@apple.com>!

Differential Revision: http://reviews.llvm.org/D10851


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 23:12:13 +00:00
Alexey Samsonov
739ded16a5 [LoopVectorize] Use ReplaceInstWithInst() helper where appropriate.
This is mostly an NFC, which increases code readability (instead of
saving old terminator, generating new one in front of old, and deleting
old, we just call a function). However, it would additionaly copy
the debug location from old instruction to replacement, which
would help PR23837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241197 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 22:18:30 +00:00
Pete Cooper
f89e1bdc1a Pack MCSymbol::Flags in to the bitfield with other members. NFC.
All file formats only needed 16-bits right now which is enough to fit
in to the padding with other fields.

This reduces the size of MCSymbol to 24-bytes on a 64-bit system.  The
layout is now

   0 | class llvm::MCSymbol
   0 |   class llvm::PointerIntPair SectionOrFragmentAndHasName
   0 |     intptr_t Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

   8 |   unsigned int IsTemporary
   8 |   unsigned int IsRedefinable
   8 |   unsigned int IsUsed
   8 |   _Bool IsRegistered
   8 |   unsigned int IsExternal
   8 |   unsigned int IsPrivateExtern
   8 |   unsigned int Kind
   9 |   unsigned int IsUsedInReloc
   9 |   unsigned int SymbolContents
   9 |   unsigned int CommonAlignLog2
  10 |   uint32_t Flags
  12 |   uint32_t Index
  16 |   union
  16 |     uint64_t Offset
  16 |     uint64_t CommonSize
  16 |     const class llvm::MCExpr * Value
     |   [sizeof=8, dsize=8, align=8
     |    nvsize=8, nvalign=8]

     | [sizeof=24, dsize=24, align=8
     |  nvsize=24, nvalign=8]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241196 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:57:51 +00:00
Dan Gohman
1efcdba0e2 [WebAssembly] Define separate Target instances for 32-bit and 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:42:34 +00:00
Jingyue Wu
e08f05f3a5 [NVPTX] expand extload/truncstore for vectors of floats
Summary:
According to PTX ISA:

For convenience, ld, st, and cvt instructions permit source and destination data operands to be wider than the instruction-type size, so that narrow values may be loaded, stored, and converted using regular-width registers. For example, 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded, stored, or converted to other types and sizes. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types; floating-point instruction types still require that the operand type-size matches exactly, unless the operand is of bit-size type.

So, the ISA does not support load with extending/store with truncatation for floating numbers. This is reflected in setting the loadext/truncstore actions to expand in the code for floating numbers, but vectors of floating numbers are not taken care of.

As a result, loading a vector of floats followed by a fp_extend may be combined by DAGCombiner to a extload, and the extload may be lowered to NVPTXISD::LoadV2 with extending information. However, NVPTXISD::LoadV2 does not perform extending, and no extending instructions are inserted. Finally, PTX instructions with mismatched types are generated, like
ld.v2.f32 {%fd3, %fd4}, [%rd2]

This patch adds the correct actions for vectors of floats, so DAGCombiner would not create loads with extending, and correct code is generated.

Patched by Gang Hu. 

Test Plan: Test case attached.

Reviewers: jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D10876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241191 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:32:42 +00:00
Pete Cooper
f77ca9f85f Encode MCSymbol alignment as log2(align).
Given that alignments are always powers of 2, just encode it this way.

This matches how we encode alignment on IR GlobalValue's for example.

This compresses the CommonAlign member down to 5 bits which allows it
to pack better with the surrounding fields.

Reviewed by Duncan Exon Smith.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241189 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:07:03 +00:00
Reid Kleckner
8a1df9b25f [WinEH] Use llvm.x86.seh.recoverfp in WinEHPrepare
Don't pattern match for frontend outlined finally calls on non-x64
platforms. The 32-bit runtime uses a different funclet prototype.  Now,
the frontend is pre-outlining the finally bodies so that it ends up
doing most of the heavy lifting for variable capturing. We're just
outlining the callsite, and adapting the frameaddress(0) call to line up
the frame pointer recovery.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241186 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 20:59:25 +00:00
Jingyue Wu
8f2981cb40 [NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
Summary:
Offset of frame index is calculated by NVPTXPrologEpilogPass. Before
that the correct offset of stack objects cannot be obtained, which
leads to wrong offset if there are more than 2 frame objects. This patch
move NVPTXPeephole after NVPTXPrologEpilogPass. Because the frame index
is already replaced by %VRFrame in NVPTXPrologEpilogPass, we check
VRFrame register instead, and try to remove the VRFrame if there
is no usage after NVPTXPeephole pass.

Patched by Xuetian Weng. 

Test Plan:
Strengthened test/CodeGen/NVPTX/local-stack-frame.ll to check the
offset calculation based on SP and SPL.

Reviewers: jholewinski, jingyue

Reviewed By: jingyue

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10853

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241185 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 20:08:06 +00:00
Bill Schmidt
9215b9ab25 [PPC64LE] Enable missing lxvdsx optimization, and related swap optimization
When adding little-endian vector support for PowerPC last year, I
inadvertently disabled an optimization that recognizes a load-splat
idiom and generates the lxvdsx instruction.  This patch moves the
offending logic so lxvdsx is once again generated.

This pattern is frequently generated by the vectorizer for scalar
loads of an effective constant.  Previously the lxvdsx instruction was
wrongly listed as lane-sensitive for the VSX swap optimization (since
both doublewords are identical, swaps are safe).  This patch fixes
this as well, so that vectorized code using lxvdsx can now have swaps
removed from the computation.

There is an existing test (@test50) in test/CodeGen/PowerPC/vsx.ll
that checks for the missing optimization.  However, vsx.ll was only
being tested for POWER7 with big-endian code generation.  I've added
a little-endian RUN statement and expected LE code generation for all
the tests in vsx.ll to give us a bit better VSX coverage, including
what's needed for this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241183 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 19:40:07 +00:00
Sanjay Patel
7472456fe9 add a cl::opt override for TargetLoweringBase's JumpIsExpensive
This patch is not intended to change existing codegen behavior for any target. 
It just exposes the JumpIsExpensive setting on the command-line to allow for
easier testing and emergency overrides.

Also, change the existing regression test to use FileCheck, explicitly specify
the jump-is-expensive option, and use more precise checks.

Differential Revision: http://reviews.llvm.org/D10846



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2015-07-01 18:10:20 +00:00
David Blaikie
b99e0eb947 Revert "[DWARF] Fix debug info generation for function static variables, typedefs, and records"
Caused PR24008

This reverts commit 37cb5f1c2d.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241176 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 18:07:16 +00:00
Sanjay Patel
89ec7f0069 fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241175 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 17:58:53 +00:00
Sanjay Patel
b3d73f5064 fix typos in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 17:55:07 +00:00
Matthias Braun
08f65f9d69 LivePhysRegs: Add support to add pristine registers when populating with live-in/live-out registers.
Differential Revision: http://reviews.llvm.org/D10139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241172 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 17:17:17 +00:00
Reid Kleckner
1804878f0c [SEH] Don't assert if the parent function lacks a personality
The EH code might have been deleted as unreachable and the personality
pruned while the filter is still present.  Currently I'm hitting this at
-O0 due to the clang bug PR24009.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241170 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 16:45:47 +00:00
Benjamin Kramer
a2b83fd687 [AsmPrinter] Hide implementation details
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241169 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 16:18:16 +00:00
Arnaud A. de Grandmaison
bdaa375556 [AArch64] Implement add/adds/sub/subs/cmp/cmn with negative immediate aliases
This patch teaches the AsmParser to accept add/adds/sub/subs/cmp/cmn
with a negative immediate operand and convert them as shown:

  add  Rd, Rn, -imm -> sub  Rd, Rn, imm
  sub  Rd, Rn, -imm -> add  Rd, Rn, imm
  adds Rd, Rn, -imm -> subs Rd, Rn, imm
  subs Rd, Rn, -imm -> adds Rd, Rn, imm
  cmp  Rn, -imm     -> cmn  Rn, imm
  cmn  Rn, -imm     -> cmp  Rn, imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers (gas). They are documented in the "ARMv8 Instruction Set
Overview", in the "Arithmetic (immediate)" section. This makes llvm-mc
a programmer-friendly assembler !

This also fixes PR20978: "Assembly handling of adding negative numbers
not as smart as gas".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 15:05:58 +00:00
Benjamin Kramer
3690da1dfa [SDAG] Give InstrEmitter hidden visibility
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 14:55:10 +00:00
Benjamin Kramer
b453775cc2 [CodeGen] Reduce visibility of implementation details
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 14:47:39 +00:00
James Y Knight
bcc1a5c01a [Sparc] Rearrange SparcInstrInfo, no change.
Move some instructions into order of sections in the spec, as the rest
already were.

Differential Revision: http://reviews.llvm.org/D9102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 14:38:07 +00:00
Igor Breger
2ae30810d8 AVX-512: Implemented missing encoding for FMA scalar instructions
Added tests for encoding

Differential Revision: http://reviews.llvm.org/D10865

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241159 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 13:24:28 +00:00
Rafael Espindola
df3edb6d36 Return ErrorOr from getSection.
This also improves the logic of what is an error:

* getSection(uint_32): only return an error if the index is out of bounds. The
  index 0 corresponds to a perfectly valid entry.
* getSection(Elf_Sym): Returns null for symbols that normally don't have
  sections and error for out of bound indexes.

In many places this just moves the report_fatal_error up the stack, but those
can then be fixed in smaller patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241156 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 12:56:27 +00:00
Michael Kuperstein
37cb5f1c2d [DWARF] Fix debug info generation for function static variables, typedefs, and records
Function static variables, typedefs and records (class, struct or union) declared inside
a lexical scope were associated with the function as their parent scope, rather than the
lexical scope they are defined or declared in.

This fixes PR19238

Patch by: amjad.aboud@intel.com
Differential Revision: http://reviews.llvm.org/D9758

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241153 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 12:33:11 +00:00
Michael Kuperstein
5020a9198d [X86] Avoid over-relaxation of 8-bit immediates in integer arithmetic instructions.
Only consider an instruction a candidate for relaxation if the last operand of the 
instruction is an expression. We previously checked whether any operand is an expression,
which is useless, since for all instructions concerned, the only operand that may be
affected by relaxation is the last one.
In addition, this removes the check for having RIP as an argument, since it was 
plain wrong - even when one of the arguments is RIP, relaxation may still be needed.

This fixes PR9807.

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 10:54:42 +00:00
Zoran Jovanovic
627c5342b2 [mips][microMIPS] Implement SLL and NOP instructions
http://reviews.llvm.org/D10474


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241150 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 09:54:51 +00:00
Gabor Ballabas
9f9bf86ed5 Fix PR23872: Integrated assembler error message when using .type directive with @ in AArch32 assembly.
The AArch32 assembler parses the '@' as a comment symbol, so the error message shouldn't suggest
that '@<type>' is a valid replacement when assembling for AArch32 target.

Differential Revision: http://reviews.llvm.org/D10651 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241149 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 08:58:49 +00:00
David Majnemer
787b9b4e95 [LoopUnroll] Use undef for phis with no value live
We would create a phi node with a zero initialized operand instead of
undef in the case where no value was originally available.  This was
problematic for x86_mmx which has no null value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241143 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 05:38:07 +00:00
David Majnemer
284c49c36f [SCCP] Turn loads of null into undef instead of zero initialized values
Surprisingly, this is a correctness issue: the mmx type exists for
calling convention purposes, LLVM doesn't have a zero representation for
them.

This partially fixes PR23999.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241142 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 05:37:57 +00:00
Jingyue Wu
4015c5e2e4 [NaryReassociate] enhances nsw by leveraging @llvm.assume
Summary:
nsw are flaky and can often be removed by optimizations. This patch enhances
nsw by leveraging @llvm.assume in the IR. Specifically, NaryReassociate now
understands that

    assume(a + b >= 0) && assume(a >= 0) ==> a +nsw b

As a result, it can split more sext(a + b) into sext(a) + sext(b) for CSE.

Test Plan: nary-gep.ll

Reviewers: broune, meheff

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241139 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 03:38:49 +00:00
Alexey Samsonov
327cfdf4fe [SanitizerCoverage] Don't add instrumentation to unreachable blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241127 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 23:11:45 +00:00
Reid Kleckner
34c6bb0ef0 [SEH] Add new intrinsics for recovering and restoring parent frames
The incoming EBP value established by the runtime is actually a pointer
to the end of the EH registration object, and not the true parent
function frame pointer. Clang doesn't need llvm.x86.seh.exceptioninfo
anymore because we know that the exception info pointer is at a fixed
offset from this incoming EBP.

The llvm.x86.seh.recoverfp intrinsic takes an EBP value provided by the
EH runtime and returns a pointer that is usable with llvm.framerecover.

The llvm.x86.seh.restoreframe intrinsic is inserted by the 32-bit
specific preparation pass in blocks targetted by the EH runtime. It
re-establishes any physical registers used by the parent function to
address the stack, such as the frame, base, and stack pointers.

Neither of these intrinsics correctly handle stack realignment prologues
yet, but it's possible to add that later.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D10848

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241125 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 22:46:59 +00:00
David Majnemer
5ca5b0d9f4 [Cloning] Teach CloneModule about personality functions
CloneModule didn't take into account that it needed to remap the value
using values in the module.

This fixes PR23992.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241122 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 22:14:01 +00:00
Jingyue Wu
10a3a33df0 [NVPTX] cleanups and refacotring in NVPTXFrameLowering.cpp
Summary: NFC

Test Plan: no regression

Reviewers: wengxt

Reviewed By: wengxt

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241118 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 21:28:31 +00:00
Sanjoy Das
e1e95c11b8 [FaultMaps] Let the frontend pre-select implicit null check candidates.
Summary:
This change introduces a !make.implicit metadata that allows the
frontend to pre-select the set of explicit null checks that will be
considered for transformation into implicit null checks.

The reason for not using profiling data instead of !make.implicit is
explained in the change to `FaultMaps.rst`.

Reviewers: atrick, reames, pgavlin, JosephTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10824

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 21:22:32 +00:00
Pete Cooper
8cdbab9dd6 Pack MCSymbol::HasName in to a spare bit in the section/fragment union.
This is part of an effort to pack the average MCSymbol down to 24 bytes.

The HasName bit was pushing the size of the bitfield over to another word,
so this change uses a PointerIntPair to fit in it to unused bits of a
PointerUnion.

Reviewed by Rafael Espíndola

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 20:54:21 +00:00
Rafael Espindola
28a83187a2 Use ErrorOr in getRelocationAdress.
We can probably do better in this method, but this is an improvement and
enables further ErrorOr cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241114 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 20:32:26 +00:00
Rafael Espindola
d231306ba8 Implement containsSymbol with other lower level methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241112 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 20:18:49 +00:00
Nemanja Ivanovic
ce772898d6 Modified a comment about the reason for the patch (removed commented code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241110 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 20:01:16 +00:00
Nemanja Ivanovic
482f87058a Fixes a bug with __builtin_vsx_lxvdw4x on Little Endian systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241108 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 19:45:45 +00:00
Peter Collingbourne
fd8c98591d COFF: Do not assign linker-weak symbols to selectany comdat sections.
It is mandatory to specify a comdat in order to receive comdat semantics
for a symbol. We were previously getting this wrong in -function-sections
mode; linker-weak symbols were being emitted in a selectany comdat. This
change causes such symbols to use a noduplicates comdat instead, fixing
the inconsistency.

Also correct an inaccuracy in the docs.

Differential Revision: http://reviews.llvm.org/D10828

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241103 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 19:10:31 +00:00
Jingyue Wu
75cacfb490 [NVPTX] Fix issue introduced in D10321
Summary:
Really check if %SP is not used in other places, instead of checking only exact
one non-dbg use.

Patched by Xuetian Weng. 

Test Plan:
@foo4 in test/CodeGen/NVPTX/local-stack-frame.ll, create a case that
SP will appear twice.

Reviewers: jholewinski, jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, sfantao, jholewinski

Differential Revision: http://reviews.llvm.org/D10844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241099 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:59:19 +00:00
Adrian Prantl
c408bc8e39 Fix a fixme and make DICompileUnit a distinct node. Tested via clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241097 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:32:18 +00:00
Alex Lorenz
eceef384d6 Fix compilation failure introduced in r241093.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241096 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:32:02 +00:00
Alex Lorenz
73d2cc5b8e MIR Serialization: Serialize MBB successors.
This commit implements serialization of the machine basic block successors. It
uses a YAML flow sequence that contains strings that have the MBB references.
The MBB references in those strings use the same syntax as the MBB machine
operands in the machine instruction strings.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10699


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241093 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:16:42 +00:00
Alex Lorenz
ba4660cb83 MIR Printer: extract the code that prints MBB references into a new method. NFC.
This commit enables the MIR printer to reuse the code that prints MBB
references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241087 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 18:00:16 +00:00
Alex Lorenz
403c3312c3 MIR Parser: refactor error reporting for machine instruction parser errors. NFC.
This commit extracts the code that reports an error that's produced by the
machine instruction parser into a new method that can be reused in other places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241086 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 17:55:00 +00:00
Alex Lorenz
939f023bf9 MIR Parser: make the machine instruction parsing interface more consistent. NFC.
This commit refactors the interface for machine instruction parser. It adopts
the pattern of returning a bool and passing in the result in the first argument
that is used by the other parsing methods for the the method 'parse' and the
function 'parseMachineInstr'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241085 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 17:47:50 +00:00
Samuel Antao
8f1e30d67c Force relocation mode to be default, regardless of what is passed to the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241081 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 17:18:00 +00:00
Alex Lorenz
1991c597a4 MIR Parser: adopt the 'maybeLex...' pattern. NFC.
This commit refactors the machine instruction lexer so that the lexing
functions use the 'maybeLex...' pattern, where they determine if they
can lex the current token by themselves.

Reviewers: Sean Silva

Differential Revision: http://reviews.llvm.org/D10817


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241078 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 16:51:29 +00:00
Sanjay Patel
5601e30a77 use range-based for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241076 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 16:30:22 +00:00
Michael Kuperstein
f8b3b92eb8 [X86] Fix a bug in WIN_FTOL_32/64 handling.
Duplicating an FP register "as itself" is a bad idea, since it violates the
invariant that every FP register is mapped to at most one FPU stack slot.
Use the scratch FP register instead.

This fixes PR23957.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241069 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 14:38:57 +00:00
Toma Tabacu
e143a3abc2 [mips] [IAS] Add support for the .module softfloat/hardfloat directives.
These directives are used to set the default value of the SoftFloat feature.
They have the same effect as setting -m{soft, hard}-float from the command line.

Differential Revision: http://reviews.llvm.org/D9073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241066 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 13:46:03 +00:00
Toma Tabacu
dcec5265ae [mips] [IAS] Make .module directives change AssemblerOptions->front().
Differential Revision: http://reviews.llvm.org/D10643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241062 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 12:41:33 +00:00
Ranjeet Singh
b0f7871d4e Reverting r241058 because it's causing buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241061 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 12:32:53 +00:00
Ranjeet Singh
a5106ca54d There are a few places where subtarget features are still
represented by uint64_t, this patch replaces these
usages with the FeatureBitset (std::bitset) type.

Differential Revision: http://reviews.llvm.org/D10542


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 11:30:42 +00:00
Toma Tabacu
5dee8da754 [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives.
Differential Revision: http://reviews.llvm.org/D10657

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241052 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 09:36:50 +00:00
Michael Kuperstein
501cad951b [X86] Add FXSR intrinsics
Add intrinsics for the FXSR instructions (FXSAVE/FXSAVE64/FXRSTOR/FXRSTOR64)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241049 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 08:49:35 +00:00
Rafael Espindola
f8a35ff558 Don't return error_code from a function that doesn't fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241042 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 04:08:37 +00:00
Dan Gohman
06bc362502 Drop the OS from the WebAssembly target triple for now.
This unbreaks TripleTest.Normalization. We'll have to come up with a new
plan for the OS component of the target triple for WebAssembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241041 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 03:52:25 +00:00
Rafael Espindola
09912eb9ec Move function to the only file that uses it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241040 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 03:41:26 +00:00
Rafael Espindola
9f2f3bba2b Don't return error_code from a function that doesn't fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241039 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 03:33:18 +00:00
Adrian Prantl
85cd16c88e Debug info: Add dwarf backend support for DIModule.
rdar://problem/20965932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241034 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 02:13:04 +00:00
Rafael Espindola
7ede9649c1 Don't return error_code from a function that doesn't fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241033 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 01:53:01 +00:00
Rafael Espindola
de4d844704 Cleanup getRelocationAddend.
Realistically, this will be returning ErrorOr for some time as refactoring the
user code to check once per section will take some time.

Given that, use it for checking if a relocation has addend or not.

While at it, add ELFRelocationRef to simplify the users.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241028 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 00:33:59 +00:00
Matthias Braun
1a5b04c725 RegisterCoalescer: Cleanup empty subranges after shrinkToUses()
A call to removeEmptySubranges() is necessary after every operation that
potentially removes all segments from a subregister range; this case in
the register coalescer was missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 00:33:44 +00:00
Rui Ueyama
13b58ec74a Object/COFF: Define coff_symbol_generic.
If you only need Name and Value fields in the COFF symbol,
you don't need to distinguish 32 bit and 64 bit COFF symbols.
These fields start at the same offsets and have the same size.

This data strucutre is one pointer smaller than COFFSymbolRef
thus slightly efficient. I'll use this class in LLD as we create
millions of LLD symbol objects that currently contain COFFSymbolRef.
Shaving off 8 byte (or 4 byte on 32 bit) from that class actually
matters becasue of the number of objects we create in LLD.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241024 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-30 00:03:56 +00:00
Dan Gohman
a74341308f [WebAssembly] Initial WebAssembly backend
This WebAssembly backend is just a skeleton at this time and is not yet
functional.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 23:51:55 +00:00
Rafael Espindola
ff67629985 Don't return error_code from function that never fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241021 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 23:29:12 +00:00
Adrian Prantl
717764717b Add a DIModule metadata node to the IR.
It is meant to be used to record modules @imported by the current
compile unit, so a debugger an import the same modules to replicate this
environment before dropping into the expression evaluator.

DIModule is a sibling to DINamespace and behaves quite similarly.
In addition to the name of the module it also records the module
configuration details that are necessary to uniquely identify the module.
This includes the configuration macros (e.g., -DNDEBUG), the include path
where the module.map file is to be found, and the isysroot.

The idea is that the backend will turn this into a DW_TAG_module.

http://reviews.llvm.org/D9614
rdar://problem/20965932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241017 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 23:03:47 +00:00
Ben Langmuir
fce3cfb784 Reapply "Use gethostuuid() on Mac to identify hosts for LockFileManager"
Reapplies r241005 after fixing the build on non-Mac platforms. Original
commit message below.

The hostname can be very unstable when there are many machines on the
network competing for the same name. Using the hardware UUID makes it
less likely to have collisions or to consider files written by the
current host to be owned by a different one at a later time.

rdar://problem/21512307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241012 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 22:16:39 +00:00
Peter Collingbourne
a6367d9136 Teach LTOModule to emit linker flags for dllexported symbols, plus interface cleanup.
This change unifies how LTOModule and the backend obtain linker flags
for globals: via a new TargetLoweringObjectFile member function named
emitLinkerFlagsForGlobal. A new function LTOModule::getLinkerOpts() returns
the list of linker flags as a single concatenated string.

This change affects the C libLTO API: the function lto_module_get_*deplibs now
exposes an empty list, and lto_module_get_*linkeropts exposes a single element
which combines the contents of all observed flags. libLTO should never have
tried to parse the linker flags; it is the linker's job to do so. Because
linkers will need to be able to parse flags in regular object files, it
makes little sense for libLTO to have a redundant mechanism for doing so.

The new API is compatible with the old one. It is valid for a user to specify
multiple linker flags in a single pragma directive like this:

 #pragma comment(linker, "/defaultlib:foo /defaultlib:bar")

The previous implementation would not have exposed
either flag via lto_module_get_*deplibs (as the test in
TargetLoweringObjectFileCOFF::getDepLibFromLinkerOpt was case sensitive)
and would have exposed "/defaultlib:foo /defaultlib:bar" as a single flag via
lto_module_get_*linkeropts. This may have been a bug in the implementation,
but it does give us a chance to fix the interface.

Differential Revision: http://reviews.llvm.org/D10548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 22:04:09 +00:00
Ben Langmuir
cb936df2a9 Revert "Use gethostuuid() on Mac to identify hosts for LockFileManager"
Broke non-Mac builds.

This reverts commit r241005.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241007 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:56:03 +00:00
Ben Langmuir
d5c333b731 Use gethostuuid() on Mac to identify hosts for LockFileManager
The hostname can be very unstable when there are many machines on the
network competing for the same name. Using the hardware UUID makes it
less likely to have collisions or to consider files written by the
current host to be owned by a different one at a later time.

rdar://problem/21512307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241005 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:47:44 +00:00
Tim Northover
9cbdfb5c05 ARM: add correct kill flags when combining stm instructions
When the store sequence being combined actually stores the base register, we
should not mark it as killed until the end.

rdar://21504262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:42:16 +00:00
Matthias Braun
7839b00d43 X86: Rework inline asm integer register specification.
This is a new version of http://reviews.llvm.org/D10260.

It turned out that when you specify an integer register in inline asm on
x86 you get the register of the required type size back. That means that
X86TargetLowering::getRegForInlineAsmConstraint() has to accept any of
the integer registers and adapt its size to the given target size which
may be any 8/16/32/64 bit sized type. Surprisingly that means given a
constraint of "{ax}" and a type of MVT::F32 we need to return X86::EAX.

This change makes this face explicit, the previous code seemed like
working by accident because there it never returned an error once a
register was found. On the other hand this rewrite allows to actually
return errors for invalid situations like requesting an integer register
for an i128 type.

Related to rdar://21042280

Differential Revision: http://reviews.llvm.org/D10813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241002 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:35:51 +00:00
Alexey Samsonov
93dd711033 [LoopSimplify] Set proper debug location in loop backedge blocks.
Set debug location for terminator instruction in loop backedge block
(which is an unconditional jump to loop header). We can't copy debug
location from original backedges, as there can be several of them,
with different debug info locations. So, we follow the approach of
SplitBlockPredecessors, and copy the debug info from first non-PHI
instruction in the header (i.e. destination block).

This is yet another change for PR23837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 21:30:14 +00:00
Pawel Bylica
4c81aa2602 [DAGCombiner] Fix & simplify constant folding of sext/zext.
Summary: This patch fixes the cases of sext/zext constant folding in DAG combiner where constans do not fit 64 bits. The fix simply removes un$

Test Plan: New regression test included.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240991 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 20:28:47 +00:00
Benjamin Kramer
17d7215661 [MMI] Use TinyPtrVector instead of PointerUnion with vector.
Also simplify duplicated code a bit. No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 20:21:55 +00:00
Diego Novillo
a8db479240 Tidy comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 20:03:46 +00:00
Ben Langmuir
4081538b2e Clean up unique lock files on signal and always release the lock
Make sure to remove the unique lock file, which is what the .lock
symlink points to, if there is a signal while the lock is held. This
will release the lock, since the symlink will point to nothing (already
tested in unit tests). For good measure, also clean up the unique lock
file if there is an error or signal before the lock is acquired.

I will add a clang test.

rdar://problem/21512307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240967 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 17:08:41 +00:00
Alex Lorenz
1a4def3d97 MIR Serialization: Serialize the register mask machine operands.
This commit implements serialization of the register mask machine
operands. This commit serializes only the call preserved register
masks that are defined by a target, it doesn't serialize arbitrary
register masks.

This commit also extends the TargetRegisterInfo class and TableGen so that
the users of TRI can get the list of all the call preserved register masks and
their names.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10673


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240966 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 16:57:06 +00:00
Benjamin Kramer
59a20ece84 [SymbolSize] Skip sorting by index, just assign by index.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240961 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 16:05:00 +00:00
Benjamin Kramer
4c6f0a7bc9 Upgrade JIT listeners for changes in the libObject API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240956 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 15:18:48 +00:00
Tobias Grosser
032d56baf2 Move delinearization from SCEVAddRecExpr to ScalarEvolution
The expressions we delinearize do not necessarily have to have a SCEVAddRecExpr
at the outermost level. At this moment, the additional flexibility  is not
exploited in LLVM itself, but in Polly we will soon soonish use this
functionality. For LLVM, this change should not affect existing functionality
(which is covered by test/Analysis/Delinearization/)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240952 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 14:42:48 +00:00
Rafael Espindola
9a6c902332 Factor out the checking of string tables.
This moves the error checking for string tables to getStringTable which returns
an ErrorOr<StringRef>.

This improves error checking, makes it uniform across all string tables and
makes it possible to check them once instead of once per name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240950 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 14:39:25 +00:00
Elena Demikhovsky
546178bfe5 AVX-512: all forms of SCATTER instruction on SKX,
encoding, intrinsics and tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240936 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 12:14:24 +00:00
Javed Absar
23fd3d6afc [ARM]: Extend -mfpu options for half-precision and vfpv3xd
removing default label in switch as it results.
This is part of earlier commit http://reviews.llvm.org/D1064

Subscribers: llvm-commits



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240932 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:53:33 +00:00
Javed Absar
263dd533ee [ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.

Reviewers: rengolin, ranjeet.singh

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:32:29 +00:00
Igor Breger
048a1eb977 AVX-512: Implemented missing encoding and intrinsics for FMA instructions
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 09:10:00 +00:00
NAKAMURA Takumi
85c698064c Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240924 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-29 04:50:09 +00:00
Matt Arsenault
8be74e16ef AMDGPU/SI: Fix extra space when printing v_div_fmas_*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 18:16:14 +00:00
Jingyue Wu
62bdd72542 [SLSR] S's basis must have the same type as S
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240910 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 17:45:05 +00:00
Asaf Badouh
13ce163855 [x86][AVX512]
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240906 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 14:30:39 +00:00
Elena Demikhovsky
b23b2fbd3a AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240905 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-28 10:53:29 +00:00
Adrian Prantl
1e7ecc8e57 Revert "Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed"
This reverts commit 240890. Breaking the gdb buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240893 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 21:55:00 +00:00
Benjamin Kramer
45b5f7e457 [SDAG] Now that we have a way to communicate the exact bit on sdiv use it to simplify sdiv by a constant.
We had a hack in SDAGBuilder in place to work around this but now we
can avoid that. Call BuildExactSDIV from BuildSDIV so DAGCombiner can
perform this trick automatically.

The added check in DAGCombiner is necessary to prevent exact sdiv by pow2
from regressing as the target-specific pow2 lowering is not aware of
exact bits yet.

This is mostly covered by existing tests. One side effect is that we
get the better lowering for exact vector sdivs now too :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 20:33:26 +00:00
Adrian Prantl
6b2ae13ea3 Debug Info: One more bitfield bugfix. While yesterday's r240853 fixed
the DW_AT_bit_offset computation, the byte offset is in fact also
endian-dependent as it needs to point to the storage unit containing the
most-significant bit of the the bitfield.
I'm so looking forward to emitting the endian-agnostic DWARF 3 version
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240890 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 20:12:43 +00:00
Daniel Sanders
817cbdeae6 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 15:39:19 +00:00
David Majnemer
8a8d8b3e59 [LoopVectorize] Pointer indicies may be wider than the pointer
If we are dealing with a pointer induction variable, isInductionPHI
gives back a step value of Stride / size of pointer.  However, we might
be indexing with a legal type wider than the pointer width.
Handle this by inserting casts where appropriate instead of crashing.

This fixes PR23954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 08:38:17 +00:00
David Majnemer
1166ce2460 [PruneEH] A naked, noinline function can return via InlineAsm
The PruneEH pass tries to annotate functions as 'noreturn' if it doesn't
see a ReturnInst.  However, a naked function containing inline assembly
can contain control flow leaving the function.

This fixes PR23971.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 07:52:53 +00:00
Petr Hosek
bc245c01bf [MC] Ensure that pending labels are flushed when -mc-relax-all flag is used
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240870 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:54:17 +00:00
Petr Hosek
0aaf3287e3 [MC] Align fragments when -mc-relax-all flag is used
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 01:49:53 +00:00
Duncan P. N. Exon Smith
2a5fda92b4 IR: Expose ModuleSlotTracker in Value::print()
Allow callers of `Value::print()` and `Metadata::print()` to pass in a
`ModuleSlotTracker`.  This allows them to pay only once for calculating
module-level slots (such as Metadata).

This is related to PR23865, where there was a huge cost for
`MachineFunction::print()`.  Although I don't have a *particular* user
in mind for this new code, I have hit big slowdowns before when running
`opt -debug`, and I think this will be useful.  Going forward, if
someone hits a big slowdown with `print()` statements, they can create a
`ModuleSlotTracker` and send it through.  Similarly, adding support to
`Value::dump()` and `Metadata::dump()` should be trivial.

I added unit tests to be sure the `print()` functions actually behave
the same way with and without the slot tracker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240867 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 00:38:26 +00:00
Peter Collingbourne
e92934e078 LowerBitSets: Ignore bitset entries that do not directly refer to a global.
It is possible for a global to be substituted with another global of a
different type or a different kind (i.e. an alias) at IR link time. One
example of this scenario is when a Microsoft ABI vtable is substituted with
an alias referring to a larger vtable containing an RTTI reference.

This will cause the global to be RAUW'd with a possibly bitcasted reference
to the other global. This will of course also affect any references to the
global in bitset metadata.

The right way to handle such metadata is simply to ignore it. This is sound
because the linked module should contain another copy of the bitset entries as
applied to the new global.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 00:17:51 +00:00
Duncan P. N. Exon Smith
4f95bcc836 Plug a leak introduced by r240848
Apparently this obvious leak was never exercised before, but r240848
exposed it.  Plug it.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/5075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240865 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27 00:15:32 +00:00
Adrian Prantl
60bd365f59 Debug Info: Fix a bug in the DW_AT_bit_offset calculation that would
result in negative offsets and attempt a better job at documenting
the algorithm.

rdar://21082998

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240853 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 23:31:27 +00:00
Duncan P. N. Exon Smith
340d78d52d CodeGen: Create a proper ModuleSlotTracker for MachineInstr
Another follow-up related to r240848: try a little harder to share slot
tracking calculations within a single `MachineInstr` dump.  This is
unrelated to `MachineFunction::print()`, since that should be passing
through the function's `ModuleSlotTracker` by now, but could affect the
speed of dumping from a debugger if there is more than one IR-level
operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240852 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 23:18:44 +00:00
Alex Lorenz
d986612a1a MIR Serialization: Serialize global address machine operands.
This commit serializes the global address machine operands.
This commit doesn't serialize the operand's offset and target
flags, it serializes only the global value reference.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10671


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:56:48 +00:00
Philip Reames
60d74b7101 [RewriteStatepointsForGC] Generalized vector phi/select handling for base pointers
This change extends the detection of base pointers for vector constructs to handle arbitrary phi and select nodes. The existing non-vector code already handles those, so this is basically just extending the vector special case to be less special cased. It still isn't generalized vector handling since we can't handle arbitrary vector instructions (e.g. shufflevectors), but it's a lot closer.

The general structure of the change is as follows:
 * Extend the base defining value relation over a subset of vector instructions and vector typed phi & select instructions.
 * Move scalarization from before base pointer rewriting to after base pointer rewriting. The extension of the BDV relation is sufficient to find vector base phis for vector inputs.
 * Preserve the existing special case logic for when the base of a vector element is locally obvious. This general idea could be extended to the scalar case as well.

Differential Revision: http://reviews.llvm.org/D10461#inline-84275



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:47:37 +00:00
Jingyue Wu
a70d990f47 [NVPTX] noop when kernel pointers are already global
Summary:
Some front ends make kernel pointers global already. In that case,
handlePointerParams does nothing.

Test Plan: more tests in lower-kernel-ptr-arg.ll

Reviewers: grosser

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D10779

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:35:43 +00:00
Duncan P. N. Exon Smith
8266df7f7f CodeGen: Push the ModuleSlotTracker through Metadata
For another 1% speedup on the testcase in PR23865, push the
`ModuleSlotTracker` through to metadata-related printing in
`MachineBasicBlock::print()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240848 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:28:47 +00:00
Philip Reames
bb8cc2f850 Minor style cleanup after 240843 [NFC]
Use a for-each loop in one case and rename the function to reflect it's new usage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240847 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:21:52 +00:00
Duncan P. N. Exon Smith
a08efbfc8e CodeGen: Push the ModuleSlotTracker through MachineOperands
Push `ModuleSlotTracker` through `MachineOperand`s, dropping the time
for `llc -print-machineinstrs` on the testcase in PR23865 from ~13
seconds to ~9 seconds.  Now `SlotTracker::processFunctionMetadata()`
accounts for only 8% of the runtime, which seems reasonable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:06:47 +00:00
Philip Reames
982139fde2 [Verifier] Follow on to 240836
Address one missed review comment and do the rename I left out of that patch to make it reviewable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:04:34 +00:00
Duncan P. N. Exon Smith
9a61a42713 CodeGen: Use a single SlotTracker in MachineFunction::print()
Expose enough of the IR-level `SlotTracker` so that
`MachineFunction::print()` can use a single one for printing
`BasicBlock`s.  Next step would be to lift this through a few more APIs
so that we can make other print methods faster.

Fixes PR23865, changing the runtime of `llc -print-machineinstrs` from
many minutes (killed after 3 minutes, but it wasn't very close) to
13 seconds for a 502185 line dump.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 22:04:20 +00:00
Tom Stellard
0be7d0cf17 AMDPGU/SI: Use correct resource descriptors for VI on HSA
Summary: We need to set MTYPE = 2 for VI shaders when targeting the HSA runtime.

Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D10777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:42 +00:00
Tom Stellard
4a888086a4 AMDGPU/SI: Update amd_kernel_code_t definition and add assembler support
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10772

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:31 +00:00
Tom Stellard
4077bd9b3b AMDGPU/SI: Remove unused variable
This should fix some bots that were broken by r240831.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:58:26 +00:00
Philip Reames
f84a6504a6 [Verifier] Verify invokes of intrinsics
We support invoking a subset of llvm's intrinsics, but the verifier didn't account for this.  We had previously added a special case to verify invokes of statepoints.  By generalizing the code in terms of CallSite, we can verify invokes of other intrinsics as well.  Interestingly, this found one test case which was invalid.

Note: I'm deliberately leaving the naming change from CI to CS to a follow up change.  That will happen shortly, I just wanted to reduce the diff to make it clear what was happening with this one.

Differential Revision: http://reviews.llvm.org/D10118



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240836 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:39:44 +00:00
Adrian Prantl
7cb828a34d Debug Info: Clarify the documentation for bitfields emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:27:30 +00:00
Tom Stellard
d40b451727 AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240832 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:11 +00:00
Tom Stellard
ac1a45e511 AMDGPU/SI: Add hsa code object directives
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:07 +00:00
Tom Stellard
4aad126e37 AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10706

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:15:03 +00:00
Tom Stellard
0d1bd457c6 AMDGPU/SI: Emit amd_kernel_code_t in EmitFunctionBodyStart()
Summary:
This way the function symbol points to the start of amd_kernel_code_t
rather than the start of the function.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 21:14:58 +00:00
Philip Reames
64b906419e Teach InlineCost to account for a null check which can be folded away
If we have a caller that knows a particular argument can never be null, we can exploit this fact while simplifying values in the inline cost analysis. This has the effect of reducing the cost for inlining when a null check is present in the callee, but the value is known non null in the caller. In particular, any dependent control flow can be discounted from the cost estimate.

Note that we use the parameter attributes at the call site to memoize the analysis within the caller's code.  The setting of this attribute is done in InstCombine, the inline cost analysis just consumes it.  This is intentional and important because we want the inline cost analysis results to be easily cachable themselves.  We're not currently doing so, but initial results on LTO indicate this will quickly become important.

Differential Revision: http://reviews.llvm.org/D9129



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240828 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 20:51:17 +00:00
Marek Olsak
e874345be4 AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
If pseudoToMCOpcode failed, we would return the original opcode, so operands
would be swapped, but the instruction would remain the same.
It resulted in LSHLREV a, b ---> LSHLREV b, a.

This fixes Glamor text rendering and
piglit/arb_sample_shading-builtin-gl-sample-mask on VI.

This is a candidate for stable branches.

v2: the test was simplified by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240824 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 20:29:10 +00:00
Pete Cooper
6d5c43889e Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:37:02 +00:00
Nemanja Ivanovic
7b3cde87f1 Add missing builtins to the PPC back end for ABI compliance (vol. 1)
This patch corresponds to review:
http://reviews.llvm.org/D10638

This is the back end portion of patch
http://reviews.llvm.org/D10637
It just adds the code gen and intrinsic functions necessary to support that patch to the back end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240820 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:26:53 +00:00
Pete Cooper
a5d25f61ae Wrap assert loops in #ifndef NDEBUG
The body of the loops here only contained asserts.  This triggered an unused variable
warning on release builds and -Werror on the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240819 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:23:20 +00:00
Pete Cooper
e0e37a2382 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:18:49 +00:00
Pete Cooper
226505c0a1 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:08:33 +00:00
Matt Arsenault
57b2119961 Show invariant loads in MMO dumping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 19:00:11 +00:00
David Majnemer
b0e21d44cb Revert "Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant""
This reverts commit r240793 while fixing how we handle array constant
pool entries.

This fixes PR23966.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240811 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 18:55:48 +00:00
Pete Cooper
e89ab0eff9 Convert a bunch of loops to foreach. NFC.
This uses the new SDNode::op_values() iterator range committed in r240805.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 18:41:54 +00:00
Pete Cooper
7c79346d81 Add op_values() to iterate over the SDValue operands of an SDNode.
SDNode already had ops() which would iterate over the operands and return
SDUse*.  This version instead gets the SDValue's out of the SDUse's so that
we can use foreach in more places.

Reviewed by David Blaikie.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 18:17:36 +00:00
David Blaikie
26bc54301b Move VectorUtils from Transforms to Analysis to correct layering violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 18:02:52 +00:00
Javed Absar
d105e18ab6 [ARM] Cortex-R5 is not VFPOnlySP
This patch fixes the error in ARM.td which stated that Cortex-R5
floating point unit can do only single precision, when it can do double as well.

Reviewers: rengolin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10769



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 17:42:37 +00:00
Adam Nemet
e11d1d2c31 [LAA] Try to prove non-wrapping of pointers if SCEV cannot
Summary:
Scalar evolution does not propagate the non-wrapping flags to values
that are derived from a non-wrapping induction variable because
the non-wrapping property could be flow-sensitive.

This change is a first attempt to establish the non-wrapping property in
some simple cases.  The main idea is to look through the operations
defining the pointer.  As long as we arrive to a non-wrapping AddRec via
a small chain of non-wrapping instruction, the pointer should not wrap
either.

I believe that this essentially is what Andy described in
http://article.gmane.org/gmane.comp.compilers.llvm.cvs/220731 as the way
forward.

Reviewers: aschwaighofer, nadav, sanjoy, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 17:25:43 +00:00
Alex Lorenz
cb2dc5bc1c Fix unused variable from r240792.
The variable 'I' wasn't used when assertions were disabled.
This commit ensures that 'I' is used outside of an assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 17:07:27 +00:00
Benjamin Kramer
23a207d839 [DAGCombine] Fix demanded bits computation for exact shifts.
Fixes a miscompilation of MultiSource/Benchmarks/MallocBench/gs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240796 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:59:31 +00:00
Douglas Katzman
cd39f3c6cb [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.
Patch by Matthew Barney. Thanks!

Differential Revision: http://reviews.llvm.org/D9514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:58:59 +00:00
David Blaikie
064274d169 Fix ODR violation waiting to happen by making static function definitions in VectorUtils.h non-static and defined out of line
Patch by Ashutosh Nema

Differential Revision: http://reviews.llvm.org/D10682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:57:30 +00:00
Hans Wennborg
57ec696dfd Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant"
It seems to have caused PR23966: "UNREACHABLE executed at ..\lib\Target\X86\X86TargetObjectFile.cpp:148"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240793 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:48:02 +00:00
Alex Lorenz
438a4919fd MIR Serialization: Serialize machine basic block operands.
This commit serializes machine basic block operands. The
machine basic block operands use the following syntax:

  %bb.<id>[.<name>]

This commit also modifies the YAML representation for the
machine basic blocks - a new, required field 'id' is added
to the MBB YAML mapping.

The id is used to resolve the MBB references to the
actual MBBs. And while the name of the MBB can be
included in a MBB reference, this name isn't used to
resolve MBB references - as it's possible that multiple
MBBs will reference the same BB and thus they will have the
same name. If the name is specified, the parser will verify
that it is equal to the name of the MBB with the specified id.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10608


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240792 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 16:46:11 +00:00
Benjamin Kramer
875007d3c4 [DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.
Allows more aggressive folding of ashr/shl pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240788 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 14:51:49 +00:00
Benjamin Kramer
3791d56da6 [DAGCombine] fold (X >>?,exact C1) << C2 --> X << (C2-C1)
Instcombine also does this but many opportunities only become visible
after GEPs are lowered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240787 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 14:51:36 +00:00
Rafael Espindola
ea767137b6 Rename getObjectFile to getObject for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 14:51:16 +00:00
Toma Tabacu
aafe2ca7d5 [mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 13:20:17 +00:00