Eric Christopher
8b3000b08e
Saving files before committing is overrated.
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Add a RUN line to this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:36:23 +00:00
Eric Christopher
af3dce5149
Sometimes isPredicable lies to us and tells us we don't need the operands.
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Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:09:29 +00:00
Jim Grosbach
7d3a16a6f8
Remove no-longer-correct special case for disasm of ARM BL instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:05:29 +00:00
Jim Grosbach
34e98e968f
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:51:00 +00:00
Jim Grosbach
f859a545de
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
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actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:45:26 +00:00
Jim Grosbach
cea5afc985
Add a FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:25:21 +00:00
Jim Grosbach
72422d38ba
Pseudo-ize the ARM 'B' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:24:15 +00:00
Jim Grosbach
3c5edaaf59
Remove dead code. These ARM instruction definitions no longer exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:15:02 +00:00
Jim Grosbach
5380bbf606
Remove dead code. These ARM instruction definitions no longer exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:11:41 +00:00
Jim Grosbach
f219f3135d
Pseudo-ize VMOVDcc and VMOVScc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:09:50 +00:00
Jim Grosbach
b181ad3486
80 columns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:00:16 +00:00
Jim Grosbach
dd11988c99
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
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effect that we get proper instruction printing using the "pop" mnemonic for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 22:51:41 +00:00
Cameron Zwarich
899eaa3569
Roll r127459 back in:
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Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:52:04 +00:00
Cameron Zwarich
53aac15a60
Fix the GCC test suite issue exposed by r127477, which was caused by stack
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protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:51:56 +00:00
Owen Anderson
2ce5bf188d
Teach FastISel to support register-immediate-immediate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:33:55 +00:00
Jim Grosbach
2a09f878ef
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:02:27 +00:00
Jim Grosbach
108e4dbecb
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:59:19 +00:00
Jim Grosbach
b9cf5f8763
Remove dead code. These ARM instruction definitions don't exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:51:07 +00:00
Jim Grosbach
958108ad14
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:44:08 +00:00
Jim Grosbach
81bb6551e6
Remove dead code. These ARM instruction definitions don't exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:38:18 +00:00
Jim Grosbach
8b8515c225
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:31:17 +00:00
Jim Grosbach
1558df79b4
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:18:05 +00:00
Jim Grosbach
f0112a224f
This FIXME has been fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:07:37 +00:00
Jim Grosbach
e672ff8430
Properly pseudo-ize ARM MVNCCi.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:55:55 +00:00
Jim Grosbach
6a44adade2
Add missing 'return on failure'. Previously we'd crash after emitting
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the diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:52:52 +00:00
Jan Sjödin
e4f6d7461a
Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:37:02 +00:00
Daniel Dunbar
950d3db5f4
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
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created from the", it broke some GCC test suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:30:30 +00:00
Oscar Fuentes
4839ded3bd
Force re-linking of LLVMgold.so when its exports file changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:27:13 +00:00
Oscar Fuentes
aa1fbb40ad
Fix processing of gold.exports.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:07:46 +00:00
Devang Patel
027f0995d4
While printing annotations, print line number and variable name if debug info is present.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:07:33 +00:00
Jim Grosbach
eb582d7ba2
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:00:42 +00:00
Andrew Trick
778583ad28
Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 17:46:59 +00:00
Oscar Fuentes
1dc550b383
Add LTO and gold plugin to the CMake build. Linux-only, support for
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other systems pending.
PR9456.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 15:44:24 +00:00
Benjamin Kramer
2715a58149
ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.
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Should fix the selfhost failures that started with r127463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 14:46:49 +00:00
Benjamin Kramer
6b4972518c
InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.
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Fixes PR9454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 11:37:40 +00:00
Nick Lewycky
b69050a94c
Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
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do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15 !
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 09:00:19 +00:00
John Wiegley
6fd2472b1b
Fix use of CompEnd predicate to be standards conforming
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The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270
This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 08:54:34 +00:00
Cameron Zwarich
592ca3fda9
Optimize trivial branches in CodeGenPrepare, which often get created from the
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lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 04:54:27 +00:00
Jim Grosbach
4a6d735105
Teach TableGen to pre-calculate register enum values when creating the
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CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.
rdar://9066491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 02:19:02 +00:00
Chris Lattner
109d6dbe50
silence a conditional assignment -Wuninitialized warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 02:12:51 +00:00
Jim Grosbach
17fad045cc
Make the register enum value part of the CodeGenRegister struct.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:33:54 +00:00
Jim Grosbach
510207cb1e
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:27:24 +00:00
Jim Grosbach
5d4314ef72
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:19:05 +00:00
Jim Grosbach
7e0e82dcd5
Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:16:49 +00:00
Jim Grosbach
3906276a8d
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:09:28 +00:00
Eric Christopher
de5e101b0d
Change the x86 32-bit scheduler to register pressure and fix up the
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corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:05:58 +00:00
Evan Cheng
9ef82ce4fe
Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 00:48:56 +00:00
Jim Grosbach
d4a16ad85d
Properly pseudo-ize MOVCCr and MOVCCs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 23:56:09 +00:00
Dan Gohman
c9f2f61d34
RecursivelyDeleteTriviallyDeadInstructions only needs a
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Value, not an Instruction, so casting is not necessary. Also,
it's theoretically possible that the Value is not an
Instruction, since WeakVH follows RAUWs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 20:57:44 +00:00
Rafael Espindola
9d2234d6a0
Don't compute the file size if we don't need to.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 20:54:07 +00:00