286 Commits

Author SHA1 Message Date
Kevin Qin
8ab549b856 [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR.
Replace r199791.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 02:53:54 +00:00
Kevin Qin
73840852cf Revert r199791.
It's old version which has some bugs. I'll commit lattest patch soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 02:53:41 +00:00
Rafael Espindola
550d791907 Pass a MCSubtargetInfo down to the TargetStreamer creation.
With this the target streamers will be able to know the target features that
are in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:38:58 +00:00
Rafael Espindola
aa75693ea4 Construct the MCStreamer before constructing the MCTargetStreamer.
This has a few advantages:
* Only targets that use a MCTargetStreamer have to worry about it.
* There is never a MCTargetStreamer without a MCStreamer, so we can use a
  reference.
* A MCTargetStreamer can talk to the MCStreamer in its constructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:06:37 +00:00
Jiangning Liu
da77e83632 Improve pattern match from v1i8 to v1i32 for AArch64 Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 04:55:53 +00:00
Jiangning Liu
6025dbfd67 Implement pattern match from v1xx to v1xx for AArch64 Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200113 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 03:27:40 +00:00
Kevin Qin
97581ccb89 [AArch64 NEON] Add patterns for concat_vector on v2i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200111 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 02:46:15 +00:00
Ana Pazos
08f6677a7f [AArch64] Removed unused i8 type from FPR8 register class.
The i8 type is not registered with any register class.
This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost.

The code selects the first type associated with register class FPR8,
which happens to be i8.
It uses this type (i8) to get the representative class pointer, which is 0.
It then uses this pointer to access a field, resulting in segmentation fault.

Since i8 type is not being used for printing any neon instruction
we can safely remove it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 22:36:53 +00:00
Alp Toker
ae43cab6ba Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 17:20:08 +00:00
Kevin Qin
b1fadec968 [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199978 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 07:53:04 +00:00
Ana Pazos
a8aa6c3940 [AArch64] Added vselect patterns with float and double types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199925 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 19:18:57 +00:00
Kevin Qin
4f046e08ff fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 01:35:13 +00:00
Kevin Qin
0af7a7db53 [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 06:11:03 +00:00
Kevin Qin
9fe8c2b527 [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.
It was commited as r199628 but reverted in r199628 as causing
regression test failed. It's because of old vervsion of patch
I used to commit. Sorry for mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199704 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 01:48:52 +00:00
Chandler Carruth
ce30a8106d Revert r199628: "[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT."
This test fails the newly added regression tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 08:18:01 +00:00
Kevin Qin
f55ec9ac18 [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 07:32:26 +00:00
Kevin Qin
7582d8d76f [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser.
For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be
printed as #0.0 instead of #0. To support the history codes using #0,
we consider to let asm parser accept both #0.0 and #0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 02:14:05 +00:00
Kevin Qin
b9536ac581 [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 09:54:30 +00:00
Hao Liu
84887ceca3 [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.
Also add copy support for FPR16.
Also add a missing test case file belongs to commit r197361.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 06:23:30 +00:00
Kevin Qin
16511208f2 [AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:52:35 +00:00
Hao Liu
555f57f67b [AArch64]Fix the problem can't select concat_vectors of two v1i32 types.
Also fix the problem can't select scalar_to_vector from f32 to v2f32/v4f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 05:44:46 +00:00
Jiangning Liu
b6db372c96 For AArch64, lowering sext_inreg and generate optimized code by using SXTL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199296 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-15 05:08:01 +00:00
Tim Northover
4e1247b836 AArch64: don't try to handle [SU]MUL_LOHI nodes
We should set them to expand for now since there are no patterns
dealing with them. Actually, there are no instructions either so I
doubt they'll ever be acceptable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199265 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 22:53:22 +00:00
Lang Hames
5f33cbc414 Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).

Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199252 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 19:56:36 +00:00
Rafael Espindola
abcf5f971a Revert "[AArch64] Added vselect patterns with float and double types"
This reverts commit r199242.

It is causing CodeGen/AArch64/neon-bsl.ll to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 19:24:08 +00:00
Ana Pazos
cba390a29e [AArch64] Added vselect patterns with float and double types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 18:45:48 +00:00
Andrea Di Biagio
36713c2c0a [AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 16:51:00 +00:00
Kevin Qin
63735e79ff [AArch64 NEON] Add missing patterns for bitcast from or to v1f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 01:58:38 +00:00
Kevin Qin
5c8b8e61df [AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector
This patch covered 2 more scenarios:

1.  Two operands of shuffle_vector are the same, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

2. One of operands is undef, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>

After this patch, perm instructions will have chance to be emitted instead of lots of INS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199069 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 01:56:29 +00:00
Saleem Abdulrasool
b6e0946d40 correct target directive handling error handling
The target specific parser should return `false' if the target AsmParser handles
the directive, and `true' if the generic parser should handle the directive.
Many of the target specific directive handlers would `return Error' which does
not follow these semantics.  This change simply changes the target specific
routines to conform to the semantis of the ParseDirective correctly.

Conformance to the semantics improves diagnostics emitted for the invalid
directives.  X86 is taken as a sample to ensure that multiple diagnostics are
not presented for a single error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199068 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 01:15:39 +00:00
Kristof Beyls
a9608f7f0e Silence unused variable warning for non-asserting builds that was introduced in r198937.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198941 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 14:20:45 +00:00
Kristof Beyls
ac843ff018 Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198937 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 13:41:49 +00:00
Ana Pazos
cb1f0ddce4 [AArch64][NEON] Added UXTL and UXTL2 instruction aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 21:02:13 +00:00
Kevin Qin
4712264fb8 [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANE
when lower build_vector if result value type mismatch with operand
value type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 08:06:14 +00:00
Rafael Espindola
b56c57bcbb Move the llvm mangler to lib/IR.
This makes it available to tools that don't link with target (like llvm-ar).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198708 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 21:19:40 +00:00
Chandler Carruth
974a445bd9 Re-sort all of the includes with ./utils/sort_includes.py so that
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 11:48:04 +00:00
Hao Liu
1a080cef90 [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 10:50:43 +00:00
Hao Liu
9cca551091 [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198682 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 10:00:03 +00:00
Kevin Qin
a4d123f461 [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07 05:10:47 +00:00
Bill Wendling
b87d142ba1 Remove unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 06:00:00 +00:00
Bill Wendling
4644d79871 Refactor function that checks that __builtin_returnaddress's argument is constant.
This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-06 00:43:20 +00:00
Bill Wendling
4a816471f5 Emit an error message if the value passed to __builtin_returnaddress isn't a constant
__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 01:47:20 +00:00
Rafael Espindola
8e0f67dcec Make the llvm mangler depend only on DataLayout.
Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198438 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03 19:21:54 +00:00
Ana Pazos
5124fef085 [AArch64][NEON] Added SXTL and SXTL2 instruction aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03 19:20:31 +00:00
Rafael Espindola
33cc3f81c1 Remove the 's' DataLayout specification
During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were

* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
  DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
  to the byval.

This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.

I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 22:29:43 +00:00
Jiangning Liu
90128bee68 For AArch64 Neon, simplify scalar dup by lane0 for fp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198194 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:44:35 +00:00
Hao Liu
afcdbf7400 [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:38:12 +00:00
Hao Liu
43ffcc571c [AArch64]Can't select shift left 0 of type v1i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:12:46 +00:00
Hao Liu
3796015b5b [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.
E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 01:38:41 +00:00
Hao Liu
0f6ebf1aa3 [AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect.
E.g. the codegen result is 
     fmls v1.2s, v0.2s, v2.s[3]
which is expected to be
     fmls v0.2s, v1.2s, v2.s[3]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198001 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 07:12:34 +00:00