Commit Graph

418 Commits

Author SHA1 Message Date
9bfa2dcff6 TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28765 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-13 13:08:58 +00:00
232c910b8a Start on my todo list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28752 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-12 16:07:18 +00:00
7e399c14ab Another typo. Pointed out by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28353 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 18:22:14 +00:00
e9b3da17cd Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28351 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17 18:10:06 +00:00
3e348494bb this should be 128 I think
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28330 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 17:45:23 +00:00
dae9cbe8d4 Move this code to a common place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28329 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 17:42:15 +00:00
07000c6f01 Refactor a bunch of includes so that TargetMachine.h doesn't have to include
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 06:33:49 +00:00
1b7371331f When tracking demanded bits, if any bits from the sext of an SRA are demanded,
then so is the input sign bit.  This fixes mediabench/g721 on X86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28166 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-08 17:22:53 +00:00
822db93e57 Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28155 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 23:48:13 +00:00
e60351bb72 Add some more sign propagation cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28154 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 23:40:29 +00:00
d6f7fe76a6 Add some more simple sign bit propagation cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28149 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 22:39:59 +00:00
5c3e21d687 Add some really really simple code for computing sign-bit propagation.
This will certainly be enhanced in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28145 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 09:27:13 +00:00
c93dfda905 Fold (trunc (srl x, c)) -> (srl (trunc x), c)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28138 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-06 00:11:52 +00:00
fe8babf689 Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28135 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-05 22:32:12 +00:00
a69571c799 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 01:29:57 +00:00
1b5232a937 relax assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27358 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 06:19:46 +00:00
1482b5fc7a Allow targets to compute masked bits for intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27357 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 06:15:09 +00:00
a6c9de4293 Was returning the wrong type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27277 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 01:50:09 +00:00
79227e2906 Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:46:36 +00:00
dc87929609 Implement TargetLowering::getPackedTypeBreakdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27270 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 00:28:56 +00:00
677274b1cb Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27008 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 23:24:51 +00:00
3a59358499 set TransformToType correctly for vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26797 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 19:50:01 +00:00
30b37b5f29 Add LSR hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 23:18:16 +00:00
b6b17ffbc6 I can't convince myself that this is safe, remove the recursive call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26725 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 06:42:16 +00:00
c1d9f1de41 Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
we want to canonicalize the other way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26547 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 19:52:57 +00:00
33143dce15 Number of NodeTypes now exceeds 128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26503 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 06:58:59 +00:00
00ffed0468 Add interfaces for targets to provide target-specific dag combiner optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 04:52:55 +00:00
a6bc5a4d21 Implement bit propagation through sub nodes, this (re)implements
PowerPC/div-2.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 01:00:42 +00:00
81cd35586f Check RHS simplification before LHS simplification to avoid infinitely looping
on PowerPC/small-arguments.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 00:36:27 +00:00
5f0c658aa4 Just like we use the RHS of an AND to simplify the LHS, use the LHS to
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 00:22:28 +00:00
ec665151b8 Add a bunch of missed cases. Perhaps the most significant of which is that
assertzext produces zero bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-26 23:36:02 +00:00
2b7401e28e Recognize memory operand codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26345 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 01:10:46 +00:00
b3befd41b4 Don't return registers from register classes that aren't legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26317 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 23:00:51 +00:00
1efa40f6a4 split register class handling from explicit physreg handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 00:56:39 +00:00
4217ca8dc1 Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 23:11:00 +00:00
003a272319 Add a fold for add that exchanges it with a constant shift if possible, so
that the shift may be more easily folded into other operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26286 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 02:43:25 +00:00
5755b17044 Fix bug noticed by VC++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26252 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-17 02:12:18 +00:00
368e18d56a Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 21:11:51 +00:00
a03a5dc7ce Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:38:30 +00:00
eb8146b5ee implementation of some methods for inlineasm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25951 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:13:02 +00:00
244d1dccd1 Implement some feedback from sabre
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25946 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-03 22:38:07 +00:00
de99629e2a Add a framework for eliminating instructions that produces undemanded bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-03 22:24:05 +00:00
9a06cce0f2 Implement MaskedValueIsZero for ANY_EXTEND nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25900 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 06:43:15 +00:00
a55079a5cc Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25866 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 01:29:47 +00:00
c6fd6cd65c Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 04:09:27 +00:00
87c890a9c2 adjust prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 03:49:07 +00:00
3e6e8cc26b clean up interface to ValueTypeActions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25783 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 08:41:12 +00:00
4ccb070f15 Implement a method for inline asm support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25660 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 20:37:03 +00:00
ee4a76563a initialize an instance var, apparently I forgot to commit this long ago
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25609 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 18:57:15 +00:00
0577a22c67 Set SchedulingForLatency to be the default scheduling preference for all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25607 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 18:52:42 +00:00