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234 Commits

Author SHA1 Message Date
Elena Demikhovsky
17bbdd05dd AVX-512: Extend/Truncate operations for SKX, 
SETCC for bit-vectors



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235875 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-27 12:57:59 +00:00
Elena Demikhovsky
bf704ed348 AVX-512: Added VPMOVx2M instructions for SKX, 
fixed encoding of VPMOVM2x.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235385 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 14:38:31 +00:00
Elena Demikhovsky
695922de3d AVX-512: Added VPTESTM and VPTESTNM instructions for SKX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235383 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 13:13:46 +00:00
Elena Demikhovsky
a1fa0de258 AVX-512: Added logical and arithmetic instructions for SKX 
by Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235375 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 10:27:40 +00:00
Elena Demikhovsky
4eb165220f AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB 
by Asaf Badouh (asaf.badouh@intel.com)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233906 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-02 10:51:40 +00:00
Elena Demikhovsky
10e73aeede AVX-512: blank lines, duplicated tests, no functional changes 
see comments http://reviews.llvm.org/D6835


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233528 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-30 09:29:28 +00:00
Elena Demikhovsky
a8f971683a AVX-512: Fixed the "commutative" property flag in VPANDN instruction 
By Asaf Badouh (asaf.badouh@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233489 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-29 09:14:29 +00:00
Elena Demikhovsky
3209a40889 AVX-512: Added encoding tests for VPROR, VPROL instructions, 
fixed opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232018 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-12 07:28:41 +00:00
Elena Demikhovsky
13cc6f2b6e AVX-512: Added SKX forms of shift instructions. 
Added rotation instructions, encoding only.
Added encoding tests for all these forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231916 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-11 10:25:42 +00:00
Elena Demikhovsky
e670dc7848 AVX-512, SKX: Enabled masked_load/store operations for this target. 
Added lowering for ISD::CONCAT_VECTORS and ISD::INSERT_SUBVECTOR for i1 vectors,
it is needed to pass all masked_memop.ll tests for SKX.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231371 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-05 15:11:35 +00:00
Elena Demikhovsky
ae765411fc AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes. 
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231069 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-03 15:03:35 +00:00
Elena Demikhovsky
e206743835 AVX-512: Simplified MOV patterns, no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230954 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-02 12:46:21 +00:00
Craig Topper
a2d7ca4495 [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230924 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-02 00:22:29 +00:00
Elena Demikhovsky
bf4d9a8aaf Reverted 230471 - gather scatter handling in table gen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230892 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-01 08:23:41 +00:00
Elena Demikhovsky
975e9b99aa AVX-512: Added mask and rounding mode for scalar arithmetics 
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230891 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-01 07:44:04 +00:00
Elena Demikhovsky
4105fd49d4 AVX-512: Gather and Scatter patterns 
Gather and scatter instructions additionally write to one of the source operands - mask register.
In this case Gather has 2 destination values - the loaded value and the mask.
Till now we did not support code gen pattern for gather - the instruction was generated from 
intrinsic only and machine node was hardcoded.
When we introduce the masked_gather node, we need to select instruction automatically,
in the standard way.
I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands.

(Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big
patch in many small patches)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230471 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-25 09:46:31 +00:00
Elena Demikhovsky
fdafc8fd5e AVX-512: recommitted 229837 + bugfix + test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230223 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-23 15:12:31 +00:00
Eric Christopher
8c4bb575e1 Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics." 
The instructions were being generated on architectures that don't support avx512.

This reverts commit r229837.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229942 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-20 00:45:28 +00:00
Eric Christopher
74678a1ed1 Add a license header to the AVX512 file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229941 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-20 00:36:53 +00:00
Elena Demikhovsky
675d06d1d0 AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229837 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-19 10:48:04 +00:00
Elena Demikhovsky
87483ed180 AVX-512: Added support for FP instructions with embedded rounding mode. 
By Asaf Badouh <asaf.badouh@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229645 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 07:59:20 +00:00
Elena Demikhovsky
199f58a198 AVX-512: changes in intel_ocl_bi calling conventions 
- added mask types v8i1 and v16i1 to possible function parameters
- enabled passing 512-bit vectors in standard CC
- added a test for KNL intel_ocl_bi conventions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229482 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-17 09:20:12 +00:00
Elena Demikhovsky
f41b8e3e49 AVX-512: Fixed the "test" operation for i1 type 
Using KORTESTW for comparison i1 value with zero was wrong since the instruction tests 16 bits.
KORTESTW may be used with KSHIFTL+KSHIFTR that clean the 15 upper bits.
I removed (X86cmp i1, 0) pattern and zero-extend i1 to i8 and then use TESTB.

There are some cases where i1 is in the mask register and the upper bits are already zeroed.
Then KORTESTW is the better solution, but it is subject for optimization.
Meanwhile, I'm fixing the correctness issue.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228916 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-12 08:40:34 +00:00
Craig Topper
bd477dfbbf [X86] Remove 'memop' uses from AVX512. Use 'load' instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228562 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-09 04:04:50 +00:00
Elena Demikhovsky
b9d3801cd2 AVX-512: Added FMA intrinsics with rounding mode 
By Asaf Badouh and Elena Demikhovsky

Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227303 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:21:27 +00:00
Craig Topper
aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 10:09:56 +00:00
Elena Demikhovsky
717d41d8c3 AVX-512: Changes in operations on masks registers for KNL and SKX 
- Added KSHIFTB/D/Q for skx
- Added KORTESTB/D/Q for skx
- Fixed store operation for v8i1 type for KNL
- Store size of v8i1, v4i1 and v2i1 are changed to 8 bits



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227043 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 12:47:15 +00:00
Craig Topper
ff763041d2 [X86] Give scalar VRNDSCALE instructions priority in AVX512 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227039 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 08:49:22 +00:00
Craig Topper
e3792c042d Simplify a multiclass. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227038 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 08:49:19 +00:00
Craig Topper
896c1e9b70 [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make the assembler bounds check them. It will also make them print as unsigned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227032 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:16 +00:00
Craig Topper
046047ccc3 [X86] Use u8imm in several places that used i32i8imm that don't require an i32 type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227031 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-25 02:21:13 +00:00
Craig Topper
c3942c9623 [X86] Add IntrNoMem to the AVX512 conflict intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226897 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-23 06:11:45 +00:00
Craig Topper
deb2e51099 Revert r226798. Guess I missed the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226802 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 09:01:20 +00:00
Craig Topper
efad370a06 Use u8imm instead of i32i8imm on a couple instructions that have no patterns and thus no reason to use a larger operand size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226798 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 08:53:11 +00:00
Craig Topper
6660dcedd3 [X86] Remove some unused multiclasses from AVX512 instruction file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226797 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-22 08:53:08 +00:00
Craig Topper
51da87a580 [X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226646 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 08:43:49 +00:00
Craig Topper
f81b1f346a [x86] Add assembly parser bounds checking to the immediate value for cmpss/cmpsd/cmpps/cmppd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226642 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 06:07:53 +00:00
Craig Topper
d624796bc6 [x86] Add some mayLoad/hasSideEffects flags. Remove one that was already covered by a pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226562 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 12:15:30 +00:00
Craig Topper
6f91bd79f3 [x86] Change AVX512 intrinsics to take a 8-bit immediate for the comparision kind instead of a 32-bit immediate. This better aligns with the emitted instruction. It also matches SSE and AVX1 equivalents. Also add auto upgrade support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226430 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-19 06:07:27 +00:00
Adam Nemet
ad2ac976af [AVX512] Add intrinsics for masked aligned FP loads and stores 
Similar to the unaligned cases.

Test was generated with update_llc_test_checks.py.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226296 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-16 18:50:09 +00:00
Craig Topper
06185e7f6b Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226155 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 09:37:15 +00:00
Craig Topper
04c853b269 [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Correctly this time. I did the wrong patterns the first time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224891 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 20:08:45 +00:00
Craig Topper
d840bf4ba9 [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Forgot to do this when I did SSE/SSE2/AVX/AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-27 18:51:06 +00:00
Elena Demikhovsky
1a637e9fc0 AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets 
by Asaf Badouh

http://reviews.llvm.org/D6456



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224764 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 10:30:39 +00:00
Elena Demikhovsky
6709428067 AVX-512: BLENDM - fixed encoding of the broadcast version 
Added more intrinsics and encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224760 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 09:36:28 +00:00
Elena Demikhovsky
c1aa521fb4 AVX-512: Added all forms of BLENDM instructions, 
intrinsics, encoding tests for AVX-512F and skx instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224707 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-22 13:52:48 +00:00
Elena Demikhovsky
573b762b68 Masked load and store codegen - fixed 128-bit vectors 
The codegen failed on 128-bit types on AVX2.
I added patterns and in td files and tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224647 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-19 23:27:57 +00:00
Robert Khasanov
43906dedbf [AVX512] Add a comment for avx512_broadcast_pat multiclass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224341 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 16:12:11 +00:00
Elena Demikhovsky
3f2027522c AVX-512: Added EXPAND instructions and intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224241 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-15 10:03:52 +00:00
Robert Khasanov
b59ec5ad50 [AVX512] Minor fix in lowering pattern for broadcast intrustions. 
No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224122 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-12 14:21:30 +00:00