6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-10 16:24:04 +00:00
Code Issues Projects Releases Wiki Activity
86,280 Commits 39 Branches 0 Tags 277 MiB
96df437a03
Commit Graph

604 Commits

Author SHA1 Message Date
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 18:26:50 +00:00
Jim Grosbach
b6744db06f Thumb2 ADR assembly parsing w/o the .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 23:52:17 +00:00
Jim Grosbach
4677708d4f ARM/Thumb2 mov vs. mvn alias goes both ways. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:56:51 +00:00
Jim Grosbach
8d11c6349f ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 17:30:24 +00:00
Jim Grosbach
863d2af947 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 22:45:11 +00:00
Jim Grosbach
b0659873e6 Thumb2 pre/post indexed stores can be from any non-PC GPR. 
rdar://10549786

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 21:10:25 +00:00
Jim Grosbach
e91e7bcadc ARM pre-UAL NEG mnemonic for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:23:22 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 22:02:17 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:31:07 +00:00
Jim Grosbach
8524bca750 Thumb2 alias for long-form pop and friends. 
rdar://10542474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 18:32:28 +00:00
Jim Grosbach
cf9814ddd2 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 05:03:45 +00:00
Jim Grosbach
7f1ec9570d Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 19:55:16 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 00:58:43 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Jim Grosbach
5d0492cfc4 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:57:07 +00:00
Jim Grosbach
88484c0030 Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:16:55 +00:00
Jim Grosbach
a581328ceb Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:22:01 +00:00
Jim Grosbach
9c5edc00c4 Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 17:28:15 +00:00
Jim Grosbach
f8e74f816d Thumb2 LDM instructions can target PC. Make sure to encode it. 
PR11220


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:16:24 +00:00
Andrew Trick
90b7b12f01 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 19:18:52 +00:00
Andrew Trick
7f5f0dae33 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:40:53 +00:00
Jim Grosbach
9858a48afc Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:09:35 +00:00
Eli Friedman
0851a29b6d Fix misc warnings. Patch by Joe Abbey. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 03:17:34 +00:00
Bill Wendling
13a7121858 Now Igor, throw the switch...give my creation life! 
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:23 +00:00
Cameron Zwarich
6f9c28060f Pseudoinstructions should not be less constrained than the instruction they are 
lowered to. This fixes a lot of verifier failures on the test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:20:13 +00:00
Cameron Zwarich
daada347b5 Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. 
These missing flags show up as errors when running -verify-coalescing on
test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 06:38:10 +00:00
Cameron Zwarich
d575137634 Fix an obvious typo found when looking at nearby code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 06:38:06 +00:00
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:59:55 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:27:30 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:15:08 +00:00
Kevin Enderby
9e5887b17e Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 22:44:48 +00:00
Jim Grosbach
b95ed6ec46 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:51:59 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:21:38 +00:00
Jim Grosbach
25ddc2bf7e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 22:18:54 +00:00
Owen Anderson
2dafe200ca Remove extraneous commit garbage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:14:02 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
Owen Anderson
4a713570b6 Add more fixed bits to USAT16 encoding to filter out incorrect decodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:57:50 +00:00
Owen Anderson
0781c1f700 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 21:26:40 +00:00
Owen Anderson
6126870193 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:53:44 +00:00
Owen Anderson
e136872970 Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 23:44:46 +00:00
Andrew Trick
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-21 02:20:46 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Jim Grosbach
50f1c37123 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:46:54 +00:00
Jim Grosbach
8c9898454c Remove incorrect comments. These are not disassmebly only patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:26:34 +00:00
Jim Grosbach
0efe213ed5 Thumb2 range check on CPS mode immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:58:31 +00:00
Jim Grosbach
32f36899e9 Tidy up comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 23:38:34 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
Jim Grosbach
bc80e94865 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:31:59 +00:00
Jim Grosbach
326efe5891 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:29:33 +00:00
Owen Anderson
061c3c4506 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 20:00:02 +00:00
Jim Grosbach
8a8d28b039 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 17:56:37 +00:00
Jim Grosbach
f67e8554bf Thumb2 assembly parsing and encoding for SUB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:58:42 +00:00
Owen Anderson
8a28bdcbcc Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 22:17:02 +00:00
Jim Grosbach
ee2c2a4f98 Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:55:56 +00:00
Jim Grosbach
947a24cd64 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:09:00 +00:00
Jim Grosbach
642caea2c6 Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 21:06:12 +00:00
Jim Grosbach
8213c96655 Thumb2 assembly parsing and encoding for STMIA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:50:13 +00:00
Jim Grosbach
b105b997a4 Thumb2 assembly parsing and encoding for SSAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:32:30 +00:00
Jim Grosbach
05ec8f7ac9 Thumb2 assembly parsing and encoding for SRS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 18:25:22 +00:00
Jim Grosbach
7ff2472b82 Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 17:10:44 +00:00
Jim Grosbach
231948f860 Thumb2 assembly parsing and encoding for SMLALD/SMLALDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 16:58:03 +00:00
Jim Grosbach
eeca7582fa Remove incorrect comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:45:50 +00:00
Jim Grosbach
191d33fd6d Thumb2 assembly parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 20:54:14 +00:00
Jim Grosbach
689b86ed2e Thumb2 assembly parsing and encoding for REV16/REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 19:46:13 +00:00
Jim Grosbach
1b69a128d6 Thumb2 assembly parsing and encoding for REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:13:30 +00:00
Jim Grosbach
57b21e437a Thumb2 push/pop mnemonic recognition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 15:55:04 +00:00
Jim Grosbach
0b69247b10 Thumb2 assembly parsing and encoding for PKH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:41 +00:00
Jim Grosbach
d32872f9ca Thumb2 assembly parsing and encoding for MVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:24:41 +00:00
Jim Grosbach
bf841cf336 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 20:03:46 +00:00
Owen Anderson
7782a58b87 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:46:26 +00:00
Eli Friedman
885f1a0c04 Zap some junk from the ARM instruction descriptions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 02:29:58 +00:00
Owen Anderson
cd00dc6852 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 21:28:46 +00:00
Jim Grosbach
1ad60c2adc Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 00:15:36 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Jim Grosbach
0811fe13d6 Thumb2 assembly parsing and encoding for LDRSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:42:40 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Jim Grosbach
e64fb28da1 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:39:19 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc Thumb2 assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:10:15 +00:00
Jim Grosbach
8bb5a861a0 Thumb2 assembly parsing and encoding for LDRB(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:41:25 +00:00
Owen Anderson
8a83f71301 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 21:10:42 +00:00
Jim Grosbach
a8307dd1c9 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 20:58:57 +00:00
Jim Grosbach
cfbb3a78db Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix. 
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:39:47 +00:00
Jim Grosbach
ffa5a76344 Thumb2 use 'ldm' as default mnemonic. 
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 16:22:42 +00:00
Jim Grosbach
218affc710 ISB is HasDB, not just HasV7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 23:09:19 +00:00
Jim Grosbach
aa833e53dc Thumb2 parsing and encoding for ISB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:53:27 +00:00
Jim Grosbach
06c1a51241 Thumb2 parsing and encoding for DMB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:14:58 +00:00
Jim Grosbach
77951908b7 Thumb2 parsing and encoding for DBG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 22:06:40 +00:00
Jim Grosbach
ef88a92677 Thumb2 parsing and encoding for CMN and CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 21:44:58 +00:00
Jim Grosbach
ad2dad930d Thumb2 parsing and encoding for CLREX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 20:27:04 +00:00
Evan Cheng
4a51708448 Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-06 18:52:20 +00:00
Jim Grosbach
6c3e11ea55 Thumb2 parsing and encoding for BXJ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:43:09 +00:00