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2643 Commits

Author SHA1 Message Date
Gabor Greif
a99be51bf5 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 17:07:56 +00:00
Dale Johannesen
e377d4d142 Refactor X87 instructions. As a side effect, all 
their names are changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37876 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-04 21:07:47 +00:00
Bill Wendling
10404c47d1 Support generation of GR64 to MMX code in the JIT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37866 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-04 01:29:22 +00:00
Bill Wendling
93888428d4 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-04 00:19:54 +00:00
Dale Johannesen
411d9c5467 Some spacing fixes. Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37853 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-03 17:07:33 +00:00
Dale Johannesen
849f214a4e Fix for PR 1505 (and 1489). Rewrite X87 register 
model to include f32 variants.  Some factoring
improvments forthcoming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-03 00:53:03 +00:00
Dan Gohman
1866f6ec7b Vector results may be returned in XMM0 and XMM1, not just XMM0. With 
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37844 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-02 16:21:53 +00:00
John Criswell
e644ef7b09 Convert .cvsignore files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 16:35:07 +00:00
Evan Cheng
a72cb0ea09 No vector fneg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37786 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 00:18:15 +00:00
Evan Cheng
0db5862cb8 Type of vector extract / insert index operand should be iPTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37784 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 00:01:20 +00:00
Dan Gohman
6445f61806 Remove a redundant newline in the asm output for ELF .rodata sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37756 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-27 15:09:47 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Dan Gohman
7f32156bb9 Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-25 16:23:39 +00:00
Dan Gohman
32791e06d8 Make minor adjustments to whitespace and comments to reduce differences 
between SSE1 instructions and their respective SSE2 analogues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37718 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-25 15:44:19 +00:00
Dan Gohman
01976307d2 Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37717 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-25 15:19:03 +00:00
Dan Gohman
8bc49c2fe7 Say AT&T instead of Intel in the comments for AT&T support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37716 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-25 15:11:25 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 14:59:07 +00:00
Dale Johannesen
5411835165 Quote complex names for Darwin X86 and ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-22 00:54:56 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Chris Lattner
52387be1e0 If a function is vararg, never pass inreg arguments in registers. Thanks to 
Anton for half of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 00:13:10 +00:00
Evan Cheng
49892af264 Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37636 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 00:02:56 +00:00
Dan Gohman
638c96d391 Define the pushq instruction for x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37625 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-18 14:12:56 +00:00
Bill Wendling
a9e64f6f2d Revert patch. It regresses: 
define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37617 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-16 23:57:15 +00:00
Bill Wendling
e81369f2a5 Fix a failure to bit_convert from integer GPR to MMX register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37611 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-16 06:17:31 +00:00
Dan Gohman
51eaa86758 Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-14 22:58:02 +00:00
Dale Johannesen
318093b6f8 Do not treat FP_REG_KILL as terminator in branch analysis (X86). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37578 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-14 22:03:45 +00:00
Dan Gohman
c101e95cb6 Add a target hook to allow loads from constant pools to be rematerialized, and an 
implementation for x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37576 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-14 20:50:44 +00:00
Dan Gohman
af67ea7318 Eliminate some redundant newlines in asm output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37574 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-14 15:00:27 +00:00
Dale Johannesen
13e8b51e3e Handle blocks with 2 unconditional branches in AnalyzeBranch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-13 17:59:52 +00:00
Chris Lattner
fdbe720416 fix x86-64 mmx calling convention for real, which passes in integer gprs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37534 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-09 05:08:10 +00:00
Chris Lattner
6b7c21cc30 fix mmx handling bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37533 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-09 05:01:50 +00:00
Evan Cheng
bfd2ec4a8e Add a utility routine to check for unpredicated terminator instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 21:59:56 +00:00
Evan Cheng
111354ff99 Misuse of hasExternalLinkage(), should be checking isDeclaration(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37419 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-04 18:54:57 +00:00
Dan Gohman
237898ac1f Add explicit qualification for namespace MVT members. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37320 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-24 14:33:05 +00:00
Bill Wendling
cd6cea0823 We only need to specify the most-implied feature for an architecture. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37275 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-22 05:15:37 +00:00
Evan Cheng
126f17a176 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:44:17 +00:00
Chris Lattner
60c7a136f3 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37239 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 20:18:14 +00:00
Dan Gohman
fa0f77d9b7 Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37234 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 18:44:07 +00:00
Evan Cheng
6ae3626a4f RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:18:17 +00:00
Evan Cheng
213d2cf94f Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37173 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 18:45:50 +00:00
Evan Cheng
174f803395 Added missing patterns for UNPCKH* and PUNPCKH*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37172 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 18:44:37 +00:00
Chris Lattner
07c70cd866 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37160 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 17:13:13 +00:00
Anton Korobeynikov
f840202953 Revert patch for PR1427. It breaks almost all vector tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37159 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 07:50:14 +00:00
Chris Lattner
a066810681 add support for 128-bit integer add/sub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37154 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 06:35:11 +00:00
Chris Lattner
da66472ea6 Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37141 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 03:29:42 +00:00
Chris Lattner
738a6ec0ae implement the missing maskmovq mmx intrinsic that akor hit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37100 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 06:08:17 +00:00
Chris Lattner
709fd414e2 fix subtle bugs in inline asm operand selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37065 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:28:08 +00:00
Anton Korobeynikov
0ff3ca4f92 More DWARF-related things cleanup: 
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37015 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-12 22:36:25 +00:00
Chris Lattner
0f1621bb4c add some notes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-10 00:08:04 +00:00
Bill Wendling
11d8fdaf6a 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36860 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-06 07:56:19 +00:00
Nate Begeman
9a22530696 Reference correct header 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36834 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-06 04:00:55 +00:00
Chris Lattner
0258011bb9 move CodeGen/X86/overlap-add.ll here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36799 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 22:10:24 +00:00
Anton Korobeynikov
2a07e2f4df Emit sections/directives in the proper order. This fixes PR1376. Also, 
some small cleanup was made.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36780 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 09:04:50 +00:00
Bill Wendling
4222d806fa Add an "implies" field to features. This indicates that, if the current 
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 20:38:40 +00:00
Chris Lattner
dc43a88b81 Fix two classes of bugs: 
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
  2. the matcher didn't correctly reject and accept some global addresses.
     the right predicate is GVRequiresExtraLoad, not "relomodel = pic".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36670 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 16:52:29 +00:00
Dan Gohman
6f858e250b Sets the section names for fixed-size constants and use the mergeable 
flag for ELF on x86 so that duplicate constants can be eliminated by
the linker. This matches what GCC does with its -fmerge-constants
option, which is enabled at most -O levels.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36666 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 16:38:57 +00:00
Devang Patel
1997473cf7 Drop 'const' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 01:11:54 +00:00
Bill Wendling
ddd35321fb Non-algorithmic change. Moved definitions around into separate sections 
for SSE1, SSE2, SSE3, and SSSE3.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36656 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 23:11:52 +00:00
Bill Wendling
4b693b01fb Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36653 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 21:42:20 +00:00
Devang Patel
3e15bf33e0 Use 'static const char' instead of 'static const int'. 
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 21:39:20 +00:00
Anton Korobeynikov
ce3b46552a Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux 
with non-llvm-compiled (e.g. "native") unwind runtime.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36647 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 19:53:33 +00:00
Anton Korobeynikov
038082d966 Emit correct DWARF reg # for RA (return address) register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36646 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-02 08:46:03 +00:00
Anton Korobeynikov
79dda2b048 Fix couple of bugs connected with eh info: 
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36633 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 22:23:12 +00:00
Devang Patel
794fd75c67 Do not use typeinfo to identify pass in pass manager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 21:15:47 +00:00
Anton Korobeynikov
edb4a6bd76 Use correct PC symbol 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 10:19:31 +00:00
Anton Korobeynikov
71144d8428 Adjust correct EH-related sections 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36627 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 10:16:06 +00:00
Evan Cheng
97de913821 eliminateFrameIndex() change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 09:13:03 +00:00
Anton Korobeynikov
6f9896fcc8 Implement protected visibility. This partly implements PR1363. Linker 
should be taught to deal with protected symbols.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36565 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-29 18:35:00 +00:00
Dan Gohman
2a3250cd23 Fix PR1339 and CodeGen/X86/dollar-name.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36495 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 21:07:05 +00:00
Bill Wendling
bff35d11f1 Have MMX registers clobbered in x86-64 too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36494 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 21:06:48 +00:00
Evan Cheng
a24ddddf68 Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of add / sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36456 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 01:09:28 +00:00
Evan Cheng
6c087e5585 Match MachineFunction::UsedPhysRegs changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 22:13:27 +00:00
Bill Wendling
3f3a17dd62 Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers 
clobbered by a call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36448 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 21:31:48 +00:00
Chris Lattner
7c6eefa5f1 do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292 
when promoted to 64-bits


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36442 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 17:23:53 +00:00
Anton Korobeynikov
8b0a8c84da Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part 
will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36435 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 14:27:10 +00:00
Evan Cheng
1e341729dd Relex assertions to account for additional implicit def / use operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 07:12:14 +00:00
Chris Lattner
ea84c5ee95 support for >4G stack frames 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36425 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 04:30:24 +00:00
Chris Lattner
618078016d support >4G stack frames 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36423 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 04:25:10 +00:00
Bill Wendling
a2c38ae90d Update. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36407 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:20:03 +00:00
Bill Wendling
b53e98eb30 Add the PADDQ to the list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36406 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:19:14 +00:00
Bill Wendling
69dc5332de Add the final MMX instructions. Correct a few wrong patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36405 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:18:37 +00:00
Bill Wendling
6dd29e08f7 Remove some invalid instructions from this check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36404 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:17:46 +00:00
Bill Wendling
2f9bb1a0a4 Support for the special case of a vector with the canonical form: 
vector_shuffle v1, v2, <2, 6, 3, 7>

I.e.

         vector_shuffle v, undef, <2, 2, 3, 3>

MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36403 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:16:55 +00:00
Lauro Ramos Venancio
ede1d78969 X86 TLS: optimize the implementation of "local exec" model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36359 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 01:28:10 +00:00
Lauro Ramos Venancio
7d2cc2b983 X86 TLS: fix and optimize the implementation of "initial exec" model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36355 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-22 22:50:52 +00:00
Lauro Ramos Venancio
2c5c111b6c X86 TLS: Implement review feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 20:56:26 +00:00
Jeff Cohen
09b362cee6 Comment out usage of write() for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36287 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 22:40:10 +00:00
Lauro Ramos Venancio
b3a0417cad Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:38:10 +00:00
Evan Cheng
6120433e9e Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36279 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:15:21 +00:00
Jeff Cohen
5d4d7f1580 Make Microsoft assembler and linker happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36265 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 00:33:54 +00:00
Dan Gohman
23420c09c0 Fix the spelling of the prefetchnta instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36256 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 14:09:14 +00:00
Anton Korobeynikov
e060b5385f Add comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36213 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 19:34:00 +00:00
Chris Lattner
d15dff24c6 rename X86FunctionInfo to X86MachineFunctionInfo to match the header file 
it is defined in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36196 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 17:21:52 +00:00
Anton Korobeynikov
57fc00d5cf Implemented correct stack probing on mingw/cygwin for dynamic alloca's. 
Also, fixed static case in presence of eax livin. This fixes PR331

PS: Why don't we still have push/pop instructions? :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36195 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 09:20:00 +00:00
Chris Lattner
56ecbf3013 SSE4 is apparently public now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36185 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 00:02:37 +00:00
Jeff Cohen
c398709525 In the event that some really old non-Intel or -AMD CPU is encountered... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36177 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 21:59:44 +00:00
Jeff Cohen
22114c319a Before assuming that the original code didn't work for Athlon64, the person who 
replaced it with a FIXME should have determined what did work.  Then he would have
realized that the code was in fact correct, and would have avoided breaking it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36173 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 21:48:58 +00:00
Anton Korobeynikov
bed2946a96 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 18:10:23 +00:00
Chris Lattner
7c162645ae add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36028 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 23:06:09 +00:00
Chris Lattner
6c284d716e Fix mmx paddq, add support for the 'y' register class, though it isn't tested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35940 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 04:14:49 +00:00
Chris Lattner
a1b253f58e Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35926 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 22:29:46 +00:00
Chris Lattner
b062000c23 done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35884 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-11 05:34:00 +00:00
Bill Wendling
bb1ee05253 Add support for our first SSSE3 instruction "pmulhrsw". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 22:10:25 +00:00
Chris Lattner
bae3bd7c19 new micro optzn 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35867 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 21:14:01 +00:00
Chris Lattner
eb8c74ddf2 remove some dead hooks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35845 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 23:31:19 +00:00
Chris Lattner
b445d0cbb9 remove some dead target hooks, subsumed by isLegalAddressingMode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 22:27:04 +00:00
Chris Lattner
0f65cad57f move a bunch of register constraints from being handled by 
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint.  This allows us to let the llvm register allocator
allocate, which gives us better code.  For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:

_run_init_process:
        subl $4, %esp
        movl %ebx, (%esp)
        xorl %ebx, %ebx
        movl $11, %eax
        movl %ebx, %ecx
        movl %ebx, %edx
        # InlineAsm Start
        push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End

Now we get:
_run_init_process:
        xorl %ecx, %ecx
        movl $11, %eax
        movl %ecx, %edx
        # InlineAsm Start
        push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35804 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 05:49:22 +00:00
Chris Lattner
e5a24ec782 implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values 
used with x constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35803 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 05:31:48 +00:00
Chris Lattner
ad043e85f8 implement CodeGen/X86/inline-asm-x-scalar.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35799 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-09 05:11:28 +00:00
Bill Wendling
71bfd11c67 Adding more MMX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:48:32 +00:00
Chris Lattner
8ceb0fd2d3 make a new missing features section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35637 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:41:34 +00:00
Bill Wendling
92ca81601c Updated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35634 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 23:37:20 +00:00
Bill Wendling
c9c9d2d554 Changed to new MMX_ recipes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35617 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:18:31 +00:00
Bill Wendling
823efee633 Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-03 06:00:37 +00:00
Chris Lattner
3e9f1d09c0 fix breakage from last night, simplify code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35560 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-01 20:49:36 +00:00
Anton Korobeynikov
ad7baee241 Consistency with native compilers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35532 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 13:11:52 +00:00
Bill Wendling
577c7d9dca Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35531 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 09:36:12 +00:00
Bill Wendling
db5c993121 Match GCC's MMX calling convention. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35523 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-31 01:03:53 +00:00
Chris Lattner
c9addb7488 implement the new addressing mode description hook. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 23:15:24 +00:00
Bill Wendling
e2501b303c Add MMX calling conventions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35489 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-30 00:35:22 +00:00
Bill Wendling
03179060ee Made this into a bug report: PR1286 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35439 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 19:07:34 +00:00
Anton Korobeynikov
f6e9353e1a Oops :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35438 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 18:38:33 +00:00
Anton Korobeynikov
33bf8c44dd Don't allow MatchAddress recurse too much. This trims exponential 
behaviour in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35437 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 18:36:33 +00:00
Chris Lattner
6ef3307062 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35435 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 18:17:19 +00:00
Chris Lattner
995f55036f Compile CodeGen/X86/lea-3.ll:test2 to: 
_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35434 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 18:12:31 +00:00
Chris Lattner
e9a61234ce Dan pointed out that this is done, remove it! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35430 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 17:26:52 +00:00
Bill Wendling
a80d7bd665 Remove cruft I put in there... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35394 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 01:02:54 +00:00
Chris Lattner
f2177b89a1 Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the 
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35393 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 00:58:40 +00:00
Bill Wendling
826f36ff80 Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35392 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-28 00:57:11 +00:00
Bill Wendling
6dc29ece6e Add the "unpack low packed data" instructions. This should be the last of 
the MMX instructions that are needed...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35389 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 21:20:36 +00:00
Bill Wendling
ccc44add81 Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35385 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 20:22:40 +00:00
Bill Wendling
ab5b49d92e Promote to v1i64 type... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 08:03:33 +00:00
Bill Wendling
aadcea33d1 Updated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35352 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 07:55:58 +00:00
Bill Wendling
eebc8a1bc5 Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-26 07:53:08 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:14:49 +00:00
Chris Lattner
1439352ece Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35320 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:01:03 +00:00
Chris Lattner
188b9fe834 enforce the proper range for the i386 N constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35319 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:57:35 +00:00
Chris Lattner
7cd5e07f3d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:44:57 +00:00
Anton Korobeynikov
3b5ee73a13 Autodetect MMX & SSE stuff for AMD processors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35292 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 23:46:48 +00:00
Bill Wendling
b8440a0c39 PR1260: 
Add final support to get the QT example to compile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:35:46 +00:00
Bill Wendling
02ced83ce7 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35269 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 20:29:26 +00:00
Bill Wendling
a348c56fde Support added for shifts and unpacking MMX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 18:42:45 +00:00
Dale Johannesen
fa4bce2b76 repair x86 performance, dejagnu problems from previous change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 21:51:52 +00:00
Dale Johannesen
aceaf5d26e add generation of unnecessary push/pop around calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35241 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 21:16:39 +00:00
Evan Cheng
768143547b Mark re-materializable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35230 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 00:16:56 +00:00
Evan Cheng
bf2c8b3c96 Added MRegisterInfo hook to re-materialize an instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 08:09:38 +00:00
Chris Lattner
a16b7cb1d3 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 06:08:29 +00:00
Chris Lattner
d435dbcbf9 fix a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35152 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 00:39:32 +00:00
Devang Patel
84f7fd2483 Support 'I' inline asm constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35129 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-17 00:13:28 +00:00
Bill Wendling
1b7a81d3ae And now support for MMX logical operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-16 09:44:46 +00:00