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20042 Commits

Author SHA1 Message Date
Jim Grosbach
c66e7afcf2 Thumb2 assembly parsing and encoding for LDC/STC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa addrmode2 is gone from these, so no need for the reg0 operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 18:11:24 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Jim Grosbach
01208d56e8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 16:36:01 +00:00
Jim Grosbach
bc9c80240b Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 16:34:37 +00:00
Akira Hatanaka
41f9a430cb Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
6baabc1dd0 Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:56:06 +00:00
Nick Lewycky
1f9c6860bf Fix indent in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:14:12 +00:00
Jakob Stoklund Olesen
1c062c24ab Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:06:23 +00:00
Akira Hatanaka
80eb994929 Change name of class to ArithOverflowR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
2dfd3a9789 Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:38:52 +00:00
Akira Hatanaka
76d9f1c022 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
c2f3ac9de2 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 23:05:46 +00:00
Akira Hatanaka
68ad5673e8 Fix function isUnalignedLoadStore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 22:04:01 +00:00
Jim Grosbach
2bd0118472 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:55:36 +00:00
Akira Hatanaka
d8212b2916 Remove unused PatLeaf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141720 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
7cc037a137 Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:48:01 +00:00
Bill Wendling
e575499d83 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:40:47 +00:00
Akira Hatanaka
395d76c5a3 Remove redundancy in setcc patterns using multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 21:40:01 +00:00
Akira Hatanaka
b07a3d6897 Use sltiu instead of sltu when a register operand and immediate are compared. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:44:43 +00:00
Jim Grosbach
2cf8dd384e ARM addressing mode cleanup for LDC/STC. 
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 20:17:35 +00:00
Akira Hatanaka
06f8231bfb Add patterns for conditional branches with 64-bit register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
8191f34797 Add support for 64-bit set-on-less-than instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
3e3427a5c3 Add support for conditional branch instructions with 64-bit register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:49:17 +00:00
Jim Grosbach
57dcb85a30 ARM parse alignment specifier for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 17:29:55 +00:00
Jim Grosbach
e53c87b302 ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 15:59:20 +00:00
Richard Osborne
6c6f28ffe4 Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks. 
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 12:55:35 +00:00
Kalle Raiskila
56354d48bb Fix a iterator out of bounds error, that triggers rarely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 12:55:18 +00:00
Craig Topper
c48b301fb0 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:13:09 +00:00
Craig Topper
227358e93c Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:01:37 +00:00
Craig Topper
37f2167f15 Add X86 LZCNT instruction. Including instruction selection support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:44:02 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Akira Hatanaka
1acb7df498 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:12:52 +00:00
Jakob Stoklund Olesen
142bd1a54e Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). 
The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:59:06 +00:00
Akira Hatanaka
a5903acd6b Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:55:05 +00:00
Lang Hames
4ad06e61c0 Fixed natural stack alignment for Linux x86-32. Thanks Eli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141616 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:51:36 +00:00
Akira Hatanaka
381e97dcf6 Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141615 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:44:20 +00:00
Akira Hatanaka
43aed32e20 Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
7bd19bd519 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:27:28 +00:00
Akira Hatanaka
d55bb38ddc Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141603 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:11:12 +00:00
Bill Wendling
3f56d4b957 Simplify check that optional def is there and is CPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:10:41 +00:00
Lang Hames
bb5b3f3359 Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:42:08 +00:00
Jim Grosbach
f6c35c59f5 Simplify operand Kind checks a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:06:42 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315 Add a name to sub-operand for clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:55:05 +00:00
Bill Wendling
721e1d2669 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:52:53 +00:00
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:28:47 +00:00
Benjamin Kramer
717073c237 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:35:07 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:31:45 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00