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b1fa7d4d26
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1799 Commits

Author SHA1 Message Date
Reed Kotler
b1fa7d4d26 Fix some issues with Mips16 floating when certain intrinsics are present. 
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the 
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 21:17:53 +00:00
Vladimir Medic
588f408b95 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 09:25:27 +00:00
Reed Kotler
f71698747e Fix some misc. issues with Mips16 fp stubs. 
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 02:26:31 +00:00
Reed Kotler
d49475bebc Add an omitted IsCall=1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 00:59:06 +00:00
Akira Hatanaka
782638aa0d [mips] Rename instruction DANDi to ANDi64. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:57:41 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
80bec28b66 [mips] Delete instruction format for "bal". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 20:42:19 +00:00
Akira Hatanaka
8838da6587 [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that 
turns "bal" into "bgezal".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 20:24:24 +00:00
Vladimir Medic
b67775df0c This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 10:12:14 +00:00
Akira Hatanaka
c0fa31d51b [mips] Add comment and simplify function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187371 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-29 19:08:34 +00:00
Akira Hatanaka
9758562aa7 [mips] Implement llvm.trap intrinsic. 
Patch by Sasa Stankovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:58:55 +00:00
Akira Hatanaka
407883b69b [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:51:20 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:13:47 +00:00
Akira Hatanaka
0fc641df37 [mips] Increase the number of floating point condition code registers to eight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 19:03:48 +00:00
Akira Hatanaka
9955cb931b [mips] Fix floating point branch, comparison, and conditional move instructions 
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 19:01:56 +00:00
Akira Hatanaka
d6a7ea2736 [mips] Delete register print method MipsInstPrinter::printCPURegs that is not 
needed. The generic method printOperand will do.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 18:50:42 +00:00
Akira Hatanaka
9b06dd6ca2 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo 
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 18:34:25 +00:00
Akira Hatanaka
94ce6dadd1 [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFail 
when there wasn't a match. This behavior is consistent with other register
parsing methods.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187063 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-24 18:43:52 +00:00
Petar Jovanovic
959d2f70fb [test commit] Minor comment change. 
Testing commit access credentials.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-24 13:02:35 +00:00
Craig Topper
f63ef914b6 Split generated asm mnemonic matching table into a separate table for each asm variant. 
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-24 07:33:14 +00:00
Akira Hatanaka
9a05b98ef9 [mips] Fix MipsAsmParser::parseCCRRegs. 
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 19:30:38 +00:00
Akira Hatanaka
0b92642767 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 18:52:22 +00:00
Akira Hatanaka
da218210f7 [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-19 01:19:52 +00:00
Vladimir Medic
764f6f5125 This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-18 09:28:35 +00:00
Akira Hatanaka
27d0c68617 [mips] Use "foreach" loop to make register definitions more concise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186528 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-17 19:09:27 +00:00
Vladimir Medic
fce9279ac0 This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-17 15:00:42 +00:00
Vladimir Medic
16f385f90f Implement eret and deret(return from exception) instructions for Mips. Test examples are given. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-17 14:05:19 +00:00
Juergen Ributzka
17c95a217d Test commit to verify write access. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-16 17:44:23 +00:00
Vladimir Medic
ab42fc66b1 Fixing a buildbot failure:unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186403 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-16 11:43:20 +00:00
Vladimir Medic
0884836277 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-16 10:07:14 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-14 04:42:23 +00:00
Akira Hatanaka
434c0bd2a5 [mips] Implement MipsTargetMachine::getInstrItineraryData(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186227 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 23:33:22 +00:00
Akira Hatanaka
ae24f7d3c6 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 22:43:20 +00:00
Vladimir Medic
dd51a0c1e0 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-12 09:25:35 +00:00
Vladimir Medic
296c1534b4 Reverting commit r185999 due to buildboot failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 12:26:26 +00:00
Vladimir Medic
2ec5933eae Add support for Mips break and syscall insructions. The corresponding test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-10 10:18:10 +00:00
Jakob Stoklund Olesen
f349a6e9e6 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 13:54:20 +00:00
Craig Topper
6227d5c690 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 01:31:24 +00:00
Jakob Stoklund Olesen
c93822901a Revert r185595-185596 which broke buildbots. 
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen
62204220e1 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 23:56:31 +00:00
Craig Topper
365ef0b197 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 15:07:05 +00:00
Akira Hatanaka
a66aacf6d7 [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 00:00:02 +00:00
Akira Hatanaka
5112243aec [mips] Reverse the order of source operands of shift and rotate instructions that 
have three register operands.

No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 20:39:53 +00:00
Akira Hatanaka
db8e0bbedb [mips] Increase the number of floating point control registers available to 32. 
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 20:31:44 +00:00
Chad Rosier
096c0a0331 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg 
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 22:23:32 +00:00
Akira Hatanaka
842cfc91f2 [mips] Do not emit ".option pic0" if target is mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 19:08:49 +00:00
Akira Hatanaka
9a308df027 [mips] Improve code generation for constant multiplication using shifts, adds and 
subs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 18:48:17 +00:00
Vladimir Medic
90b1086b93 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 10:05:34 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-22 18:37:38 +00:00
Vladimir Medic
7231625f75 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 11:21:49 +00:00