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c075510e43
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283 Commits

Author SHA1 Message Date
Jim Grosbach
c075510e43 Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:17:31 +00:00
Jim Grosbach
b80ab8e369 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:39:39 +00:00
Jim Grosbach
c9a9b44285 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 18:29:05 +00:00
Jim Grosbach
0f3abd8d68 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:07:33 +00:00
Jim Grosbach
f8e1e3e729 Thumb2 parsing and encoding for IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:24:09 +00:00
Owen Anderson
0da10cf44d Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 19:36:44 +00:00
Owen Anderson
63553c77cd Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:17:09 +00:00
Jim Grosbach
4af54a461f ARM assembly parsing tweak for pldw. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:21:51 +00:00
Jim Grosbach
89df996ab2 Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:43:41 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Jim Grosbach
0c49ac05cd Explicitly disallow predication in Thumb1 assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:23:55 +00:00
Jim Grosbach
4d23e99d2a Thumb .n mnemonic qualifiers can be ignored for now. 
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:19:48 +00:00
Jim Grosbach
f69c804036 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:42:27 +00:00
Jim Grosbach
72f39f8436 Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:22:15 +00:00
Jim Grosbach
f95aaf951b Add missing explicit writeback operand to tSTMIA_UPD. 
rdar://10014745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:19:42 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 18:08:43 +00:00
Evan Cheng
7801136b95 Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 20:15:21 +00:00
Jim Grosbach
1e84f19337 Thumb parsing and encoding for STM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 18:15:37 +00:00
Jim Grosbach
aa875f8c6f Factor low reg checking into a helper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 18:13:04 +00:00
Jim Grosbach
04d55f1905 Thumb parsing and encoding for SBC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:55:58 +00:00
Jim Grosbach
934755ac04 Thumb parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:47:13 +00:00
Jim Grosbach
6dcafc0d0b Improve error checking for tPUSH and tPOP register lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:17:34 +00:00
Jim Grosbach
7260c6a4ea Thumb assemmbly parsing diagnostic improvements for LDM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:01:07 +00:00
Jim Grosbach
11e03e7c2d Tighten up ARM reglist validation a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:50:36 +00:00
Jim Grosbach
0780b6303b Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 23:24:36 +00:00
Jim Grosbach
2c3f70e5d4 Thumb assembly parsing and encoding for NEG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:51:03 +00:00
Jim Grosbach
7a01069420 Be more lenient on tied operand matching for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:46 +00:00
Jim Grosbach
88ae2bc6d5 Thumb assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:07:46 +00:00
Jim Grosbach
4ec6e888ec Thumb assembly parsing and encoding for MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:46:54 +00:00
Jim Grosbach
1b7b68f087 Thumb assembly parsing and encoding for LSL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:29:25 +00:00
Jim Grosbach
38466309d5 Thumb assembly parsing and encoding for LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:55:51 +00:00
Jim Grosbach
48ff5ffe9e Thumb assembly parsing and encoding for LDRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:49:59 +00:00
Jim Grosbach
ecd8589683 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:13:48 +00:00
Jim Grosbach
2f7232efd5 Use helper function to check for low registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 17:57:22 +00:00
Jim Grosbach
60f91a3d95 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 17:55:24 +00:00
Jim Grosbach
93b3eff623 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 21:50:53 +00:00
Jim Grosbach
3ce23d3d87 Add missing 'break'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 16:08:39 +00:00
Jim Grosbach
395b453bed Thumb assembly parsing and encoding for B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:57:40 +00:00
Jim Grosbach
00f5d98205 Thumb assembly parsing and encoding for ASR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:49:09 +00:00
Jim Grosbach
70939ee141 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 21:51:27 +00:00
Jim Grosbach
89e2aa6afd Thumb ADD(immediate) parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:57:34 +00:00
Jim Grosbach
194bd89829 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:20:01 +00:00
Jim Grosbach
00c9a51888 Add missing exit for 'case'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137774 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:42:31 +00:00
Jim Grosbach
3912b73c74 Thumb assembly parsing and encoding for ADD(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:34:08 +00:00
Jim Grosbach
d54b4e612a Move some logic into a helper function and expand the commentary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137756 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:12:37 +00:00
Jim Grosbach
47a0d52b69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:45:50 +00:00
Jim Grosbach
19cb7f491f MCTargetAsmParser target match predicate support. 
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:03:29 +00:00
Jim Grosbach
857e1a7b3f ARM vector compare to zero instruction assembly parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:51:13 +00:00
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00