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147 Commits

Author SHA1 Message Date
Eli Friedman
84e7f7e267 X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 19:43:50 +00:00
Dan Gohman
a0697a7ef5 Add a comment describing why transforming (shl x, 1) to (add x, x) is to be 
considered safe enough in this context.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 15:55:48 +00:00
Benjamin Kramer
b22da2a72c X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 18:32:01 +00:00
Stuart Hastings
0e29ed081b Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends. 
rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 19:04:40 +00:00
Stuart Hastings
d22f036c2a Reverting 131641 to investigate 'bot complaint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 17:54:42 +00:00
Stuart Hastings
b6dcf3c514 Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be 
pseudos.  rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 16:59:50 +00:00
Eric Christopher
c324f72ab7 Support XOR and AND optimization with no return value. 
Finishes off rdar://8470697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 08:10:18 +00:00
Eric Christopher
b38fe4b52d Optimize atomic lock or that doesn't use the result value. 
Next up: xor and and.

Part of rdar://8470697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 23:57:45 +00:00
Eric Christopher
988397dcbc Refactor lock versions of binary operators to be a little less 
cut and paste.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 18:36:16 +00:00
Benjamin Kramer
f51190b697 X86: Add a bunch of peeps for add and sub of SETB. 
"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-08 18:36:07 +00:00
Dan Gohman
64849ce66f The labyrinthine X86 backend no longer appears to require 
these patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-17 18:50:19 +00:00
NAKAMURA Takumi
7754f85885 Target/X86: Tweak win64's tailcall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:04:09 +00:00
NAKAMURA Takumi
e5fffe9c3f Fix whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:03:37 +00:00
Eric Christopher
cdfe3c359b The stub routine that we're calling uses test and so clobbers 
the flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 01:37:20 +00:00
Chris Lattner
39ffcb7b62 We lower setb to sbb with the hope that the and will go away, when it 
doesn't, match it back to setb.

On a 64-bit version of the testcase before we'd get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbb	%dl, %dl
	andb	$1, %dl
	ret

now we get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	setb	%dl
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 01:16:03 +00:00
Chris Lattner
c19d1c3ba2 improve the setcc -> setcc_carry optimization to happen more 
consistently by moving it out of lowering into dag combine.

Add some missing patterns for matching away extended versions of setcc_c.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-19 22:08:31 +00:00
Evan Cheng
f735f2da6e Only rr forms of ADD*_DB are commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121908 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 22:57:36 +00:00
Eric Christopher
2871768f40 Add rsp to the uses for the same reason as 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 00:26:41 +00:00
Rafael Espindola
d652dbe720 Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-28 21:16:39 +00:00
Rafael Espindola
5bf7c534cf Lower TLS_addr32 and TLS_addr64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-27 20:43:02 +00:00
Chris Lattner
4d1189f385 reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 00:46:16 +00:00
Chris Lattner
a4a3a5e3c2 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-31 19:15:18 +00:00
Michael J. Spencer
e9c253e0bc X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 01:41:01 +00:00
Michael J. Spencer
6e56b18e57 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 23:40:27 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 13:31:20 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:00:49 +00:00
Chris Lattner
15df55d8c2 reapply: Use the new TB_NOT_REVERSABLE flag instead of special 
reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da reapply the patch reverted in r116033: 
"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into 
'add'", which seems to have broken just about everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:32 +00:00
Daniel Dunbar
32f0cdba30 Revert "reimplement the second half of the or/add optimization. We should now", 
which depends on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:26 +00:00
Chris Lattner
cd3167b281 reimplement the second half of the or/add optimization. We should now 
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 01:05:10 +00:00
Chris Lattner
122e2ea043 Reimplement (part of) the or -> add optimization. Matching 'or' into 'add' 
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies.  However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA.  This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:36:18 +00:00
Chris Lattner
6dbbff9172 Move cmov pseudo instructions to InstrCompiler, 
convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe Use #NAME# to have the CMOV multiclass define things with the same names as before 
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745 convert cmov mr patterns to use a multipattern. Death to redundancy 
and verbosity


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e switch CMOVBE to the multipattern: 
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:23:58 +00:00
Chris Lattner
2c383d8c4d move SETB pseudos into the same place in InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:18:04 +00:00
Chris Lattner
d8cc2722a4 move some instructions from Instr64Bit -> InstrInfo. 
bswap32 doesn't read eflags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:47:35 +00:00
Chris Lattner
5673e1d314 move CMOV_FR32 and friends to InstrCompiler, since they are 
pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:41:40 +00:00
Chris Lattner
41efbfaa66 move various pattern matching support goop out of X86Instr64Bit, to live 
with the 32-bit stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:37:31 +00:00
Chris Lattner
35649fc3dd split conditional moves and setcc's out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:33:16 +00:00
Chris Lattner
d3f033d969 move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:27:48 +00:00
Chris Lattner
010496c6a7 move the atomic pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115599 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:22:35 +00:00
Chris Lattner
8af88ef157 move more pseudo instructions out to X86InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:10:16 +00:00
Chris Lattner
87be16a9e1 continue moving stuff out to X86InstrSystem.td. Move 
control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 06:04:14 +00:00