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434 Commits

Author SHA1 Message Date
Evan Cheng
055b0310f8 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 07:51:04 +00:00
David Goodwin
caffbd7b01 ORN and BIC tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74289 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 16:20:06 +00:00
Evan Cheng
6677f51127 Fix tests: Count -> count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 07:05:57 +00:00
Evan Cheng
c0ad80fd9e Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74276 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 05:59:16 +00:00
Evan Cheng
6267422318 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:34:10 +00:00
Evan Cheng
1e249e3705 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 20:59:23 +00:00
Evan Cheng
9f76ed5127 Move thumb and thumb2 tests into separate directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 06:36:07 +00:00
Evan Cheng
a67efd1226 Proper patterns for thumb2 shift and rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 19:39:13 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Evan Cheng
524961e57f It's coalescer, not coaleser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:09:17 +00:00
Bob Wilson
54fc124d72 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:01:46 +00:00
Evan Cheng
81909b7423 Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 20:49:32 +00:00
Evan Cheng
8dcbbdd00e hasFP should return true if frame address is taken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 18:38:48 +00:00
Evan Cheng
694f6c81e8 Fix PR4419: handle defs of partial uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73816 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 04:34:51 +00:00
Evan Cheng
ae69a2a12b Enable arm pre-allocation load / store multiple optimization pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 23:17:27 +00:00
Eli Friedman
6b7bb42c36 Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 01:43:08 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
a4e968cb0e Make the test target-neutral 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 20:25:25 +00:00
Anton Korobeynikov
2932795309 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 18:49:08 +00:00
Evan Cheng
67fcf56ac4 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. 
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 07:12:58 +00:00
Evan Cheng
2077e18caf ifcvt should ignore cfg where true and false successors are the same. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 21:24:34 +00:00
Evan Cheng
358dec5180 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 08:28:29 +00:00
Evan Cheng
e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from 
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-13 09:12:55 +00:00
Evan Cheng
4a274e573d If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 21:34:26 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-12 20:46:18 +00:00
Anton Korobeynikov
f194b0edc9 Add testcase for register scanveger assertion fix in r72755 
(double def due to livevars)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73096 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:54:15 +00:00
Evan Cheng
925492279a Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-05 19:08:58 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:49:04 +00:00
Evan Cheng
cd0c4ac7fb A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72888 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 20:25:48 +00:00
Evan Cheng
1488326156 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 01:15:28 +00:00
Evan Cheng
70fd60bd57 Temporarily revert 72756 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0 Fold preceding / trailing base inc / dec into the single load / store as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-03 06:14:58 +00:00
Bob Wilson
04746eae49 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and 
the stack.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 10:02:36 +00:00
Bob Wilson
224c244f56 Fix pr4091: Add support for "m" constraint in ARM inline assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 05:53:42 +00:00
Dan Gohman
04623272d2 Add nounwind to a few tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72002 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-18 15:16:49 +00:00
Bob Wilson
74b0ccc577 Fix pr4195: When iterating through predecessor blocks, break out of the loop 
after finding the (unique) layout predecessor.  Sometimes a block may be listed
more than once, and processing it more than once in this loop can lead to
inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not
clear these values.  There's no point in continuing the loop regardless.
The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource
test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71536 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-12 03:48:10 +00:00
Bob Wilson
9d928c223f Fix pr4100. Do not remove no-op copies when they are dead. The register 
scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.

Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move.  Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move.  The move ends up being a no-op, copying R3 to R3, so it is
deleted.  But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.

Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
  Regs have values: 
  Reloading %reg1028 into R3
  Last use of R3[%reg1028], removing it from live set
  Assigning R3 to %reg1025
  Register R3 [%reg1025] is never used, removing it from live set

Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy.  I couldn't see an easy way to do
either of those, though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71196 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-07 23:47:03 +00:00
Evan Cheng
caab129cd1 Do not use register as base ptr of pre- and post- inc/dec load / store nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-06 18:25:01 +00:00
Dan Gohman
afc36a9520 Previously, RecursivelyDeleteDeadInstructions provided an option 
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.

Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.

This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70636 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-02 18:29:22 +00:00
Bob Wilson
7eb793dd09 Rename file to have the correct suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69380 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-17 20:40:20 +00:00
Bob Wilson
1f595bb429 Use CallConvLower.h and TableGen descriptions of the calling conventions 
for ARM.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-17 19:07:39 +00:00
Dan Gohman
2d1be87ee4 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now 
have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.

Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.

Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69258 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-16 03:18:22 +00:00
Dale Johannesen
442b7bfc80 Use the output of the asm so the optimizer won't 
delete it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69018 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-14 01:51:40 +00:00
Chris Lattner
dbf1e2b08b move a target-specific test into its directory so it isn't run if you 
don't configure the ARM target in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-10 23:58:38 +00:00
Bob Wilson
d9df501704 Fix pr3954. The register scavenger asserts for inline assembly with 
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-09 17:16:43 +00:00
Bob Wilson
83593a369b Add testcase for PR3795. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68620 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-08 18:00:55 +00:00
Duncan Sands
3d0355b825 Soft float support for FREM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68614 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-08 16:20:57 +00:00
Duncan Sands
7beb1ec298 Soft float support for undef. Reported by Xerxes Rånby. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68607 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-08 13:33:37 +00:00
Bob Wilson
8f3434647d Handle 'a' modifier in ARM inline assembly. 
Patch by Richard Pennington.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-06 21:46:51 +00:00
Bob Wilson
bf6396bed0 Fix PR3862: Recognize some ARM-specific constraints for immediates in inline 
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-01 17:58:54 +00:00
Evan Cheng
f1c0ae9de5 Do not emit comments unless -asm-verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 00:17:40 +00:00
Chris Lattner
1285295e61 add no-unwind, remove duplicate run line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66775 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-12 05:56:37 +00:00
Evan Cheng
6501153fc0 ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-09 19:15:00 +00:00
Evan Cheng
4b1747430a Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-08 04:02:49 +00:00
Evan Cheng
821b8560e7 If a MI uses the same register more than once, only mark one of them as 'kill'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-08 03:58:35 +00:00
Evan Cheng
c8bb37a50a Last commit accidentially deleted this code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65679 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-28 06:02:14 +00:00
Evan Cheng
04cf3e39f3 The last commit was overly conservative. It's ok to reuse value that's already marked livein. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65498 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-26 03:02:21 +00:00
Evan Cheng
58207f12ee If a use operand is marked isKill, don't forget to add kill to its live interval as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-22 08:35:56 +00:00
Evan Cheng
bf18939180 A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-17 06:41:03 +00:00
Evan Cheng
8182347d70 Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 08:59:45 +00:00
Evan Cheng
f0e366a929 Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64210 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-10 08:30:11 +00:00
Evan Cheng
8f0d99e463 Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-09 08:45:39 +00:00
Bill Wendling
7f51fd3ea9 Revert r63999. It was breaking self-hosting builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64062 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-08 00:58:05 +00:00
Evan Cheng
c963b638c7 Enable machine sinking pass in non-fast mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63999 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-07 01:57:46 +00:00
Evan Cheng
c5d1a4ffd9 Turn on machine LICM in non-fast mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63855 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-05 08:46:33 +00:00
Rafael Espindola
bb46f52027 Add the private linkage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 20:18:42 +00:00
Evan Cheng
c3ccc1aaaf Clean up some ARM GV asm printing out; minor fixes to match what gcc does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60621 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-06 02:00:55 +00:00
Evan Cheng
d37c13cfd1 - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. 
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59697 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-20 02:32:35 +00:00
Evan Cheng
9c64bf3905 Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59559 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-18 22:28:38 +00:00
Evan Cheng
3eb22e835f Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 22:19:55 +00:00
Evan Cheng
c7c77297e2 Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 19:57:48 +00:00
Devang Patel
2c9c3e7368 Implement function notes as function attributes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56716 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-26 23:51:19 +00:00
Evan Cheng
870e4bef41 Unallocatable registers do not have live intervals. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56287 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-17 18:36:25 +00:00
Dan Gohman
5eb0cecbc5 Re-enable SelectionDAG CSE for calls. It matters in the case of 
libcalls, as in this testcase on ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56226 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-15 19:46:03 +00:00
Evan Cheng
25f34a30d6 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56199 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-15 06:28:41 +00:00
Evan Cheng
4b88702ac3 Legalizer was missing code that expand fpow to a libcall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56028 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-09 23:02:14 +00:00
Evan Cheng
711b6dce24 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54519 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 06:56:16 +00:00
Anton Korobeynikov
feac94b18d Print section flags ok on platforms, which use '@' as comment string. Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54460 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 09:55:06 +00:00
Owen Anderson
287b7b7ed7 This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54355 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 17:52:54 +00:00
Owen Anderson
3888aa0b7d Remove the need for -disable-correct-folding from this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54354 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 17:49:52 +00:00
Owen Anderson
2b85dc3544 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54334 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:55:29 +00:00
Evan Cheng
d1b3da621b Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54004 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-25 00:55:17 +00:00
Duncan Sands
c3e26727c1 Softfloat support for FDIV. Patch by 
Richard Pennington.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53773 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-18 21:18:48 +00:00
Gabor Greif
f6cadc440c sabre brings to my attention that the 'tr' suffix is also obsolete 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51349 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-20 21:00:03 +00:00
Gabor Greif
722243bd40 Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51328 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-20 19:52:04 +00:00
Evan Cheng
7a0f1851ec More local spiller complexity! 
If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51306 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-20 08:13:21 +00:00
Evan Cheng
b0a6f62c9b Don't spill dead def. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51305 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-20 08:10:37 +00:00
Evan Cheng
f870fbc554 If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49543 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-11 17:54:45 +00:00
Evan Cheng
b94d966716 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49514 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-10 23:49:09 +00:00
Evan Cheng
1dc7869025 1. IMPLICIT_DEF can *re-define* any register. 
2. Coalescer can now create an interesting situation where a register def can
   reaches itself without being killed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49246 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-05 01:27:09 +00:00
Evan Cheng
9845eb5b03 More soft fp fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49016 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-01 02:18:22 +00:00
Evan Cheng
110cf48752 Unbreak ARM / Thumb soft FP support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49012 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-01 01:50:16 +00:00
Evan Cheng
d68f47c6fd Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48024 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-07 20:12:54 +00:00
Evan Cheng
433f6f62ca Constant fold SIGN_EXTEND_INREG with ashr not lshr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47992 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-06 08:20:51 +00:00
Bill Wendling
65201f5a43 DCE'ed this testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47760 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 19:28:11 +00:00
Bill Wendling
97e3c01eb4 If we reload a virtual register that's already been assigned, we want to mark 
that instruction as its "last use". This fixes PR1925.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47758 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 18:52:01 +00:00
Tanya Lattner
6263f94674 Remove llvm-upgrade. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47238 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-17 20:02:20 +00:00
Evan Cheng
b745e88bf0 It's PR1925, not PR1609. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46825 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-06 22:07:17 +00:00
Evan Cheng
2fc628d662 Fix a number of local register allocator issues: PR1609. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46821 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-06 19:16:53 +00:00
Chris Lattner
15c2351a93 Update this test. Due to dag combiner improvements, we now compile 
f7/f11 to:

_f7:
	eor r0, r0, #2, 2 @ -2147483648
	bx lr
_f11:
	bic r0, r0, #2, 2 @ -2147483648
	bx lr

instead of:

_f7:
	fmsr s0, r0
	fnegs s0, s0
	fmrs r0, s0
	bx lr

_f11:
	fmsr s0, r0
	fabss s0, s0
	fmrs r0, s0
	bx lr



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46423 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-27 23:26:37 +00:00
Evan Cheng
e3c1cfb181 Remove xfail. This is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45254 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-20 02:25:21 +00:00
Evan Cheng
33faddc35d Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44660 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-06 08:54:31 +00:00
Evan Cheng
5ef3a04b54 Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-06 00:01:56 +00:00
Evan Cheng
213ee902cc Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44435 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-29 10:03:54 +00:00
Chris Lattner
2adcf10a80 update this test after the fmrrd fix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44393 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-28 05:27:07 +00:00
Tanya Lattner
727842e9d7 Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines. 
XFAILed 3 arm regressions (will file bugs)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44389 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-28 04:57:00 +00:00
Chris Lattner
a5d4a4e33e commit testcase I forgot to svn add. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44383 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-27 22:43:37 +00:00
Lauro Ramos Venancio
e0cb36b9fb [ARM] Implement __builtin_thread_pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-08 17:20:05 +00:00
Lauro Ramos Venancio
8699a97a2e [ARM] Fix code generation for: 
static __thread struct {
    int a;
    int b;
} teste = {0, 0};



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43722 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-05 18:33:37 +00:00
Evan Cheng
4102eb57bb Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-22 22:11:27 +00:00
Chris Lattner
f8f7cf3987 new testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42953 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-13 06:56:18 +00:00
Evan Cheng
b7c8017208 Disable if-conversion for this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42170 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 18:06:22 +00:00
Evan Cheng
4226689f44 -enable-arm-if-conversion is gone. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42169 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-20 18:03:23 +00:00
Dale Johannesen
c2ec2baf3d Change all floating constants that are not exactly 
representable to use hex format.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41722 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-05 17:50:36 +00:00
Duncan Sands
e9685143f4 Testcases for PR1628. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41719 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-05 11:53:04 +00:00
Lauro Ramos Venancio
c90f08936d Implement FPOWI ExpandOp. 
Fix PR1287.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41112 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 22:13:27 +00:00
Evan Cheng
77f8b72af2 Test case for PR1609. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41110 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 20:30:10 +00:00
Dan Gohman
64d8e1b9a7 This test used "wc | grep ..."; convert it to use the count script. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41101 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 13:55:47 +00:00
Dan Gohman
43c3db37f6 Convert tests using "grep -c ... | grep ..." to use the count script. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41100 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 13:49:33 +00:00
Dan Gohman
28beeeac4d Convert tests using "| wc -l | grep ..." to use the count script. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41097 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-15 13:36:28 +00:00
Evan Cheng
3b1d3068c3 New test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41087 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-14 23:34:50 +00:00
Lauro Ramos Venancio
f3c13c82e3 Expand unaligned loads/stores when the target doesn't support them. (PR1548) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 19:34:21 +00:00
Reid Spencer
9445e9aaa0 For PR1553: 
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40069 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 23:13:04 +00:00
Dan Gohman
2a69a04afa Add explicit triples to these tests so that llc behaves as expected on 
non-Apple hosts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38455 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-09 13:42:32 +00:00
John Criswell
e644ef7b09 Convert .cvsignore files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 16:35:07 +00:00
Dan Gohman
10a7aa6dea Fix an assertion failure in legalizing bitcast operators on targets where 
vectors are split down to single elements as part of legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37785 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-29 00:09:08 +00:00
Evan Cheng
52974eb49a Fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37693 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-21 18:22:42 +00:00
Evan Cheng
53855ca95c New tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37686 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-21 07:40:00 +00:00
Evan Cheng
60c916bc72 Added some if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37672 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-20 18:26:15 +00:00
Lauro Ramos Venancio
4f3485c0da Add a test for PR1424. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37372 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-31 18:36:07 +00:00
Evan Cheng
51d2d0780f Add a new test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37317 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-24 02:31:15 +00:00
Dale Johannesen
7e07b30e80 new testcases for -enable-tail-merge default handling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37287 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-22 17:19:23 +00:00
Chris Lattner
4b2e7acd6a testcase that crashes llc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37059 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:13:42 +00:00
Evan Cheng
0dbea33fff Test for PR1406. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37051 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 21:12:43 +00:00
Lauro Ramos Venancio
69642f11ed Enable aliases on arm-linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-14 18:32:56 +00:00
Dale Johannesen
e163e696be Another test for tail mergeing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36967 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-10 01:04:28 +00:00
Evan Cheng
7de291aa8c Can't fold bit_convert into truncating store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36963 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-09 21:54:34 +00:00
Dale Johannesen
fe252f38dd testcase for CodeGenPrepare bug fixed yesterday 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36940 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 17:44:36 +00:00
Chris Lattner
b64c2c8a2a move this out of Codegen/Generic, because it requires the ARM backend to be 
linked into llc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36919 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 02:19:56 +00:00
Evan Cheng
fd4dbf78ae Fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36913 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:50:07 +00:00
Evan Cheng
070549eb9c Add some tests for (conv (load x)) -> (load (conv*)x) xform. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36912 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-07 21:49:35 +00:00
Lauro Ramos Venancio
8f57667a5d Fix PR1390. 
Don't spill extra register to align the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 23:44:41 +00:00
Chris Lattner
2d4a5abb75 remove xfailed testcase (attached to pr) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36797 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 21:57:34 +00:00
Evan Cheng
8535072e88 Test load global in static mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36719 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-04 00:29:34 +00:00
Evan Cheng
874ebada58 New test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36717 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 23:53:36 +00:00
Dale Johannesen
4ac075c859 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 20:54:42 +00:00
Chris Lattner
f972db0f4f match a reassociated form of fnmul 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36659 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-03 00:31:40 +00:00
Evan Cheng
43d44f036c Test a dag combiner crasher. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36605 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 00:40:38 +00:00
Reid Spencer
4274e40514 For PR1370: 
Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36587 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-30 05:11:58 +00:00
Chris Lattner
93e3d8f308 update syntax 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36531 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-28 06:03:12 +00:00