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220 Commits

Author SHA1 Message Date
Tim Northover
fe37e6279e Switch to LLVM support function abs64 to keep VS2008 happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 13:15:08 +00:00
Jyotsna Verma
0f680703eb Hexagon: Disable optimizations at O0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178132 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 11:14:24 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
a8c8c45838 Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178030 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:34:22 +00:00
Jyotsna Verma
97e602b574 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-22 18:41:34 +00:00
Jyotsna Verma
cec50e6da2 Hexagon: Removed asserts regarding alignment and offset. 
We are warning the user about the alignment, so we should not assert.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-14 19:08:03 +00:00
Jakub Staszak
760fa5dc80 Cleanup #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-10 13:11:23 +00:00
Tom Stellard
3ef5383b35 DAGCombiner: Use correct value type for checking legality of BR_CC v3 
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 15:36:57 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
a4dd8d6732 Hexagon: Handle i8, i16 and i1 Var Args. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 20:28:34 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
18daead3ff Hexagon: Expand addc, adde, subc and sube. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:04:47 +00:00
Jyotsna Verma
9feabc23b3 Hexagon: Use MO operand flags to mark constant extended instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:51:42 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:42:28 +00:00
Andrew Trick
1c01af8f26 Added FIXME for future Hexagon cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176400 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-02 01:43:08 +00:00
Jyotsna Verma
ef94c6c85e Hexagon: Add constant extender support framework. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-01 17:37:13 +00:00
Andrew Trick
667754e239 Remove code copied from GenRegisterInfo.inc. 
There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-22 01:15:08 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 20:05:00 +00:00
Anshuman Dasgupta
6585d3b64b Hexagon: Expand cttz, ctlz, and ctpop for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 19:39:40 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy. 
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 21:13:59 +00:00
Jyotsna Verma
d6c98ae638 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 16:13:27 +00:00
Jyotsna Verma
383c6fc458 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with 
HexagonInstrFormats.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-19 18:18:36 +00:00
Jyotsna Verma
55a98b00c1 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-15 17:52:07 +00:00
Jyotsna Verma
84a2c2bbb5 Hexagon: Change insn class to support instruction encoding. 
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 19:57:17 +00:00
Jyotsna Verma
5e3100afef Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 18:15:29 +00:00
Anshuman Dasgupta
666e0d3bc4 Hexagon: add support for predicate-GPR copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 22:56:34 +00:00
Jyotsna Verma
f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 21:38:46 +00:00
Andrew Trick
ecb8c2ba60 MIsched: HazardRecognizers are created for each DAG. Free them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 19:22:27 +00:00
Jyotsna Verma
6b8d2026ba Hexagon: Add support to generate predicated absolute addressing mode 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
71490fa946 Extend Hexagon hardware loop generation to handle various additional cases: 
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-11 21:37:55 +00:00
Krzysztof Parzyszek
ce55d91ec9 Implement HexagonInstrInfo::analyzeCompare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-11 20:04:29 +00:00
Jyotsna Verma
1d3d2c57f5 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 19:20:45 +00:00
Jyotsna Verma
691c365aad Hexagon: Use multiclass for absolute addressing mode stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 18:15:34 +00:00
Jakob Stoklund Olesen
87b87ad8fb Move MRI liveouts to Hexagon return instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 18:08:43 +00:00
Jyotsna Verma
4210da7253 Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 16:42:24 +00:00
Jyotsna Verma
3e1635d08c Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-04 15:52:56 +00:00
Jyotsna Verma
924223c9ab Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174193 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-01 16:36:16 +00:00
Jyotsna Verma
05f52eca94 Add appropriate TSFlags to the instructions that must be always extended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-01 15:54:43 +00:00
Chad Rosier
108fb3202a [PEI] Pass the frame index operand number to the eliminateFrameIndex function. 
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-31 20:02:54 +00:00
Jyotsna Verma
9c3846c99c Use multiclass for post-increment store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:42:41 +00:00
Jyotsna Verma
30c3bbe007 Add constant extender support for MInst type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:18:50 +00:00
Evan Cheng
8688a58c53 Teach SDISel to combine fsin / fcos into a fsincos node if the following 
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
   the target provides a sincos library call.

Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.

rdar://13087969
PR13204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 02:32:37 +00:00
Andrew Trick
4e1fb18940 MIsched: Improve the interface to SchedDFS analysis (subtrees). 
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-25 06:33:57 +00:00
Jyotsna Verma
a454ffd02a Add indexed load/store instructions for offset validation check. 
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-17 18:42:37 +00:00
Dmitri Gribenko
510db8bcb9 Improve r172468: const_cast is not needed here 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172483 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 22:18:18 +00:00
David Greene
ef44c35359 Fix Another Cast 
Properly cast code to eliminate cast-away-const errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 21:04:42 +00:00
Craig Topper
a812641879 Remove more unnecessary # operators with nothing to paste proceeding them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171702 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 06:14:20 +00:00
Craig Topper
71ab7a79a7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:45:56 +00:00