6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-18 12:29:27 +00:00
Code Issues Projects Releases Wiki Activity
20,323 Commits 39 Branches 0 Tags 277 MiB
dfdd6c5d7a
Commit Graph

4325 Commits

Author SHA1 Message Date
Chris Lattner
8ca02914e5 Speed up the asm printer a lot by not printing formatted LLVM asm output 
for globals


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23608 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-03 07:08:36 +00:00
Chris Lattner
3cf8760dc5 silence some warnings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23594 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:29:36 +00:00
Chris Lattner
123557fcf0 silence a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23593 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:27:59 +00:00
Chris Lattner
dff06f4348 add patterns for float binops and fma ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23592 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:46:28 +00:00
Chris Lattner
080a4b1637 Sort the cpu and features table, so that the alpha backend doesn't fail EVERY 
compile with an assertion that the tables are not sorted!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23591 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:13:52 +00:00
Chris Lattner
43f07a4bbc another solution to the fsel issue. Instead of having 4 variants, just force 
the comparison to be 64-bits.  This is fine because extensions from float
to double are free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:07:49 +00:00
Chris Lattner
867940d1b7 fsel can take a different FP type for the comparison and for the result. As such 
split the FSEL family into 4 things instead of just two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:58:23 +00:00
Chris Lattner
7c0d664c21 fix an f32/f64 type mismatch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:37:13 +00:00
Chris Lattner
a916dd8888 Adjust to change in ctor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23585 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:23:51 +00:00
Chris Lattner
ca0a4778a8 Minor tweak to the branch selector. When emitting a two-way branch, and if 
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23582 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 23:06:26 +00:00
Chris Lattner
b91956e7f8 like the comment says, enable this 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23581 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 23:02:40 +00:00
Chris Lattner
2c1760f636 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23578 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 02:51:36 +00:00
Chris Lattner
919c032fa4 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. 
These are used to represent float and double values, and the two regclasses
contain the same physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 01:35:02 +00:00
Jim Laskey
242f2557cc Should be using flag and not chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23572 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 23:43:37 +00:00
Nate Begeman
2b5e66fc6e Remove some now-dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23571 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 21:28:27 +00:00
Andrew Lenharth
ac35cd207f subtarget support for CIX and FIX extentions (the only 2 I care about right now) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23569 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 20:24:38 +00:00
Chris Lattner
0f21fd5204 Rename MRegisterDesc -> TargetRegisterDesc for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23564 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:49:27 +00:00
Chris Lattner
863914feb5 trim down the target info structs now that we have a preferred spill register class for each callee save register 
Why is V9 maintaining these tables manually? ugh!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23561 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:38:36 +00:00
Chris Lattner
5802be13e0 constant fold these calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23558 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:16:59 +00:00
Chris Lattner
56bcae0de9 simplify this code using the new regclass info passed in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23557 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:12:38 +00:00
Chris Lattner
e4047188e7 stub out a virtual method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23554 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:55:18 +00:00
Chris Lattner
d174fe0ec3 CR registers are not used by this "target" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23552 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:43:58 +00:00
Chris Lattner
0a37960d32 these registers don't belong to any register classes, so don't mark them 
as callee save.  They can never be generated by the compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23551 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:42:24 +00:00
Chris Lattner
ef242b1ccc Now that self referential classes are supported, get rid of a work-around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23544 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 04:13:23 +00:00
Chris Lattner
b48d2cf5eb pass extra args 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23539 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:31:52 +00:00
Chris Lattner
0ffb1a56ff these methods get extra args 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23538 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:30:55 +00:00
Chris Lattner
97d5e6461a Pass extra regclasses into spilling code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:29:42 +00:00
Chris Lattner
ff201eebea Use the 32-bit version for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23534 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 00:05:05 +00:00
Chris Lattner
67ab118a6d Add a bunch of patterns for F64 FP ops, add some more integer ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:34:24 +00:00
Chris Lattner
237733e933 Remove code for patterns that are autogenerated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23532 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:33:31 +00:00
Andrew Lenharth
120ab480ab begining alpha subtarget support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23531 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 22:54:56 +00:00
Chris Lattner
c7a37a52cd tblgen autogens this pattern now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23530 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 22:37:24 +00:00
Andrew Lenharth
68fd4866de copy and paste error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23528 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 21:11:57 +00:00
Chris Lattner
221e53caea now that tblgen is smarter, this pattern is not needed. Also, tblgen 
now inverts commuted versions of ANDC/ORC with the current .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23527 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 19:29:15 +00:00
Chris Lattner
52897f827e consistency with other cases, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23524 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 17:38:52 +00:00
Chris Lattner
f13befb456 Make the JIT default to the DAG isel instead of the pattern isel, like LLC. 
The Pattern isel has some strange memory corruption issues going on. :(

This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23523 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 17:31:03 +00:00
Chris Lattner
d3d2cf52bb Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead. 
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23515 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 00:59:32 +00:00
Chris Lattner
79d0e9f3d1 Codegen ADD X, IMM -> addis/addi if needed. 
This implements PowerPC/fold-li.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23514 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 23:07:13 +00:00
Chris Lattner
d8ead9e250 Autogen MUL, move FP cases together 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23512 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:53:16 +00:00
Chris Lattner
88add100b3 disentangle FP from INT versions of div/mul 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23511 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:50:24 +00:00
Chris Lattner
4a7de219b4 Use the autogenerated matcher for ADD/SUB 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23510 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:47:28 +00:00
Chris Lattner
e025574370 add a patter for SUBFIC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23509 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:47:06 +00:00
Chris Lattner
0648ccf1e9 Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but 
not associative.  Add [SU]REM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23508 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:38:27 +00:00
Chris Lattner
615c2d0920 Add FP versions of the binary operators, keeping the int and fp worlds seperate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23506 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:29:58 +00:00
Chris Lattner
3e2bafd640 Add FP versions of the binary operators, keeping the int and fp worlds seperate. 
Though I have done extensive testing, it is possible that this will break
things in configs I can't test.  Please let me know if this causes a problem
and I'll fix it ASAP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23505 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 22:29:17 +00:00
Chris Lattner
a5cac6f6eb Mark associative nodes as associative 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23503 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 20:58:39 +00:00
Chris Lattner
645992f595 Nate pointed out that mulh[us] are commutative as well. Thanks! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23500 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 19:01:44 +00:00
Chris Lattner
6bcf1b7eed expose commutativity information 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23498 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 18:27:58 +00:00
Chris Lattner
393e138f60 All (xor *) cases are autogenerated now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23497 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 18:12:37 +00:00
Chris Lattner
cfc828a3d0 add support for missed eqv tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23496 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-28 18:10:51 +00:00