accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Removal of redundant code and formatting fixes.
Contributers: Jack Carter/Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
