Ted Kremenek
b388eb82fb
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 02:54:11 +00:00
Evan Cheng
88e3041ca6
Unbreak fast isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55685 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 01:04:47 +00:00
Evan Cheng
c3f44b0d63
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03 00:03:49 +00:00
Dale Johannesen
a619d012c1
Fix some bugs in the code sequences for atomics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 20:30:23 +00:00
Evan Cheng
95ce1178e4
Add Mac OS X compatible JIT callback routine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 07:49:03 +00:00
Evan Cheng
7602e11c32
Revamp ARM JIT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 06:52:38 +00:00
Evan Cheng
acff339e39
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 06:51:36 +00:00
Evan Cheng
3aac788365
Control flow instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 08:25:56 +00:00
Evan Cheng
3c2ee4939b
ldm / stm instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:48:18 +00:00
Evan Cheng
5d2c1cf74d
AXI2 and AXI3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:34:13 +00:00
Evan Cheng
4bbd5f8a9c
Reorganize instruction formats again; AXI1 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:19:00 +00:00
Evan Cheng
840917be2c
addrmode3 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 07:00:14 +00:00
Evan Cheng
0d14fc8cd5
Reorganize some instruction format definitions. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:51:14 +00:00
Evan Cheng
93912739c9
Rest of addrmode2 instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01 01:27:33 +00:00
Evan Cheng
17222df0ec
Addr2 word / byte load encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 19:02:21 +00:00
Evan Cheng
b7880ac470
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 18:32:16 +00:00
Gabor Greif
93c53e5583
fix a bunch of 80-col violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 15:37:04 +00:00
Bill Wendling
9440e35b98
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 02:59:23 +00:00
Bill Wendling
3156b62855
Expand for ROTR with MVT::i64.
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Dale, Could you please review this?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31 02:53:19 +00:00
Gabor Greif
92362680c1
fix some 80-col violations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 10:09:02 +00:00
Evan Cheng
b18ae3cb63
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 08:54:22 +00:00
Evan Cheng
eb9f89287e
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 02:03:58 +00:00
Dale Johannesen
ea9eedb787
Add ppc partial-word ATOMIC_CMP_SWAP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 00:08:53 +00:00
Evan Cheng
456704476f
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 23:22:12 +00:00
Evan Cheng
97af60b3ae
Use static_cast instead of C style cast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 23:21:31 +00:00
Evan Cheng
94a50da93c
Backing out 55521. Not safe.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 22:13:21 +00:00
Dale Johannesen
0e55f0678c
Add partial word version of ATOMIC_SWAP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 18:29:46 +00:00
Owen Anderson
667d8f7607
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 17:45:56 +00:00
Evan Cheng
ba705f62b1
TableGen'ing instruction encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:42:03 +00:00
Evan Cheng
612b79edc9
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:40:52 +00:00
Evan Cheng
3924f78a96
MVN is addrmode1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 07:36:24 +00:00
Evan Cheng
130966411f
More refactoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29 06:41:12 +00:00
Evan Cheng
4d46d0af58
Swap fp comparison operands and change predicate to allow load folding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:48:31 +00:00
Evan Cheng
37f25d989a
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:39:26 +00:00
Dan Gohman
99b218218c
Add a target callback for FastISel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:21:34 +00:00
Gabor Greif
327ef031ed
remove tabs, fix > 80 cols
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 23:19:51 +00:00
Gabor Greif
ba36cb5242
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 21:40:38 +00:00
Mon P Wang
5ad0bf658a
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 21:04:05 +00:00
Rafael Espindola
833a990c26
Use resize instead of reserve. Reserve doesn't change size().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 18:32:53 +00:00
Dale Johannesen
97efa36586
Implement partial-word binary atomics on ppc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 17:53:09 +00:00
Evan Cheng
66e13153bd
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 07:52:25 +00:00
Dale Johannesen
e00a8a2a2e
Split the ATOMIC NodeType's to include the size, e.g.
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ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 02:44:49 +00:00
Bill Wendling
1dd0086b06
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
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SSE2 registers as well as the MMX registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 21:32:04 +00:00
Dan Gohman
7deb17108f
Reinstate the x86-64 portion of r55190. When doing extloads into
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64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 17:33:15 +00:00
Gabor Greif
99a6cb92d1
disallow direct access to SDValue::ResNo, provide a getter instead
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 22:36:50 +00:00
Owen Anderson
a317767f0e
These assertions should be return false's instead, allowing the client to detect the failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55377 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 18:50:40 +00:00
Owen Anderson
940f83e772
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
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was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 18:03:31 +00:00
Chris Lattner
6ba50a9252
If an xmm register is referenced explicitly in an inline asm, make sure to
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assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 06:19:02 +00:00
Evan Cheng
b09c25ebf0
This is done.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55348 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 01:13:44 +00:00
Dale Johannesen
bdab93a2ef
Implement 32 & 64 bit versions of PPC atomic
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binary primitives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 22:34:37 +00:00
Evan Cheng
bdf7b5da47
80 col. violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55341 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 21:58:43 +00:00
Evan Cheng
ab6c3bb44d
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 21:27:18 +00:00
Dale Johannesen
140a8bb006
Remove PPC-specific lowering for atomics; the
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generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 21:09:52 +00:00
Dale Johannesen
65e3973dff
It's important for the cmp-and-swap to balance
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loads and stores but it's even more important for
it to store the right value.:(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55319 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 18:53:26 +00:00
Bill Wendling
cb3c51a4ae
Nevermind. This broke the bootstrap (?!).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55318 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 18:32:39 +00:00
Bill Wendling
51e05e7a99
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
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instructions on having SSE2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55317 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 18:20:52 +00:00
Evan Cheng
e7321441ac
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 04:11:42 +00:00
Bill Wendling
59b63e4a18
Temporarily reverting r55292. It's causing a bootstraping failure:
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/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-24 21:45:30 +00:00
Evan Cheng
32c727cd95
Move callseq_start above the call address load to allow load to be folded into the call node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-24 19:19:55 +00:00
Cedric Venet
d85f51abd4
Use additionnal include directory instead of ../ in #include.
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Suggested by aKor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55282 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-24 12:30:46 +00:00
Chris Lattner
944fac71e0
Switch the asmprinter (.ll) and all the stuff it requires over to
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use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55263 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-23 22:23:09 +00:00
Anton Korobeynikov
017c260944
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
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Is there way to avoid explicit target check?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55238 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-23 15:53:19 +00:00
Dan Gohman
f350b277f3
Move the point at which FastISel taps into the SelectionDAGISel
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process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-23 02:25:05 +00:00
Anton Korobeynikov
70f24c62ad
Make option variables static, so they won't cause nameclash
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55203 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 21:27:49 +00:00
Bill Wendling
449416deb6
Reverting r55190, r55191, and r55192. They broke the build with this error message:
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{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 20:51:05 +00:00
Dan Gohman
b4ae2da7e4
Anyext tweaks for x86. When extloading a value to i32 or i64, choose
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instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55190 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 19:19:31 +00:00
Dale Johannesen
f87d6c02f5
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 17:20:54 +00:00
Dale Johannesen
5f0cfa299d
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
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so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 03:49:10 +00:00
Dan Gohman
22bb31103d
Factor out the predicate check code from DAGISelEmitter.cpp
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 00:20:26 +00:00
Bill Wendling
ae0218c914
If part of the mask is "undef", then ignore it as we don't care what goes into it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55147 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 22:36:36 +00:00
Bill Wendling
e85dc49e13
Fix whitespace. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 22:35:37 +00:00
Evan Cheng
1887c1c2f9
Fix a number of byval / memcpy / memset related codegen issues.
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1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 21:00:15 +00:00
Mon P Wang
7e66510a2e
Treat floating point ST1 the same as ST0 when lowering for a call result
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55135 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 19:54:16 +00:00
Dan Gohman
509e84fa71
Add libm-oriented ISD opcodes for rounding operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 17:55:02 +00:00
Anton Korobeynikov
62990bafa3
Allow inline asm nodes with empty bodies inside JIT.
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This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55128 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 17:33:01 +00:00
Dan Gohman
ad3460c3c9
Simplify SelectRoot's interface, and factor out some common code
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from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 16:36:34 +00:00
Bill Wendling
3b32a23a90
Clean up whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55117 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 08:38:54 +00:00
Chris Lattner
1f0f37a742
unbreak the CBE on treeadd an many others.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55112 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 05:51:43 +00:00
Owen Anderson
cb37188323
Use raw_ostream throughout the AsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-21 00:14:44 +00:00
Dan Gohman
0bfa1bfbff
Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
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out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.
Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55078 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 21:27:32 +00:00
Dan Gohman
bb466331e7
Simplify FastISel's constructor argument list, make the FastISel
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class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 21:05:57 +00:00
Dan Gohman
cb0fe7c226
Clean up a dead return missed in r55055.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55057 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 15:54:46 +00:00
Dan Gohman
67ca6be16a
Tablegen generated code already tests the opcode value, so it's not
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necessary to use dyn_cast in these predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55055 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 15:24:22 +00:00
Dan Gohman
d8ed2a7184
Use cast instead of dyn_cast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55052 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 14:50:24 +00:00
Dan Gohman
1e684cf1ef
Fix comment spacing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55047 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 13:46:21 +00:00
Dale Johannesen
a99e38495f
Add remaining 64-bit atomic patterns for x86-64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55029 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 00:48:50 +00:00
Bill Wendling
5bf1b4eacd
Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.
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Just expand it like the other X-bit sub_and_fetches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55023 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 00:28:16 +00:00
Bill Wendling
108ecf3975
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
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was already present, but not hooked up to anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55018 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 23:09:18 +00:00
Dan Gohman
1adf1b03af
Instantiate FastISel for X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55011 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 21:45:35 +00:00
Dan Gohman
d9f3c480a7
The X86 target will soon have an implementation of createFastISel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55010 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 21:32:53 +00:00
Dale Johannesen
140be2dfb7
Add support for 8 and 16 bit forms of __sync
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builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 18:47:28 +00:00
Chris Lattner
23f35bc3ae
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54985 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 06:22:16 +00:00
Chris Lattner
fa7e17d379
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54964 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 00:41:02 +00:00
Chris Lattner
cd7ab05c37
remove empty file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54950 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-18 21:27:19 +00:00
Anton Korobeynikov
70053c340e
Unbreak cpp backend: upgrade output due to change in APInt API
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54942 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-18 20:03:45 +00:00
Evan Cheng
6aa3898730
ARM asm printer can't handle dwarf info yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54913 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-18 08:52:48 +00:00
Evan Cheng
0ac3fc2a61
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54903 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 19:22:34 +00:00
Gordon Henriksen
8715367182
Don't require Registry specializations to define random static variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54902 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 19:08:34 +00:00
Gordon Henriksen
5eca075b74
Rename some GC classes so that their roll will hopefully be clearer.
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In particular, Collector was confusing to implementors. Several
thought that this compile-time class was the place to implement
their runtime GC heap. Of course, it doesn't even exist at runtime.
Specifically, the renames are:
Collector -> GCStrategy
CollectorMetadata -> GCFunctionInfo
CollectorModuleMetadata -> GCModuleInfo
CollectorRegistry -> GCRegistry
Function::getCollector -> getGC (setGC, hasGC, clearGC)
Several accessors and nested types have also been renamed to be
consistent. These changes should be obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54899 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 18:44:35 +00:00
Cedric Venet
94fb5f2a70
Make it compile on VC2005:
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- update VC projects.
- Add an overload to llvm::Stream for <<, since std::hex and std::dec have type std::ios_base& (*)(std::ios_base&) in VC++. (templating the function don't work, due to ambiguities)
- add ../ on several include in X86/AsmPrinter/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54898 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 18:24:26 +00:00